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authorTakahiro <hogehoge@gachapin.jp>2020-12-08 00:08:46 -0800
committerGitHub <noreply@github.com>2020-12-08 00:08:46 -0800
commitcbeadfda33ba8bc04b620a49bda8873fd52b9f1c (patch)
tree3d47996b5392b0cb737b65a29f8d69d3a4c77885 /isa/rv64si
parent4a54e2b7d89343798fcbbdf07d9a061d8a5b651e (diff)
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Add rd=x0 test case to csr test (#308)
Diffstat (limited to 'isa/rv64si')
-rw-r--r--isa/rv64si/csr.S1
1 files changed, 1 insertions, 0 deletions
diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S
index 09494ef..daaee6a 100644
--- a/isa/rv64si/csr.S
+++ b/isa/rv64si/csr.S
@@ -48,6 +48,7 @@ RVTEST_CODE_BEGIN
TEST_CASE(20, a0, 0, csrw sscratch, zero; csrr a0, sscratch);
TEST_CASE(21, a0, 0, csrrwi a0, sscratch, 0; csrrwi a0, sscratch, 0xF);
+ TEST_CASE(22, a0, 0x1f, csrrsi x0, sscratch, 0x10; csrr a0, sscratch);
csrwi sscratch, 3
TEST_CASE( 2, a0, 3, csrr a0, sscratch);