| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2022-12-07 | zicntr: separate cycle/instret accessibility test (#439) | Chih-Min Chao | 2 | -2/+11 | |
| It is allowed that M-mode only implementation could skip cycle/instret if the Zicntr is not included. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
| 2022-06-09 | Test misaligned stores. (#397) | Tim Newsome | 3 | -0/+18 | |
| Assume that misaligned loads work correctly. Passes `make -C isa run` against spike (both with and without misaligned support). | |||||
| 2022-06-07 | Test misaligned loads. | Tim Newsome | 3 | -0/+18 | |
| Cover lh, lw, and ld (only on rv64). | |||||
| 2022-06-07 | Set TESTNUM before executing code. | Tim Newsome | 1 | -2/+1 | |
| Tests that might cause a trap during their code need TESTNUM (gp) set so the trap handler can correctly identify which test is running, and also report that to the user in case the test fails. Fix up shamt.S and csr.S to handle the new behavior. | |||||
| 2021-02-01 | Align mtvec in rv32mi-p-shamt test | Andrew Waterman | 1 | -0/+1 | |
| Resolves #323 | |||||
| 2020-11-20 | Only attempt to build tests supported by compiler | Andrew Waterman | 1 | -2/+0 | |
| Resolves #303 | |||||
| 2020-03-18 | Fix shamt.S header (#264) | Takahiro | 1 | -2/+2 | |
| 2018-08-17 | making mtvec_handler global (#150) | Srivatsa Yogendra | 1 | -0/+1 | |
| 2017-05-17 | Manually assemble bad shift amount, since assembler rejects | Andrew Waterman | 1 | -1/+1 | |
| Resolves #51 | |||||
| 2017-04-07 | Remove defunct IPI tests | Andrew Waterman | 2 | -10/+0 | |
| 2016-07-29 | Add RV32 RVC and breakpoint tests | Andrew Waterman | 2 | -1/+10 | |
| 2016-07-22 | Move rv32mi dirty bit test to rv32si | Andrew Waterman | 2 | -11/+0 | |
| 2016-07-07 | Update WFI test for priv v1.9 | Andrew Waterman | 2 | -9/+0 | |
| 2016-04-30 | ERET -> xRET; new memory map | Andrew Waterman | 2 | -10/+1 | |
| For now, we no longer build hex files, because the programs don't start at address 0. This decision will likely be revisited. | |||||
| 2016-03-10 | Add missing rv32mi/rv32si tests | Andrew Waterman | 4 | -0/+28 | |
| 2016-03-03 | Some S-mode tests really only belong in M-mode | Andrew Waterman | 4 | -8/+50 | |
| 2015-07-05 | New M-mode timers | Andrew Waterman | 1 | -4/+3 | |
| 2015-04-03 | Run RV32 tests on spike with --isa=RV32 | Andrew Waterman | 1 | -0/+2 | |
| 2015-03-25 | split out S-mode tests and M-mode tests | Yunsup Lee | 9 | -0/+81 | |
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index : riscv-tools/riscv-tests.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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