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authorAndrew Waterman <waterman@cs.berkeley.edu>2016-03-02 22:33:37 -0800
committerAndrew Waterman <waterman@cs.berkeley.edu>2016-03-03 11:03:59 -0800
commit4d1491df727e9aeb5fdfeac25c22eaf24cafb908 (patch)
tree3b3639675a9eb006a0eb7cb35d89a6ba34006cea /isa/rv32mi
parenta0a3ae4841308010c6437e0f47467af97a140cda (diff)
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Some S-mode tests really only belong in M-mode
Diffstat (limited to 'isa/rv32mi')
-rw-r--r--isa/rv32mi/Makefrag1
-rw-r--r--isa/rv32mi/illegal.S7
-rw-r--r--isa/rv32mi/ma_addr.S7
-rw-r--r--isa/rv32mi/shamt.S43
4 files changed, 50 insertions, 8 deletions
diff --git a/isa/rv32mi/Makefrag b/isa/rv32mi/Makefrag
index 7560dbc..3a5b376 100644
--- a/isa/rv32mi/Makefrag
+++ b/isa/rv32mi/Makefrag
@@ -9,6 +9,7 @@ rv32mi_sc_tests = \
ma_addr \
scall \
sbreak \
+ shamt \
timer \
rv32mi_mc_tests = \
diff --git a/isa/rv32mi/illegal.S b/isa/rv32mi/illegal.S
index c357ed7..e167c71 100644
--- a/isa/rv32mi/illegal.S
+++ b/isa/rv32mi/illegal.S
@@ -1,8 +1,7 @@
# See LICENSE for license details.
#include "riscv_test.h"
-#undef RVTEST_RV64S
-#define RVTEST_RV64S RVTEST_RV32M
-#define __MACHINE_MODE
+#undef RVTEST_RV64M
+#define RVTEST_RV64M RVTEST_RV32M
-#include "../rv64si/illegal.S"
+#include "../rv64mi/illegal.S"
diff --git a/isa/rv32mi/ma_addr.S b/isa/rv32mi/ma_addr.S
index df5099a..7575a3f 100644
--- a/isa/rv32mi/ma_addr.S
+++ b/isa/rv32mi/ma_addr.S
@@ -1,8 +1,7 @@
# See LICENSE for license details.
#include "riscv_test.h"
-#undef RVTEST_RV64S
-#define RVTEST_RV64S RVTEST_RV32M
-#define __MACHINE_MODE
+#undef RVTEST_RV64M
+#define RVTEST_RV64M RVTEST_RV32M
-#include "../rv64si/ma_addr.S"
+#include "../rv64mi/ma_addr.S"
diff --git a/isa/rv32mi/shamt.S b/isa/rv32mi/shamt.S
new file mode 100644
index 0000000..2c92412
--- /dev/null
+++ b/isa/rv32mi/shamt.S
@@ -0,0 +1,43 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# csr.S
+#-----------------------------------------------------------------------------
+#
+# Test CSRRx and CSRRxI instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32M
+RVTEST_CODE_BEGIN
+
+ # Make sure slli with shamt[4] set is legal.
+ TEST_CASE( 2, a0, 65536, li a0, 1; slli a0, a0, 16);
+
+ # Make sure slli with shamt[5] set is not legal.
+ TEST_CASE( 3, x0, 1, slli a0, a0, 32);
+
+ TEST_PASSFAIL
+
+mtvec_handler:
+ # Trapping on test 3 is good.
+ # Note that since the test didn't complete, TESTNUM is smaller by 1.
+ li t0, 2
+ bne TESTNUM, t0, fail
+
+ # Make sure CAUSE indicates an illegal instructino.
+ csrr t0, mcause
+ li t1, CAUSE_ILLEGAL_INSTRUCTION
+ bne t0, t1, fail
+ j pass
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END