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2022-05-31Address pylint warnings. (#385)Tim Newsome6-13/+13
I'm running a newer version of pylint, and thus there are new warnings to be fixed. All very minor.
2022-05-16V implies FD now. (#382)Tim Newsome1-3/+3
Adjust test to work with that.
2021-11-12Set `riscv resume_order reversed`. (#363)Tim Newsome1-0/+2
The tests don't confirm that the order actually changes, but at least the code that does the work now is executed during the tests.
2021-10-05Remove slen. (#360)Tim Newsome3-18/+14
It's not an argument to spike anymore. Also switch testing the vector unit from multi-gdb to `-rtos hwthread`. This exposes a bug in OpenOCD (which is already fixed).
2021-05-20Test multiple heterogeneous spike instances. (#338)Tim Newsome3-22/+9
2021-05-07Test daisy chained homogeneous spike instances. (#334)Tim Newsome4-2/+89
* Test debugging multiple spikes in a daisy chain. * Hugely speed up rbb_daisychain. Now 2 dual-hart spikes are less than 4x slower than a single dual-hart spike. * WIP * Test daisy chained homogeneous spike instances. For OpenOCD, this means we're checking that we can talk to multiple TAPs. Next up is heterogeneous testing. * Enable Sv48Test. Didn't mean to disable it with this commit. * Test authentication again. Another change I hadn't meant to push...
2021-04-13Add FreeRTOS smoke tests. (#333)Tim Newsome3-4/+9
* Add FreeRTOS smoke tests. Make sure that OpenOCD can access all threads in a FreeRTOS binary on single-hart RV32 and RV64. * Also test `-rtos FreeRTOS`.
2021-01-25Smoketest that vl and vtype can be modified. (#320)Tim Newsome1-29/+0
2021-01-07Stop testing `-rtos riscv`. (#314)Tim Newsome1-20/+0
As of tomorrow that feature is officially no longer supported in OpenOCD, so stop testing it.
2020-12-31Make HiFiveUnleashed tests clean.Tim Newsome2-0/+2
HiFiveUnleashed-flash fails som address translation tests. Possibly that would be fixed when https://github.com/riscv/riscv-tests/pull/313 merges.
2020-12-14Add tests for memory sampling feature. (#300)Tim Newsome6-0/+6
2020-10-08Expose registers on all harts in openocd cfgs (#297)Samuel Obuch2-4/+10
2020-08-06Add enable_rtos_riscv (#288)Tim Newsome1-0/+2
This is now required to use `-rtos riscv`. Addresses the aside mentioned in #287.
2020-06-25Add manual hwbp test. (#283)Tim Newsome2-0/+2
Make sure OpenOCD cooperates when a user sets a trigger by writing tselect/tdata* directly.
2020-05-26Test semihosting calls (#280)Tim Newsome5-5/+14
* Add a basic semihosting test. * Need to configure semihosting on each target. * WIP * Parse "cannot insert breakpoint" message. Also use sys.exit instead of exit, per new pylint's suggestion.
2020-04-10Change slen to a value that spike supports. (#271)Tim Newsome1-1/+3
2020-02-14Add tests for vector register access (#244)Tim Newsome3-10/+13
* WIP * Add vector register smoketest. Also redo the gdb value parsing code to accommodate the more complicated way that vector registers look. * Test vector access a little more thoroughly. * Revert unnecessary changes.
2019-12-18Hardcode misa values for all spike targets. (#227)Tim Newsome8-7/+19
`make` now takes 31s, `make all` takes 1m53s. The new CheckMisa test ensures that the misa value specified in the configuration is correct.
2019-10-09Remove ocd_ prefix. (#210)Tim Newsome4-4/+4
The latest OpenOCD doesn't need (nor support) this anymore.
2019-08-02Miscellaneous minor test improvements (#199)Tim Newsome1-1/+3
* Let the debugger enable mstatus.F if necessary. * Ignore (some) gdb debug output. * Increase timeout. * Make newer version of pylint happy.
2019-07-15Use work area in spike-1 to cover CRC algorithm. (#195)Tim Newsome1-0/+2
2019-05-16Cover with/without halt groups. (#191)Tim Newsome4-5/+6
Also work with the new command line options that were renamed in https://github.com/riscv/riscv-isa-sim/pull/299
2019-04-08Test lack of abstract CSR access. (#187)Tim Newsome6-6/+9
2019-04-04Test simultaneous resume using hasel. (#186)Tim Newsome4-5/+11
Passes on spike and Arty. Won't merge until https://github.com/riscv/riscv-openocd/pull/364 merges.
2019-02-14Test `-rtos hwthread` (#178)Tim Newsome3-0/+57
* WIP * Use hwthread everywhere. * Test `-rtos hwthread`. Also tweak timeouts a bit so that we don't have ridiculous timeouts for simple operations. * Tweak timeouts so tests pass on a loaded system.
2018-12-31Add testing of run-test/idle cases.Tim Newsome6-6/+7
2018-08-29Add test case for `riscv expose_custom`.Tim Newsome9-0/+9
Only works against spike, where I've implemented some custom debug registers to test against.
2018-04-02Use `gdb_report_register_access_error enable`Tim Newsome3-0/+3
2018-03-27Test debug authentication.Tim Newsome3-3/+18
Also halt instead of reset spike targets, which tests a more complicated code path.
2018-03-01Test debugging with/without a program bufferTim Newsome3-3/+3
2018-03-01Ensure an error when reading a non-existent CSR.Tim Newsome3-0/+12
2017-12-27Test FPRs that aren't XLEN in size.Tim Newsome4-4/+6
Cover all combinations of 32,64 bit XLEN with F and FD extensions. Finishes Issue https://github.com/riscv/riscv-openocd/issues/110
2017-10-24Increase dual-core RV64 timeouts.Tim Newsome2-2/+2
I need this for CompareSections to pass when I instrument spike to be really slow.
2017-09-29Fix tests to work in multi-gdb mode.Tim Newsome9-4/+48
The Gdb class now can handle connecting to more than one gdb. It enumerates the harts across all connections, and when asked to select a hart, it transparently sends future gdb commands to the correct instance. Multicore tests still have to be aware of some differences. The main one is that when executing 'c' in RTOS mode, all harts resume, while in multi-gdb mode only the current one resumes. Additionally, gdb doesn't set breakpoints until 'c' is issued, so the hart where breakpoints are set needs to be resumed before other harts might see them.
2017-09-21Add coverage for single-core non-rtos OpenOCD.Tim Newsome4-3/+19
2017-09-19Allow multiple reset vectors.Tim Newsome2-2/+2
Some boards have jumpers that control the reset vector, and forcing them one way or another is more annoying than dealing with it in software.
2017-09-01Use 32-bit link script for 32-bit target.Tim Newsome1-1/+1
2017-08-28This file isn't ready yet.Tim Newsome1-11/+0
2017-08-28Increase remotetimeout for spike targets.Tim Newsome5-0/+15
On overloaded systems, when executing compare-sections, otherwise gdb might hit a timeout and the compare-sections code doesn't deal with it. (You get an error message complaining that 130 is not a valid hex digit.)
2017-08-28Make pylint happy.Tim Newsome2-2/+2
2017-08-28WIP multicore testing.Tim Newsome2-0/+4
2017-08-28Make the debug tests aware of multicore.Tim Newsome6-25/+35
Targets now contain an array of harts. When running a regular test, one hart is selected to run the test on while the remaining harts are parked in a safe infinite loop. There's currently only one test that tests multicore behavior, but there could be more. The infrastructure should be able to support heterogeneous multicore, but I don't have a target like that to test with.
2017-06-26Move target definition into individual files.Tim Newsome6-0/+132
Instead of defining each target in targets.py, now each target gets its own .py file. This means people can easily keep their own target files around that they may not want to put into the main test source. As part of that, I removed the freedom-u500-sim target since I assume it's only used internally at SiFive. Added a few cleanups as well: * Update README examples, mostly --sim_cmd instead of --cmd. * Allow defining misa in a target, to skip running of ExamineTarget. * Rename target.target() to target.create(), which is less confusing. * Default --sim_cmd to `spike` * Got rid of `use_fpu`, instead looking at F or D in $misa.
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