Fix tests to work in multi-gdb mode.

The Gdb class now can handle connecting to more than one gdb. It
enumerates the harts across all connections, and when asked to select a
hart, it transparently sends future gdb commands to the correct
instance.

Multicore tests still have to be aware of some differences. The main one
is that when executing 'c' in RTOS mode, all harts resume, while in
multi-gdb mode only the current one resumes. Additionally, gdb doesn't
set breakpoints until 'c' is issued, so the hart where breakpoints are
set needs to be resumed before other harts might see them.

9 files changed, 48 insertions, 4 deletions

diff --git a/debug/targets/RISC-V/spike.cfg b/debug/targets/RISC-V/spike-1.cfg
index fc20b53..fc20b53 100644
--- a/debug/targets/RISC-V/spike.cfg
+++ b/debug/targets/RISC-V/spike-1.cfg
diff --git a/debug/targets/RISC-V/spike-2.cfg b/debug/targets/RISC-V/spike-2.cfg
new file mode 100644
index 0000000..17526ec
--- /dev/null
+++ b/debug/targets/RISC-V/spike-2.cfg
@@ -0,0 +1,19 @@
+# Connect to a mult-icore RISC-V target, exposing each hart as a thread.
+adapter_khz     10000
+
+interface remote_bitbang
+remote_bitbang_host $::env(REMOTE_BITBANG_HOST)
+remote_bitbang_port $::env(REMOTE_BITBANG_PORT)
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME_0 $_CHIPNAME.cpu0
+set _TARGETNAME_1 $_CHIPNAME.cpu1
+target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid 0
+target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1
+
+gdb_report_data_abort enable
+
+init
+reset halt
diff --git a/debug/targets/RISC-V/spike-rtos.cfg b/debug/targets/RISC-V/spike-rtos.cfg
index 9b1841c..799e3cb 100644
--- a/debug/targets/RISC-V/spike-rtos.cfg
+++ b/debug/targets/RISC-V/spike-rtos.cfg
@@ -1,3 +1,4 @@
+# Connect to a mult-icore RISC-V target, exposing each hart as a thread.
 adapter_khz     10000
 
 interface remote_bitbang
diff --git a/debug/targets/RISC-V/spike32-2-rtos.py b/debug/targets/RISC-V/spike32-2-rtos.py
new file mode 100644
index 0000000..a7b9a1c
--- /dev/null
+++ b/debug/targets/RISC-V/spike32-2-rtos.py
@@ -0,0 +1,12 @@
+import targets
+import testlib
+
+import spike32  # pylint: disable=import-error
+
+class spike32_2(targets.Target):
+    harts = [spike32.spike32_hart(), spike32.spike32_hart()]
+    openocd_config_path = "spike-rtos.cfg"
+    timeout_sec = 30
+
+    def create(self):
+        return testlib.Spike(self)
diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py
index a7b9a1c..719009d 100644
--- a/debug/targets/RISC-V/spike32-2.py
+++ b/debug/targets/RISC-V/spike32-2.py
@@ -5,7 +5,7 @@ import spike32  # pylint: disable=import-error
 
 class spike32_2(targets.Target):
     harts = [spike32.spike32_hart(), spike32.spike32_hart()]
-    openocd_config_path = "spike-rtos.cfg"
+    openocd_config_path = "spike-2.cfg"
     timeout_sec = 30
 
     def create(self):
diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py
index bcb5892..809463c 100644
--- a/debug/targets/RISC-V/spike32.py
+++ b/debug/targets/RISC-V/spike32.py
@@ -11,7 +11,7 @@ class spike32_hart(targets.Hart):
 
 class spike32(targets.Target):
     harts = [spike32_hart()]
-    openocd_config_path = "spike.cfg"
+    openocd_config_path = "spike-1.cfg"
     timeout_sec = 30
 
     def create(self):
diff --git a/debug/targets/RISC-V/spike64-2-rtos.py b/debug/targets/RISC-V/spike64-2-rtos.py
new file mode 100644
index 0000000..d65d2ab
--- /dev/null
+++ b/debug/targets/RISC-V/spike64-2-rtos.py
@@ -0,0 +1,12 @@
+import targets
+import testlib
+
+import spike64  # pylint: disable=import-error
+
+class spike64_2_rtos(targets.Target):
+    harts = [spike64.spike64_hart(), spike64.spike64_hart()]
+    openocd_config_path = "spike-rtos.cfg"
+    timeout_sec = 30
+
+    def create(self):
+        return testlib.Spike(self)
diff --git a/debug/targets/RISC-V/spike64-2.py b/debug/targets/RISC-V/spike64-2.py
index 4f6f1ff..709ebbe 100644
--- a/debug/targets/RISC-V/spike64-2.py
+++ b/debug/targets/RISC-V/spike64-2.py
@@ -5,7 +5,7 @@ import spike64  # pylint: disable=import-error
 
 class spike64_2(targets.Target):
     harts = [spike64.spike64_hart(), spike64.spike64_hart()]
-    openocd_config_path = "spike-rtos.cfg"
+    openocd_config_path = "spike-2.cfg"
     timeout_sec = 30
 
     def create(self):
diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py
index 9c37f87..2cd67a5 100644
--- a/debug/targets/RISC-V/spike64.py
+++ b/debug/targets/RISC-V/spike64.py
@@ -11,7 +11,7 @@ class spike64_hart(targets.Hart):
 
 class spike64(targets.Target):
     harts = [spike64_hart()]
-    openocd_config_path = "spike.cfg"
+    openocd_config_path = "spike-1.cfg"
     timeout_sec = 30
 
     def create(self):