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| author | Tim Newsome <tim@sifive.com> | 2021-04-13 14:41:45 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-04-13 14:41:45 -0700 |
| commit | 1b05661baa79f03830f5ddefa999dc7aaf7b1ce1 (patch) | |
| tree | c3b934eea5e0522888edc7a4cf742d09afaa7512 /debug/targets/RISC-V | |
| parent | 1ce128fa78c24bb0ed399c647e7139322b5353a7 (diff) | |
| download | riscv-tests-1b05661baa79f03830f5ddefa999dc7aaf7b1ce1.zip riscv-tests-1b05661baa79f03830f5ddefa999dc7aaf7b1ce1.tar.gz riscv-tests-1b05661baa79f03830f5ddefa999dc7aaf7b1ce1.tar.bz2 | |
Add FreeRTOS smoke tests. (#333)
* Add FreeRTOS smoke tests.
Make sure that OpenOCD can access all threads in a FreeRTOS binary on
single-hart RV32 and RV64.
* Also test `-rtos FreeRTOS`.
Diffstat (limited to 'debug/targets/RISC-V')
| -rw-r--r-- | debug/targets/RISC-V/spike-1.cfg | 7 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike32.py | 3 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike64.py | 3 |
3 files changed, 9 insertions, 4 deletions
diff --git a/debug/targets/RISC-V/spike-1.cfg b/debug/targets/RISC-V/spike-1.cfg index 3bc32d1..5f11b08 100644 --- a/debug/targets/RISC-V/spike-1.cfg +++ b/debug/targets/RISC-V/spike-1.cfg @@ -8,10 +8,13 @@ set _CHIPNAME riscv jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME riscv -chain-position $_TARGETNAME +if {$::env(USE_FREERTOS)} { + target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos FreeRTOS +} else { + target create $_TARGETNAME riscv -chain-position $_TARGETNAME +} $_TARGETNAME configure -work-area-phys $::env(WORK_AREA) -work-area-size 8096 -work-area-backup 1 - gdb_report_data_abort enable gdb_report_register_access_error enable diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py index 463e7cf..381aea7 100644 --- a/debug/targets/RISC-V/spike32.py +++ b/debug/targets/RISC-V/spike32.py @@ -5,7 +5,7 @@ class spike32_hart(targets.Hart): xlen = 32 ram = 0x10000000 ram_size = 0x10000000 - bad_address = 0x10000000 - 8 + bad_address = ram - 8 instruction_hardware_breakpoint_count = 4 reset_vectors = [0x1000] link_script_path = "spike32.lds" @@ -19,6 +19,7 @@ class spike32(targets.Target): timeout_sec = 30 implements_custom_test = True support_memory_sampling = False # Needs SBA + freertos_binary = "bin/RTOSDemo32.axf" def create(self): # 64-bit FPRs on 32-bit target diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py index cdb67f7..c4c66c8 100644 --- a/debug/targets/RISC-V/spike64.py +++ b/debug/targets/RISC-V/spike64.py @@ -5,7 +5,7 @@ class spike64_hart(targets.Hart): xlen = 64 ram = 0x1212340000 ram_size = 0x10000000 - bad_address = 0x1212340000 - 8 + bad_address = ram - 8 instruction_hardware_breakpoint_count = 4 reset_vectors = [0x1000] link_script_path = "spike64.lds" @@ -18,6 +18,7 @@ class spike64(targets.Target): openocd_config_path = "spike-1.cfg" timeout_sec = 30 implements_custom_test = True + freertos_binary = "bin/RTOSDemo64.axf" def create(self): # 32-bit FPRs only |