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| author | Tim Newsome <tim@sifive.com> | 2019-04-04 11:40:08 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-04 11:40:08 -0700 |
| commit | 74aecdcce266d2d7f73df415cb83b6e7816e0dc5 (patch) | |
| tree | d712af2e9f68d10fafbcaf64176f5aae7411e622 /debug/targets/RISC-V | |
| parent | 91b6f8fdda47323fd6af16320b6560d325ac6317 (diff) | |
| download | riscv-tests-74aecdcce266d2d7f73df415cb83b6e7816e0dc5.zip riscv-tests-74aecdcce266d2d7f73df415cb83b6e7816e0dc5.tar.gz riscv-tests-74aecdcce266d2d7f73df415cb83b6e7816e0dc5.tar.bz2 | |
Test simultaneous resume using hasel. (#186)
Passes on spike and Arty. Won't merge until
https://github.com/riscv/riscv-openocd/pull/364 merges.
Diffstat (limited to 'debug/targets/RISC-V')
| -rw-r--r-- | debug/targets/RISC-V/spike32-2-hwthread.py | 3 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike32-2-rtos.py | 4 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike64-2-rtos.py | 3 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike64-2.py | 6 |
4 files changed, 11 insertions, 5 deletions
diff --git a/debug/targets/RISC-V/spike32-2-hwthread.py b/debug/targets/RISC-V/spike32-2-hwthread.py index bec68dc..333a7f2 100644 --- a/debug/targets/RISC-V/spike32-2-hwthread.py +++ b/debug/targets/RISC-V/spike32-2-hwthread.py @@ -8,6 +8,7 @@ class spike32_2(targets.Target): openocd_config_path = "spike-2-hwthread.cfg" timeout_sec = 5 implements_custom_test = True + support_hasel = False def create(self): - return testlib.Spike(self) + return testlib.Spike(self, support_hasel=False) diff --git a/debug/targets/RISC-V/spike32-2-rtos.py b/debug/targets/RISC-V/spike32-2-rtos.py index a2951c1..4b29801 100644 --- a/debug/targets/RISC-V/spike32-2-rtos.py +++ b/debug/targets/RISC-V/spike32-2-rtos.py @@ -8,6 +8,8 @@ class spike32_2(targets.Target): openocd_config_path = "spike-rtos.cfg" timeout_sec = 30 implements_custom_test = True + support_hasel = False def create(self): - return testlib.Spike(self, progbufsize=0, dmi_rti=4) + return testlib.Spike(self, progbufsize=0, dmi_rti=4, + support_hasel=False) diff --git a/debug/targets/RISC-V/spike64-2-rtos.py b/debug/targets/RISC-V/spike64-2-rtos.py index 1da7116..3e7c221 100644 --- a/debug/targets/RISC-V/spike64-2-rtos.py +++ b/debug/targets/RISC-V/spike64-2-rtos.py @@ -8,6 +8,7 @@ class spike64_2_rtos(targets.Target): openocd_config_path = "spike-rtos.cfg" timeout_sec = 60 implements_custom_test = True + support_hasel = False def create(self): - return testlib.Spike(self, abstract_rti=30) + return testlib.Spike(self, abstract_rti=30, support_hasel=False) diff --git a/debug/targets/RISC-V/spike64-2.py b/debug/targets/RISC-V/spike64-2.py index e981105..beccae3 100644 --- a/debug/targets/RISC-V/spike64-2.py +++ b/debug/targets/RISC-V/spike64-2.py @@ -6,8 +6,10 @@ import spike64 # pylint: disable=import-error class spike64_2(targets.Target): harts = [spike64.spike64_hart(), spike64.spike64_hart()] openocd_config_path = "spike-2.cfg" - timeout_sec = 60 + timeout_sec = 10 implements_custom_test = True + support_hasel = False def create(self): - return testlib.Spike(self, isa="RV64IMAFD", abstract_rti=30) + return testlib.Spike(self, isa="RV64IMAFD", abstract_rti=30, + support_hasel=False) |