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| author | Tim Newsome <tim@sifive.com> | 2022-05-31 13:25:18 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-05-31 13:25:18 -0700 |
| commit | 7530d52174988076c182a9e6cd43eca7a574925f (patch) | |
| tree | 5c3138e974f883a06f5d4117f258c608bc29ea9b /debug/targets/RISC-V | |
| parent | 3bd84bd415cd6b3ef9454df354eb2973b4e0f623 (diff) | |
| download | riscv-tests-7530d52174988076c182a9e6cd43eca7a574925f.zip riscv-tests-7530d52174988076c182a9e6cd43eca7a574925f.tar.gz riscv-tests-7530d52174988076c182a9e6cd43eca7a574925f.tar.bz2 | |
Address pylint warnings. (#385)
I'm running a newer version of pylint, and thus there are new warnings
to be fixed. All very minor.
Diffstat (limited to 'debug/targets/RISC-V')
| -rw-r--r-- | debug/targets/RISC-V/spike-multi.py | 6 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike32-2-hwthread.py | 4 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike32-2.py | 4 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike64-2-hwthread.py | 4 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike64-2-rtos.py | 4 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike64-2.py | 4 |
6 files changed, 13 insertions, 13 deletions
diff --git a/debug/targets/RISC-V/spike-multi.py b/debug/targets/RISC-V/spike-multi.py index 82de76f..571506d 100644 --- a/debug/targets/RISC-V/spike-multi.py +++ b/debug/targets/RISC-V/spike-multi.py @@ -1,9 +1,9 @@ -import targets -import testlib - import spike32 # pylint: disable=import-error import spike64 # pylint: disable=import-error +import targets +import testlib + class multispike(targets.Target): harts = [ spike32.spike32_hart(misa=0x4034112d, system=0), diff --git a/debug/targets/RISC-V/spike32-2-hwthread.py b/debug/targets/RISC-V/spike32-2-hwthread.py index d54136d..3a24269 100644 --- a/debug/targets/RISC-V/spike32-2-hwthread.py +++ b/debug/targets/RISC-V/spike32-2-hwthread.py @@ -1,8 +1,8 @@ +import spike32 # pylint: disable=import-error + import targets import testlib -import spike32 # pylint: disable=import-error - class spike32_2(targets.Target): harts = [spike32.spike32_hart(misa=0x40341129), spike32.spike32_hart(misa=0x40341129)] diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py index ca198d7..ca62610 100644 --- a/debug/targets/RISC-V/spike32-2.py +++ b/debug/targets/RISC-V/spike32-2.py @@ -1,8 +1,8 @@ +import spike32 # pylint: disable=import-error + import targets import testlib -import spike32 # pylint: disable=import-error - class spike32_2(targets.Target): harts = [spike32.spike32_hart(misa=0x40141125), spike32.spike32_hart(misa=0x40141125)] diff --git a/debug/targets/RISC-V/spike64-2-hwthread.py b/debug/targets/RISC-V/spike64-2-hwthread.py index db381d4..1ac184a 100644 --- a/debug/targets/RISC-V/spike64-2-hwthread.py +++ b/debug/targets/RISC-V/spike64-2-hwthread.py @@ -1,8 +1,8 @@ +import spike64 # pylint: disable=import-error + import targets import testlib -import spike64 # pylint: disable=import-error - class spike64_2(targets.Target): harts = [spike64.spike64_hart(misa=0x8000000000341129), spike64.spike64_hart(misa=0x8000000000341129)] diff --git a/debug/targets/RISC-V/spike64-2-rtos.py b/debug/targets/RISC-V/spike64-2-rtos.py index acb217f..33c1ff2 100644 --- a/debug/targets/RISC-V/spike64-2-rtos.py +++ b/debug/targets/RISC-V/spike64-2-rtos.py @@ -1,8 +1,8 @@ +import spike64 # pylint: disable=import-error + import targets import testlib -import spike64 # pylint: disable=import-error - class spike64_2_rtos(targets.Target): harts = [spike64.spike64_hart(misa=0x8000000000141129), spike64.spike64_hart(misa=0x8000000000141129)] diff --git a/debug/targets/RISC-V/spike64-2.py b/debug/targets/RISC-V/spike64-2.py index e710fe1..48326ad 100644 --- a/debug/targets/RISC-V/spike64-2.py +++ b/debug/targets/RISC-V/spike64-2.py @@ -1,8 +1,8 @@ +import spike64 # pylint: disable=import-error + import targets import testlib -import spike64 # pylint: disable=import-error - class spike64_2(targets.Target): harts = [spike64.spike64_hart(misa=0x8000000000141129), spike64.spike64_hart(misa=0x8000000000141129)] |