diff options
Diffstat (limited to 'tcl')
134 files changed, 1917 insertions, 315 deletions
diff --git a/tcl/board/actux3.cfg b/tcl/board/actux3.cfg index edb529c..7c2ce06 100644 --- a/tcl/board/actux3.cfg +++ b/tcl/board/actux3.cfg @@ -50,7 +50,7 @@ reset init # setup to debug u-boot in flash proc uboot_debug {} { - gdb_breakpoint_override hard + gdb breakpoint_override hard xscale vector_catch 0xFF xscale vector_table low 1 0xe59ff018 diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg index 4740471..22a38a7 100644 --- a/tcl/board/at91sam9g20-ek.cfg +++ b/tcl/board/at91sam9g20-ek.cfg @@ -43,7 +43,7 @@ proc read_register {register} { proc at91sam9g20_reset_start { } { - # Make sure that the the jtag is running slow, since there are a number of different ways the board + # Make sure that the jtag is running slow, since there are a number of different ways the board # can be configured coming into this state that can cause communication problems with the jtag # adapter. Also since this call can be made following a "reset init" where fast memory accesses # are enabled, need to temporarily shut this down so that the RSTC_MR register can be written at slower @@ -202,7 +202,7 @@ proc at91sam9g20_reset_init { } { mww 0xffffea00 0x3 mww 0x20000000 0 - # Signal normal mode using the SDRAMC_MR register and follow with a zero value write the the starting + # Signal normal mode using the SDRAMC_MR register and follow with a zero value write the starting # memory location for the SDRAM. mww 0xffffea00 0x0 diff --git a/tcl/board/digilent_anvyl.cfg b/tcl/board/digilent_anvyl.cfg new file mode 100644 index 0000000..e820028 --- /dev/null +++ b/tcl/board/digilent_anvyl.cfg @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Digilent Anvyl with Xilinx Spartan-6 FPGA +# https://digilent.com/reference/programmable-logic/anvyl/start +# Almost the same setup as the Digilent Nexys Video board or the Digilent HS1 +# adapter. +adapter driver ftdi +adapter speed 30000 + +ftdi device_desc "Digilent USB Device" +ftdi vid_pid 0x0403 0x6010 + +# channel 0 is the JTAG channel +# channel 1 is a user serial channel to pins on the FPGA +ftdi channel 0 + +# just TCK TDI TDO TMS, no reset +ftdi layout_init 0x0088 0x008b +reset_config none + +# Enable sampling on falling edge for high JTAG speeds. +ftdi tdo_sample_edge falling + +transport select jtag + +source [find cpld/xilinx-xc6s.cfg] +source [find cpld/jtagspi.cfg] diff --git a/tcl/board/digilent_nexys2.cfg b/tcl/board/digilent_nexys2.cfg new file mode 100644 index 0000000..c1c5b2a --- /dev/null +++ b/tcl/board/digilent_nexys2.cfg @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# https://digilent.com/reference/programmable-logic/nexys-2/start +# +# The Digilent Nexy2 normally requires proprietary tools to program and will +# enumerate as: +# ID 1443:0005 1443 ONBOARD USB +# +# However, the ixo-usb-jtag project provides an alternative open firmware for +# the on board programmer. When using this firmware the board will then +# enumerate as: +# ID 16c0:06ad ixo.de USB-JTAG-IF (With SerialNumber == hw_nexys) +# +# See the interface/usb-jtag.cfg for more information. + +source [find interface/usb-jtag.cfg] +source [find cpld/xilinx-xcf-s.cfg] +source [find fpga/xilinx-xc3s.cfg] + +# Usage: +# +# Load Bitstream into FPGA: +# openocd -f board/digilent_nexys2.cfg -c "init;\ +# pld load 0 bitstream.bit;\ +# shutdown" + +# Read Unique Device Identifier (DNA): +# openocd -f board/digilent_nexys2.cfg -c "init;\ +# xilinx_print_dna [xc3s_get_dna xc3s.tap];\ +# shutdown" diff --git a/tcl/board/mini2440.cfg b/tcl/board/mini2440.cfg index 85d9a35..5642cb1 100644 --- a/tcl/board/mini2440.cfg +++ b/tcl/board/mini2440.cfg @@ -128,7 +128,7 @@ reset_config trst_and_srst # GDB Setup #------------------------------------------------------------------------- - gdb_breakpoint_override hard + gdb breakpoint_override hard #------------------------------------------------ # ARM SPECIFIC diff --git a/tcl/board/mini6410.cfg b/tcl/board/mini6410.cfg index 18f9e8d..276e718 100644 --- a/tcl/board/mini6410.cfg +++ b/tcl/board/mini6410.cfg @@ -95,7 +95,7 @@ adapter srst delay 100 jtag_ntrst_delay 100 reset_config trst_and_srst -gdb_breakpoint_override hard +gdb breakpoint_override hard targets nand device $_CHIPNAME.flash s3c6400 $_CHIPNAME.cpu diff --git a/tcl/board/netgear-wg102.cfg b/tcl/board/netgear-wg102.cfg index 15f9c11..0a7dad5 100644 --- a/tcl/board/netgear-wg102.cfg +++ b/tcl/board/netgear-wg102.cfg @@ -27,7 +27,7 @@ $_TARGETNAME configure -event reset-init { # 0x00003800 - 0x07 << FLASHCTL_WST2_S # FLASHCTL_AC_8M 0x00060000 - Size of flash # FLASHCTL_E 0x00080000 - Flash bank enable (added) - # FLASHCTL_WP 0x04000000 - write protect. If used, CFI mode wont work!! + # FLASHCTL_WP 0x04000000 - write protect. If used, CFI mode won't work!! # FLASHCTL_MWx16 0x10000000 - 16bit mode. Do not use it!! # FLASHCTL_MWx8 0x00000000 - 8bit mode. mww 0xb8400000 0x000d3ce1 diff --git a/tcl/board/nordic/nrf54l15-dk.cfg b/tcl/board/nordic/nrf54l15-dk.cfg new file mode 100644 index 0000000..d785d85 --- /dev/null +++ b/tcl/board/nordic/nrf54l15-dk.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Nordic Semiconductor nRF54L15 Development kit +# https://www.nordicsemi.com/Products/Development-hardware/nRF54L15-DK +# + +source [find interface/jlink.cfg] +source [find target/nordic/nrf54l.cfg] diff --git a/tcl/board/nxp/frdm-kv11z-jlink.cfg b/tcl/board/nxp/frdm-kv11z-jlink.cfg new file mode 100644 index 0000000..725a37b --- /dev/null +++ b/tcl/board/nxp/frdm-kv11z-jlink.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Configuration file for NXP FRDM-KV11Z development boards. +# +# This configuration file is only for FRDM-KV11Z development boards with the +# SEGGER J-Link OpenSDA firmware, see: +# https://www.segger.com/products/debug-probes/j-link/models/other-j-links/opensda-sda-v2/ + +source [find interface/jlink.cfg] + +# Set working area size to 16 KiB. +set WORKAREASIZE 0x4000 + +# Set the chip name. +set CHIPNAME kv11z + +transport select swd + +source [find target/kx.cfg] + +reset_config srst_only diff --git a/tcl/board/nxp/frdm-kv31f-jlink.cfg b/tcl/board/nxp/frdm-kv31f-jlink.cfg new file mode 100644 index 0000000..e55a01c --- /dev/null +++ b/tcl/board/nxp/frdm-kv31f-jlink.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Configuration file for NXP FRDM-KV31F development boards. +# +# This configuration file is only for FRDM-KV31F development boards with the +# SEGGER J-Link OpenSDA firmware, see: +# https://www.segger.com/products/debug-probes/j-link/models/other-j-links/opensda-sda-v2/ + +source [find interface/jlink.cfg] + +# Set working area size to 32 KiB. +set WORKAREASIZE 0x8000 + +# Set the chip name. +set CHIPNAME kv31f + +transport select swd + +source [find target/kx.cfg] + +reset_config srst_only diff --git a/tcl/board/nxp_imx8mp-evk.cfg b/tcl/board/nxp_imx8mp-evk.cfg new file mode 100644 index 0000000..4e101d4 --- /dev/null +++ b/tcl/board/nxp_imx8mp-evk.cfg @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# configuration file for NXP IMX8M Plus EVK +# + +# only JTAG supported +transport select jtag + +# set a safe JTAG clock speed, can be overridden +adapter speed 1000 + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 70 + + +# board has an i.MX8MP with 4 Cortex-A55 cores +set CHIPNAME imx8mp +set CHIPCORES 4 + +# source SoC configuration +source [find target/imx8mp.cfg] diff --git a/tcl/board/or1k_generic.cfg b/tcl/board/or1k_generic.cfg index 915a0de..b6cf3a0 100644 --- a/tcl/board/or1k_generic.cfg +++ b/tcl/board/or1k_generic.cfg @@ -22,7 +22,7 @@ poll_period 1 adapter speed 3000 # Enable the target description feature -gdb_target_description enable +gdb target_description enable # Add a new register in the cpu register list. This register will be # included in the generated target descriptor file. diff --git a/tcl/board/st_b-l475e-iot01a.cfg b/tcl/board/st_b-l475e-iot01a.cfg index e75c99d..3f3db12 100644 --- a/tcl/board/st_b-l475e-iot01a.cfg +++ b/tcl/board/st_b-l475e-iot01a.cfg @@ -6,7 +6,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd # increase working area to 96KB set WORKAREASIZE 0x18000 diff --git a/tcl/board/st_nucleo_8l152r8.cfg b/tcl/board/st_nucleo_8l152r8.cfg index 7cb8bce..681b5a2 100644 --- a/tcl/board/st_nucleo_8l152r8.cfg +++ b/tcl/board/st_nucleo_8l152r8.cfg @@ -3,7 +3,7 @@ # This is a ST NUCLEO 8L152R8 board with a single STM8L152R8T6 chip. # http://www.st.com/en/evaluation-tools/nucleo-8l152r8.html -source [find interface/stlink-dap.cfg] +source [find interface/stlink.cfg] transport select swim diff --git a/tcl/board/st_nucleo_8s208rb.cfg b/tcl/board/st_nucleo_8s208rb.cfg index 0d3c0c9..0f6bde2 100644 --- a/tcl/board/st_nucleo_8s208rb.cfg +++ b/tcl/board/st_nucleo_8s208rb.cfg @@ -3,7 +3,7 @@ # This is a ST NUCLEO 8S208RB board with a single STM8S208RBT6 chip. # https://www.st.com/en/evaluation-tools/nucleo-8s208rb.html -source [find interface/stlink-dap.cfg] +source [find interface/stlink.cfg] transport select swim diff --git a/tcl/board/st_nucleo_c0.cfg b/tcl/board/st_nucleo_c0.cfg new file mode 100644 index 0000000..7d07675 --- /dev/null +++ b/tcl/board/st_nucleo_c0.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find interface/stlink.cfg] + +transport select dapdirect_swd + +source [find target/stm32c0x.cfg] + +reset_config srst_only diff --git a/tcl/board/st_nucleo_f0.cfg b/tcl/board/st_nucleo_f0.cfg index 31a95f5..00c131f 100644 --- a/tcl/board/st_nucleo_f0.cfg +++ b/tcl/board/st_nucleo_f0.cfg @@ -10,7 +10,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd source [find target/stm32f0x.cfg] diff --git a/tcl/board/st_nucleo_f103rb.cfg b/tcl/board/st_nucleo_f103rb.cfg index 9815d45..892bdda 100644 --- a/tcl/board/st_nucleo_f103rb.cfg +++ b/tcl/board/st_nucleo_f103rb.cfg @@ -5,7 +5,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd source [find target/stm32f1x.cfg] diff --git a/tcl/board/st_nucleo_f3.cfg b/tcl/board/st_nucleo_f3.cfg index 8833724..38f49e3 100644 --- a/tcl/board/st_nucleo_f3.cfg +++ b/tcl/board/st_nucleo_f3.cfg @@ -5,7 +5,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd source [find target/stm32f3x.cfg] diff --git a/tcl/board/st_nucleo_f4.cfg b/tcl/board/st_nucleo_f4.cfg index a1908e4..7617a17 100644 --- a/tcl/board/st_nucleo_f4.cfg +++ b/tcl/board/st_nucleo_f4.cfg @@ -8,7 +8,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd source [find target/stm32f4x.cfg] diff --git a/tcl/board/st_nucleo_f7.cfg b/tcl/board/st_nucleo_f7.cfg index 9c5b36e..41f8b21 100644 --- a/tcl/board/st_nucleo_f7.cfg +++ b/tcl/board/st_nucleo_f7.cfg @@ -5,7 +5,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd source [find target/stm32f7x.cfg] diff --git a/tcl/board/st_nucleo_g0.cfg b/tcl/board/st_nucleo_g0.cfg index f8e67a0..f22a7e3 100644 --- a/tcl/board/st_nucleo_g0.cfg +++ b/tcl/board/st_nucleo_g0.cfg @@ -12,7 +12,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd source [find target/stm32g0x.cfg] diff --git a/tcl/board/st_nucleo_g4.cfg b/tcl/board/st_nucleo_g4.cfg index 8e583e7..309f7a4 100644 --- a/tcl/board/st_nucleo_g4.cfg +++ b/tcl/board/st_nucleo_g4.cfg @@ -12,7 +12,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd source [find target/stm32g4x.cfg] diff --git a/tcl/board/st_nucleo_h743zi.cfg b/tcl/board/st_nucleo_h743zi.cfg index b857b00..be2d42f 100644 --- a/tcl/board/st_nucleo_h743zi.cfg +++ b/tcl/board/st_nucleo_h743zi.cfg @@ -5,7 +5,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd source [find target/stm32h7x_dual_bank.cfg] diff --git a/tcl/board/st_nucleo_h745zi.cfg b/tcl/board/st_nucleo_h745zi.cfg index ad563b7..84865f4 100644 --- a/tcl/board/st_nucleo_h745zi.cfg +++ b/tcl/board/st_nucleo_h745zi.cfg @@ -2,7 +2,7 @@ # This is an ST NUCLEO-H745ZI-Q board with single STM32H745ZITx chip. -source [find interface/stlink-dap.cfg] +source [find interface/stlink.cfg] transport select dapdirect_swd # STM32H745xx devices are dual core (Cortex-M7 and Cortex-M4) diff --git a/tcl/board/st_nucleo_l073rz.cfg b/tcl/board/st_nucleo_l073rz.cfg index 10fac5e..317c86e 100644 --- a/tcl/board/st_nucleo_l073rz.cfg +++ b/tcl/board/st_nucleo_l073rz.cfg @@ -4,7 +4,7 @@ # http://www.st.com/en/evaluation-tools/nucleo-l073rz.html source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd set WORKAREASIZE 0x2000 diff --git a/tcl/board/st_nucleo_l1.cfg b/tcl/board/st_nucleo_l1.cfg index 50688d2..d7474d0 100644 --- a/tcl/board/st_nucleo_l1.cfg +++ b/tcl/board/st_nucleo_l1.cfg @@ -5,7 +5,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd source [find target/stm32l1x_dual_bank.cfg] diff --git a/tcl/board/st_nucleo_l4.cfg b/tcl/board/st_nucleo_l4.cfg index 8c63d8c..b0a75af 100644 --- a/tcl/board/st_nucleo_l4.cfg +++ b/tcl/board/st_nucleo_l4.cfg @@ -5,7 +5,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd source [find target/stm32l4x.cfg] diff --git a/tcl/board/st_nucleo_l5.cfg b/tcl/board/st_nucleo_l5.cfg index 6450f08..626914a 100644 --- a/tcl/board/st_nucleo_l5.cfg +++ b/tcl/board/st_nucleo_l5.cfg @@ -3,7 +3,7 @@ # This is for STM32L5 Nucleo Dev Boards. # http://www.st.com/en/evaluation-tools/stm32-mcu-nucleo.html -source [find interface/stlink-dap.cfg] +source [find interface/stlink.cfg] transport select dapdirect_swd diff --git a/tcl/board/st_nucleo_wb55.cfg b/tcl/board/st_nucleo_wb55.cfg index 29b7ec9..ab7307c 100644 --- a/tcl/board/st_nucleo_wb55.cfg +++ b/tcl/board/st_nucleo_wb55.cfg @@ -6,7 +6,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd source [find target/stm32wbx.cfg] diff --git a/tcl/board/stm320518_eval_stlink.cfg b/tcl/board/stm320518_eval_stlink.cfg index 153f7e5..997bb4a 100644 --- a/tcl/board/stm320518_eval_stlink.cfg +++ b/tcl/board/stm320518_eval_stlink.cfg @@ -8,7 +8,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd # increase working area to 8KB set WORKAREASIZE 0x2000 diff --git a/tcl/board/stm3220g_eval_stlink.cfg b/tcl/board/stm3220g_eval_stlink.cfg index d529672..4233d04 100644 --- a/tcl/board/stm3220g_eval_stlink.cfg +++ b/tcl/board/stm3220g_eval_stlink.cfg @@ -8,7 +8,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd # increase working area to 128KB set WORKAREASIZE 0x20000 diff --git a/tcl/board/stm3241g_eval_stlink.cfg b/tcl/board/stm3241g_eval_stlink.cfg index d2d5790..3bccd28 100644 --- a/tcl/board/stm3241g_eval_stlink.cfg +++ b/tcl/board/stm3241g_eval_stlink.cfg @@ -8,7 +8,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd # increase working area to 128KB set WORKAREASIZE 0x20000 diff --git a/tcl/board/stm32429i_eval_stlink.cfg b/tcl/board/stm32429i_eval_stlink.cfg index be3c482..7d04aa7 100644 --- a/tcl/board/stm32429i_eval_stlink.cfg +++ b/tcl/board/stm32429i_eval_stlink.cfg @@ -8,7 +8,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd # increase working area to 128KB set WORKAREASIZE 0x20000 diff --git a/tcl/board/stm32439i_eval_stlink.cfg b/tcl/board/stm32439i_eval_stlink.cfg index 7a1a396..b9ea084 100644 --- a/tcl/board/stm32439i_eval_stlink.cfg +++ b/tcl/board/stm32439i_eval_stlink.cfg @@ -8,7 +8,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd # increase working area to 128KB set WORKAREASIZE 0x20000 diff --git a/tcl/board/stm32f0discovery.cfg b/tcl/board/stm32f0discovery.cfg index 60fb4a6..398ecc1 100644 --- a/tcl/board/stm32f0discovery.cfg +++ b/tcl/board/stm32f0discovery.cfg @@ -5,7 +5,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd set WORKAREASIZE 0x2000 source [find target/stm32f0x.cfg] diff --git a/tcl/board/stm32f3discovery.cfg b/tcl/board/stm32f3discovery.cfg index f28e11f..73c349a 100644 --- a/tcl/board/stm32f3discovery.cfg +++ b/tcl/board/stm32f3discovery.cfg @@ -5,7 +5,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd source [find target/stm32f3x.cfg] diff --git a/tcl/board/stm32f412g-disco.cfg b/tcl/board/stm32f412g-disco.cfg index 757b25d..30a9537 100644 --- a/tcl/board/stm32f412g-disco.cfg +++ b/tcl/board/stm32f412g-disco.cfg @@ -6,7 +6,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd # increase working area to 128KB set WORKAREASIZE 0x20000 diff --git a/tcl/board/stm32f413h-disco.cfg b/tcl/board/stm32f413h-disco.cfg index 6abf495..c82d0d4 100644 --- a/tcl/board/stm32f413h-disco.cfg +++ b/tcl/board/stm32f413h-disco.cfg @@ -10,7 +10,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd # increase working area to 128KB set WORKAREASIZE 0x20000 diff --git a/tcl/board/stm32f429disc1.cfg b/tcl/board/stm32f429disc1.cfg index 657aa19..0a8e7ef 100644 --- a/tcl/board/stm32f429disc1.cfg +++ b/tcl/board/stm32f429disc1.cfg @@ -7,7 +7,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd source [find target/stm32f4x.cfg] diff --git a/tcl/board/stm32f429discovery.cfg b/tcl/board/stm32f429discovery.cfg index d1b5f5a..865602a 100644 --- a/tcl/board/stm32f429discovery.cfg +++ b/tcl/board/stm32f429discovery.cfg @@ -7,7 +7,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd # increase working area to 128KB set WORKAREASIZE 0x20000 diff --git a/tcl/board/stm32f469discovery.cfg b/tcl/board/stm32f469discovery.cfg index cca25b7..c9acbbb 100644 --- a/tcl/board/stm32f469discovery.cfg +++ b/tcl/board/stm32f469discovery.cfg @@ -7,7 +7,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd # increase working area to 128KB set WORKAREASIZE 0x20000 diff --git a/tcl/board/stm32f469i-disco.cfg b/tcl/board/stm32f469i-disco.cfg index 7ce57f6..63c42c6 100644 --- a/tcl/board/stm32f469i-disco.cfg +++ b/tcl/board/stm32f469i-disco.cfg @@ -6,7 +6,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd # increase working area to 128KB set WORKAREASIZE 0x20000 diff --git a/tcl/board/stm32f4discovery.cfg b/tcl/board/stm32f4discovery.cfg index 714f1e9..d96e2db 100644 --- a/tcl/board/stm32f4discovery.cfg +++ b/tcl/board/stm32f4discovery.cfg @@ -5,7 +5,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd # increase working area to 64KB set WORKAREASIZE 0x10000 diff --git a/tcl/board/stm32f723e-disco.cfg b/tcl/board/stm32f723e-disco.cfg index 2dee2f9..0207956 100644 --- a/tcl/board/stm32f723e-disco.cfg +++ b/tcl/board/stm32f723e-disco.cfg @@ -6,7 +6,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd # increase working area to 128KB set WORKAREASIZE 0x20000 diff --git a/tcl/board/stm32f746g-disco.cfg b/tcl/board/stm32f746g-disco.cfg index fed1d8e..75ff4ec 100644 --- a/tcl/board/stm32f746g-disco.cfg +++ b/tcl/board/stm32f746g-disco.cfg @@ -6,7 +6,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd # increase working area to 256KB set WORKAREASIZE 0x40000 diff --git a/tcl/board/stm32f769i-disco.cfg b/tcl/board/stm32f769i-disco.cfg index 2969bb9..cd6383a 100644 --- a/tcl/board/stm32f769i-disco.cfg +++ b/tcl/board/stm32f769i-disco.cfg @@ -6,7 +6,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd # increase working area to 256KB set WORKAREASIZE 0x40000 diff --git a/tcl/board/stm32f7discovery.cfg b/tcl/board/stm32f7discovery.cfg index 4cc22ea..6fd6c64 100644 --- a/tcl/board/stm32f7discovery.cfg +++ b/tcl/board/stm32f7discovery.cfg @@ -6,7 +6,7 @@ # This is for using the onboard STLINK/V2-1 source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd # increase working area to 256KB set WORKAREASIZE 0x40000 diff --git a/tcl/board/stm32h735g-disco.cfg b/tcl/board/stm32h735g-disco.cfg index 4097ae2..327a364 100644 --- a/tcl/board/stm32h735g-disco.cfg +++ b/tcl/board/stm32h735g-disco.cfg @@ -7,7 +7,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd set CHIPNAME stm32h735igk6 diff --git a/tcl/board/stm32h745i-disco.cfg b/tcl/board/stm32h745i-disco.cfg index 1c0bc67..9da1dae 100644 --- a/tcl/board/stm32h745i-disco.cfg +++ b/tcl/board/stm32h745i-disco.cfg @@ -7,7 +7,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd set CHIPNAME stm32h745xih6 diff --git a/tcl/board/stm32h747i-disco.cfg b/tcl/board/stm32h747i-disco.cfg index e0a348e..7f8eda8 100644 --- a/tcl/board/stm32h747i-disco.cfg +++ b/tcl/board/stm32h747i-disco.cfg @@ -7,7 +7,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd set CHIPNAME stm32h747xih6 diff --git a/tcl/board/stm32h750b-disco.cfg b/tcl/board/stm32h750b-disco.cfg index efb32b1..8b254f2 100644 --- a/tcl/board/stm32h750b-disco.cfg +++ b/tcl/board/stm32h750b-disco.cfg @@ -7,7 +7,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd set CHIPNAME stm32h750xbh6 diff --git a/tcl/board/stm32h7b3i-disco.cfg b/tcl/board/stm32h7b3i-disco.cfg index 58ad9f7..df0d0a6 100644 --- a/tcl/board/stm32h7b3i-disco.cfg +++ b/tcl/board/stm32h7b3i-disco.cfg @@ -7,7 +7,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd set CHIPNAME stm32h7b3lih6q diff --git a/tcl/board/stm32h7x3i_eval.cfg b/tcl/board/stm32h7x3i_eval.cfg index b9c4c74..508f10d 100644 --- a/tcl/board/stm32h7x3i_eval.cfg +++ b/tcl/board/stm32h7x3i_eval.cfg @@ -8,7 +8,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd source [find target/stm32h7x_dual_bank.cfg] diff --git a/tcl/board/stm32l0discovery.cfg b/tcl/board/stm32l0discovery.cfg index c711d9c..59aed34 100644 --- a/tcl/board/stm32l0discovery.cfg +++ b/tcl/board/stm32l0discovery.cfg @@ -5,7 +5,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd set WORKAREASIZE 0x2000 source [find target/stm32l0.cfg] diff --git a/tcl/board/stm32l476g-disco.cfg b/tcl/board/stm32l476g-disco.cfg index a32d20f..fe33ffe 100644 --- a/tcl/board/stm32l476g-disco.cfg +++ b/tcl/board/stm32l476g-disco.cfg @@ -6,7 +6,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd # increase working area to 96KB set WORKAREASIZE 0x18000 diff --git a/tcl/board/stm32l496g-disco.cfg b/tcl/board/stm32l496g-disco.cfg index 1ba2299..823fa6e 100644 --- a/tcl/board/stm32l496g-disco.cfg +++ b/tcl/board/stm32l496g-disco.cfg @@ -6,7 +6,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd # increase working area to 96KB set WORKAREASIZE 0x18000 diff --git a/tcl/board/stm32l4discovery.cfg b/tcl/board/stm32l4discovery.cfg index f089550..64a456b 100644 --- a/tcl/board/stm32l4discovery.cfg +++ b/tcl/board/stm32l4discovery.cfg @@ -8,7 +8,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd source [find target/stm32l4x.cfg] diff --git a/tcl/board/stm32l4p5g-disco.cfg b/tcl/board/stm32l4p5g-disco.cfg index 20d781a..33bb9a7 100644 --- a/tcl/board/stm32l4p5g-disco.cfg +++ b/tcl/board/stm32l4p5g-disco.cfg @@ -6,7 +6,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd # increase working area to 96KB set WORKAREASIZE 0x18000 diff --git a/tcl/board/stm32l4r9i-disco.cfg b/tcl/board/stm32l4r9i-disco.cfg index f364ad3..cbb8666 100644 --- a/tcl/board/stm32l4r9i-disco.cfg +++ b/tcl/board/stm32l4r9i-disco.cfg @@ -6,7 +6,7 @@ # This is for using the onboard STLINK source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd # increase working area to 96KB set WORKAREASIZE 0x18000 diff --git a/tcl/board/stm32ldiscovery.cfg b/tcl/board/stm32ldiscovery.cfg index d760eda..e39b522 100644 --- a/tcl/board/stm32ldiscovery.cfg +++ b/tcl/board/stm32ldiscovery.cfg @@ -5,7 +5,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd set WORKAREASIZE 0x4000 source [find target/stm32l1.cfg] diff --git a/tcl/board/stm32mp13x_dk.cfg b/tcl/board/stm32mp13x_dk.cfg index 6328ddb..08377ca 100644 --- a/tcl/board/stm32mp13x_dk.cfg +++ b/tcl/board/stm32mp13x_dk.cfg @@ -3,7 +3,7 @@ # board MB1635x # http://www.st.com/en/evaluation-tools/stm32mp135f-dk.html -source [find interface/stlink-dap.cfg] +source [find interface/stlink.cfg] transport select dapdirect_swd diff --git a/tcl/board/stm32mp15x_dk2.cfg b/tcl/board/stm32mp15x_dk2.cfg index 9503428..0e71e05 100644 --- a/tcl/board/stm32mp15x_dk2.cfg +++ b/tcl/board/stm32mp15x_dk2.cfg @@ -4,7 +4,7 @@ # http://www.st.com/en/evaluation-tools/stm32mp157a-dk1.html # http://www.st.com/en/evaluation-tools/stm32mp157c-dk2.html -source [find interface/stlink-dap.cfg] +source [find interface/stlink.cfg] transport select dapdirect_swd diff --git a/tcl/board/stm32vldiscovery.cfg b/tcl/board/stm32vldiscovery.cfg index 30e35b9..57852bf 100644 --- a/tcl/board/stm32vldiscovery.cfg +++ b/tcl/board/stm32vldiscovery.cfg @@ -5,7 +5,7 @@ source [find interface/stlink.cfg] -transport select hla_swd +transport select dapdirect_swd set WORKAREASIZE 0x2000 source [find target/stm32f1x.cfg] diff --git a/tcl/board/ti_am261_launchpad.cfg b/tcl/board/ti_am261_launchpad.cfg new file mode 100644 index 0000000..c6c4609 --- /dev/null +++ b/tcl/board/ti_am261_launchpad.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ +# +# Texas Instruments AM261 Launchpad +# https://www.ti.com/tool/LP-AM261 +# + +# AM263 Launchpad has an xds110 onboard. +source [find interface/xds110.cfg] + +transport select jtag + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 20 + +if { ![info exists SOC] } { + set SOC am261 +} + +source [find target/ti_k3.cfg] + +adapter speed 250 diff --git a/tcl/board/ti_am263p_launchpad.cfg b/tcl/board/ti_am263p_launchpad.cfg new file mode 100644 index 0000000..96e06fa --- /dev/null +++ b/tcl/board/ti_am263p_launchpad.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ +# +# Texas Instruments AM263P Launchpad +# https://www.ti.com/tool/LP-AM263P +# + +# AM263P Launchpad has an xds110 onboard. +source [find interface/xds110.cfg] + +transport select jtag + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 20 + +if { ![info exists SOC] } { + set SOC am263p +} + +source [find target/ti_k3.cfg] + +adapter speed 250 diff --git a/tcl/board/ti_am62a7_swd_native.cfg b/tcl/board/ti_am62a7_swd_native.cfg new file mode 100644 index 0000000..99fc0b0 --- /dev/null +++ b/tcl/board/ti_am62a7_swd_native.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ +# +# Texas Instruments AM62A7 +# Link: https://www.ti.com/product/AM62A7 +# +# This configuration file is used as a self hosted debug configuration that +# works on every AM62A7 platform based on firewall configuration permitted +# in the system. +# +# In this system openOCD runs on one of the CPUs inside AM62A7 and provides +# network ports that can then be used to debug the microcontrollers on the +# SoC - either self hosted IDE OR remotely. + +# We are using dmem, which uses dapdirect_swd transport +adapter driver dmem + +if { ![info exists SOC] } { + set SOC am62a7 +} + +source [find target/ti_k3.cfg] diff --git a/tcl/board/ti_am62levm.cfg b/tcl/board/ti_am62levm.cfg new file mode 100644 index 0000000..6debdd4 --- /dev/null +++ b/tcl/board/ti_am62levm.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ +# +# Texas Instruments AM62L EVM: +# Links: https://www.ti.com/tool/TMDS62LEVM +# + +# the AM62L3 EVM/SK has an xds110 onboard. +source [find interface/xds110.cfg] + +transport select jtag + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 20 + +if { ![info exists SOC] } { + set SOC am62l +} + +source [find target/ti_k3.cfg] + +adapter speed 2500 diff --git a/tcl/board/ti_am62p_swd_native.cfg b/tcl/board/ti_am62p_swd_native.cfg new file mode 100644 index 0000000..fa549f3 --- /dev/null +++ b/tcl/board/ti_am62p_swd_native.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ +# +# Texas Instruments am62p +# Link: https://www.ti.com/product/AM62P +# +# This configuration file is used as a self hosted debug configuration that +# works on every AM62P platform based on firewall configuration permitted +# in the system. +# +# In this system openOCD runs on one of the CPUs inside AM62P and provides +# network ports that can then be used to debug the microcontrollers on the +# SoC - either self hosted IDE OR remotely. + +# We are using dmem, which uses dapdirect_swd transport +adapter driver dmem + +if { ![info exists SOC] } { + set SOC am62p +} + +source [find target/ti_k3.cfg] diff --git a/tcl/board/ti_cc26x2x7_launchpad.cfg b/tcl/board/ti_cc26x2x7_launchpad.cfg new file mode 100644 index 0000000..9e6e72e --- /dev/null +++ b/tcl/board/ti_cc26x2x7_launchpad.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TI CC1352P7 LaunchPad Evaluation Kit +# +source [find interface/xds110.cfg] +adapter speed 5500 +transport select jtag +source [find target/ti_cc26x2x7.cfg] diff --git a/tcl/board/ti_j722s_swd_native.cfg b/tcl/board/ti_j722s_swd_native.cfg new file mode 100644 index 0000000..bbe0d50 --- /dev/null +++ b/tcl/board/ti_j722s_swd_native.cfg @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ +# +# Texas Instruments J722S/AM67/TDA4VEN +# Link: https://www.ti.com/product/AM67 +# Link: https://www.ti.com/product/TDA4VEN-Q1 +# +# This configuration file is used as a self hosted debug configuration that +# works on every J722S platform based on firewall configuration permitted +# in the system. +# +# In this system openOCD runs on one of the CPUs inside J722S and provides +# network ports that can then be used to debug the microcontrollers on the +# SoC - either self hosted IDE OR remotely. + +# We are using dmem, which uses dapdirect_swd transport +adapter driver dmem + +if { ![info exists SOC] } { + set SOC j722s +} + +source [find target/ti_k3.cfg] diff --git a/tcl/board/ti_mspm0_launchpad.cfg b/tcl/board/ti_mspm0_launchpad.cfg new file mode 100644 index 0000000..132fdc2 --- /dev/null +++ b/tcl/board/ti_mspm0_launchpad.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2023-2025 Texas Instruments Incorporated - https://www.ti.com/ +# +# TI MSPM0L1306 LaunchPad Evaluation Kit +# https://www.ti.com/tool/LP-MSPM0L1306 +# TI MSPM0C1104 LaunchPad Evaluation Kit +# https://www.ti.com/tool/LP-MSPM0C1104 +# TI MSPM0G3507 LaunchPad Evaluation Kit +# https://www.ti.com/tool/LP-MSPM0G3507 +# + +source [find interface/xds110.cfg] +adapter speed 10000 +source [find target/ti_mspm0.cfg] diff --git a/tcl/chip/st/spear/spear3xx_ddr.tcl b/tcl/chip/st/spear/spear3xx_ddr.tcl index 5992567..0696221 100644 --- a/tcl/chip/st/spear/spear3xx_ddr.tcl +++ b/tcl/chip/st/spear/spear3xx_ddr.tcl @@ -10,7 +10,7 @@ proc sp3xx_ddr_init {ddr_type {ddr_chips 1}} { if { $ddr_chips != 1 && $ddr_chips != 2 } { - error "Only 1 or 2 DDR chips permitted. Wrong value "$ddr_chips + error "Only 1 or 2 DDR chips permitted. Wrong value $ddr_chips" } if { $ddr_type == "mt47h64m16_3_333_cl5_async" } { @@ -21,7 +21,7 @@ proc sp3xx_ddr_init {ddr_type {ddr_chips 1}} { # ????? $ddr_chips # set ddr_size 0x????? } else { - error "sp3xx_ddr_init: unrecognized DDR type "$ddr_type + error "sp3xx_ddr_init: unrecognized DDR type $ddr_type" } # MPMC START diff --git a/tcl/cpld/xilinx-xc6s.cfg b/tcl/cpld/xilinx-xc6s.cfg index 92b2605..862c4aa 100644 --- a/tcl/cpld/xilinx-xc6s.cfg +++ b/tcl/cpld/xilinx-xc6s.cfg @@ -35,7 +35,7 @@ set XC6S_JSTART 0x0c set XC6S_BYPASS 0x3f proc xc6s_program {tap} { - echo "DEPRECATED! use 'virtex2 program ...' not 'xc6s_program'" + echo "DEPRECATED! use 'virtex2 refresh XXXX.pld' not 'xc6s_program'" global XC6S_JSHUTDOWN XC6S_JPROGRAM XC6S_JSTART XC6S_BYPASS irscan $tap $XC6S_JSHUTDOWN irscan $tap $XC6S_JPROGRAM @@ -45,7 +45,7 @@ proc xc6s_program {tap} { #xtp038 and xc3sprog approach proc xc6s_program_iprog {tap} { - echo "DEPRECATED! use 'virtex2 program ...' not 'xc6s_program_iprog'" + echo "DEPRECATED! use 'virtex2 refresh XXXX.pld' not 'xc6s_program_iprog'" global XC6S_JSHUTDOWN XC6S_JSTART XC6S_BYPASS XC6S_CFG_IN irscan $tap $XC6S_JSHUTDOWN runtest 16 diff --git a/tcl/cpld/xilinx-xc7.cfg b/tcl/cpld/xilinx-xc7.cfg index f5b0733..6f8f4ae 100644 --- a/tcl/cpld/xilinx-xc7.cfg +++ b/tcl/cpld/xilinx-xc7.cfg @@ -49,7 +49,7 @@ set XC7_JSTART 0x0c set XC7_BYPASS 0x3f proc xc7_program {tap} { - echo "DEPRECATED! use 'virtex2 program ...' not 'xc7_program'" + echo "DEPRECATED! use 'virtex2 refresh XXXX.pld' not 'xc7_program'" global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS irscan $tap $XC7_JSHUTDOWN irscan $tap $XC7_JPROGRAM diff --git a/tcl/cpld/xilinx-xcu.cfg b/tcl/cpld/xilinx-xcu.cfg index 4d7f26c..63a67da 100644 --- a/tcl/cpld/xilinx-xcu.cfg +++ b/tcl/cpld/xilinx-xcu.cfg @@ -109,7 +109,7 @@ set XCU_JSTART 0x0c set XCU_BYPASS 0x3f proc xcu_program {tap} { - echo "DEPRECATED! use 'virtex2 program ...' not 'xcu_program'" + echo "DEPRECATED! use 'virtex2 refresh XXXX.pld' not 'xcu_program'" global XCU_JSHUTDOWN XCU_JPROGRAM XCU_JSTART XCU_BYPASS irscan $tap $XCU_JSHUTDOWN irscan $tap $XCU_JPROGRAM diff --git a/tcl/fpga/altera-arriaii.cfg b/tcl/fpga/altera-arriaii.cfg index d59c182..9cf680d 100644 --- a/tcl/fpga/altera-arriaii.cfg +++ b/tcl/fpga/altera-arriaii.cfg @@ -21,11 +21,26 @@ if { [info exists CHIPNAME] } { set _CHIPNAME arriaii } -jtag newtap $_CHIPNAME tap -irlen 10 \ - -expected-id 0x025120dd -expected-id 0x025040dd \ - -expected-id 0x025020dd -expected-id 0x024810dd \ - -expected-id 0x025130dd -expected-id 0x0240a0dd \ - -expected-id 0x025030dd -expected-id 0x024820dd \ - -expected-id 0x025140dd +array set _ARRIA_2_DATA { + 0x025120dd {1227 1174 EP2AGX45} + 0x025020dd {1227 -1 EP2AGX65} + 0x025130dd {1467 -1 EP2AGX95} + 0x025030dd {1467 -1 EP2AGX125} + 0x025140dd {1971 -1 EP2AGX190} + 0x025040dd {1971 -1 EP2AGX260} + 0x024810dd {2274 -1 EP2AGZ225} + 0x0240a0dd {2682 -1 EP2AGZ300} + 0x024820dd {2682 -1 EP2AGZ350} +} + +set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version} +foreach id [array names _ARRIA_2_DATA] { + set cmd [concat "-expected-id" id] +} +eval $jtag_newtap_cmd + +source [find fpga/altera_common_init.cfg] pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family arriaii +jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_ARRIA_2_DATA}" + diff --git a/tcl/fpga/altera-cyclone10.cfg b/tcl/fpga/altera-cyclone10.cfg index 3a1bc1f..0898c74 100644 --- a/tcl/fpga/altera-cyclone10.cfg +++ b/tcl/fpga/altera-cyclone10.cfg @@ -4,31 +4,33 @@ # see: https://www.intel.com/content/www/us/en/docs/programmable/683777/current/bst-operation-control.html # and: https://www.intel.cn/content/dam/support/us/en/programmable/kdb/pdfs/literature/hb/cyclone-10/c10gx-51003.pdf -# GX085: 0x02e120dd -# GX105: 0x02e320dd -# GX150: 0x02e720dd -# GX220: 0x02ef20dd -# 10cl006: 0x020f10dd -# 10cl010: 0x020f10dd -# 10cl016: 0x020f20dd -# 10cl025: 0x020f30dd -# 10cl040: 0x020f40dd -# 10cl055: 0x020f50dd -# 10cl080: 0x020f60dd -# 10cl120: 0x020f70dd - if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { set _CHIPNAME cyclone10 } -jtag newtap $_CHIPNAME tap -irlen 10 \ - -expected-id 0x02e720dd -expected-id 0x02e120dd \ - -expected-id 0x02ef20dd -expected-id 0x02e320dd \ - -expected-id 0x020f10dd -expected-id 0x020f20dd \ - -expected-id 0x020f30dd -expected-id 0x020f40dd \ - -expected-id 0x020f50dd -expected-id 0x020f60dd \ - -expected-id 0x020f70dd +array set _CYCLONE_10_DATA { + 0x020f10dd { 603 226 10cl006_10cl010} + 0x020f20dd {1080 409 10cl016} + 0x020f30dd { 732 286 10cl025} + 0x020f40dd {1632 604 10cl040} + 0x020f50dd {1164 442 10cl055} + 0x020f60dd {1314 502 10cl080} + 0x020f70dd {1620 613 10cl120} + 0x02e120dd {1339 -1 GX085} + 0x02e320dd {1339 -1 GX105} + 0x02e720dd {1339 -1 GX150} + 0x02ef20dd {1339 -1 GX220} +} + +set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version} +foreach id [array names _CYCLONE_10_DATA] { + set cmd [concat "-expected-id" id] +} +eval $jtag_newtap_cmd + +source [find fpga/altera_common_init.cfg] -pld device intel $_CHIPNAME.tap cyclone10 +pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cyclone10 +jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_10_DATA}" diff --git a/tcl/fpga/altera-cycloneiii.cfg b/tcl/fpga/altera-cycloneiii.cfg index d9be645..b0da418 100644 --- a/tcl/fpga/altera-cycloneiii.cfg +++ b/tcl/fpga/altera-cycloneiii.cfg @@ -4,32 +4,33 @@ # see Cyclone III Device Handbook # Table 12-2: Device IDCODE for Cyclone III Device Family -#EP3C5 0x020f10dd -#EP3C10 0x020f10dd -#EP3C16 0x020f20dd -#EP3C25 0x020f30dd -#EP3C40 0x020f40dd -#EP3C55 0x020f50dd -#EP3C80 0x020f60dd -#EP3C120 0x020f70dd -#Cyclone III LS -#EP3CLS70 0x027010dd -#EP3CLS100 0x027000dd -#EP3CLS150 0x027030dd -#EP3CLS200 0x027020dd - if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { set _CHIPNAME cycloneiii } -jtag newtap $_CHIPNAME tap -irlen 10 \ - -expected-id 0x020f10dd -expected-id 0x020f20dd \ - -expected-id 0x020f30dd -expected-id 0x020f40dd \ - -expected-id 0x020f50dd -expected-id 0x020f60dd \ - -expected-id 0x020f70dd -expected-id 0x027010dd \ - -expected-id 0x027000dd -expected-id 0x027030dd \ - -expected-id 0x027020dd +array set _CYCLONE_3_DATA { + 0x020f10dd { 603 226 EP3C5_EP3C10} + 0x020f20dd {1080 409 EP3C16} + 0x020f30dd { 732 286 EP3C25} + 0x020f40dd {1632 604 EP3C40} + 0x020f50dd {1164 442 EP3C55} + 0x020f60dd {1314 502 EP3C80} + 0x020f70dd {1620 613 EP3C120} + 0x027010dd {1314 226 EP3CLS70} + 0x027000dd {1314 226 EP3CLS100} + 0x027030dd {1314 409 EP3CLS150} + 0x027020dd {1314 409 EP3CLS200} +} + +set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version} +foreach id [array names _CYCLONE_3_DATA] { + set cmd [concat "-expected-id" id] +} +eval $jtag_newtap_cmd + +source [find fpga/altera_common_init.cfg] pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cycloneiii +jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_3_DATA}" diff --git a/tcl/fpga/altera-cycloneiv.cfg b/tcl/fpga/altera-cycloneiv.cfg index 6a908e8..44eb89d 100644 --- a/tcl/fpga/altera-cycloneiv.cfg +++ b/tcl/fpga/altera-cycloneiv.cfg @@ -4,38 +4,37 @@ # see Cyclone IV Device Handbook # Table 10-2: IDCODE Information for 32-Bit Cyclone IV Devices -#EP4CE6 0x020f10dd -#EP4CE10 0x020f10dd -#EP4CE15 0x020f20dd -#EP4CE22 0x020f30dd -#EP4CE30 0x020f40dd -#EP4CE40 0x020f40dd -#EP4CE55 0x020f50dd -#EP4CE75 0x020f60dd -#EP4CE115 0x020f70dd -#EP4CGX15 0x028010dd -#EP4CGX22 0x028120dd -#EP4CGX30 (3) 0x028020dd -#EP4CGX30 (4) 0x028230dd -#EP4CGX50 0x028130dd -#EP4CGX75 0x028030dd -#EP4CGX110 0x028140dd -#EP4CGX150 0x028040dd - if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { set _CHIPNAME cycloneiv } -jtag newtap $_CHIPNAME tap -irlen 10 \ - -expected-id 0x020f10dd -expected-id 0x020f20dd \ - -expected-id 0x020f30dd -expected-id 0x020f40dd \ - -expected-id 0x020f50dd -expected-id 0x020f60dd \ - -expected-id 0x020f70dd -expected-id 0x028010dd \ - -expected-id 0x028120dd -expected-id 0x028020dd \ - -expected-id 0x028230dd -expected-id 0x028130dd \ - -expected-id 0x028030dd -expected-id 0x028140dd \ - -expected-id 0x028040dd +array set _CYCLON_4_DATA { + 0x020f10dd { 603 226 EP4CE6_EP4CE10} + 0x020f20dd {1080 409 EP4CE15} + 0x020f30dd { 732 286 EP4CE22} + 0x020f40dd {1632 604 EP4CE30_EP4CE40} + 0x020f50dd {1164 442 EP4CE55} + 0x020f60dd {1314 502 EP4CE75} + 0x020f70dd {1620 613 EP4CE115} + 0x028010dd { 260 229 EP4CGX15} + 0x028120dd { 494 463 EP4CGX22} + 0x028020dd { 494 463 EP4CGX30} + 0x028230dd {1006 943 EP4CGX30} + 0x028130dd {1006 943 EP4CGX50} + 0x028030dd {1006 943 EP4CGX75} + 0x028140dd {1495 1438 EP4CGX110} + 0x028040dd {1495 1438 EP4CGX150} +} + +set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version} +foreach id [array names _CYCLON_4_DATA] { + set cmd [concat "-expected-id" id] +} +eval $jtag_newtap_cmd + +source [find fpga/altera_common_init.cfg] pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cycloneiv +jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_4_DATA}" diff --git a/tcl/fpga/altera-cyclonev.cfg b/tcl/fpga/altera-cyclonev.cfg index 46532a5..8d19cd8 100644 --- a/tcl/fpga/altera-cyclonev.cfg +++ b/tcl/fpga/altera-cyclonev.cfg @@ -4,44 +4,36 @@ # see Cyclone V Device Handbook # Table 9-1: IDCODE Information for Cyclone V Devices -#5CEA2 0x02b150dd -#5CEA4 0x02b050dd -#5CEA5 0x02b220dd -#5CEA7 0x02b130dd -#5CEA9 0x02b140dd -#5CGXC3 0x02b010dd -#5CGXC4 0x02b120dd -#5CGXC5 0x02b020dd -#5CGXC7 0x02b030dd -#5CGXC9 0x02b040dd -#5CGTD5 0x02b020dd -#5CGTD7 0x02b030dd -#5CGTD9 0x02b040dd -#5CSEA2 0x02d110dd -#5CSEA4 0x02d010dd -#5CSEA5 0x02d120dd -#5CSEA6 0x02d020dd -#5CSXC2 0x02d110dd -#5CSXC4 0x02d010dd -#5CSXC5 0x02d120dd -#5CSXC6 0x02d020dd -#5CSTD5 0x02d120dd -#5CSTD6 0x02d020dd - - if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { set _CHIPNAME cyclonev } -jtag newtap $_CHIPNAME tap -irlen 10 \ - -expected-id 0x02b150dd -expected-id 0x02b050dd \ - -expected-id 0x02b220dd -expected-id 0x02b130dd \ - -expected-id 0x02b140dd -expected-id 0x02b010dd \ - -expected-id 0x02b120dd -expected-id 0x02b020dd \ - -expected-id 0x02b030dd -expected-id 0x02b040dd \ - -expected-id 0x02d110dd -expected-id 0x02d010dd \ - -expected-id 0x02d120dd -expected-id 0x02d020dd +array set _CYCLONE_5_DATA { + 0x02b150dd { 864 163 5CEA2} + 0x02d020dd {1485 19 5CSEA6_5CSXC6_5CSTD6} + 0x02b040dd {1728 -1 5CGXC9_5CGTD9} + 0x02b050dd { 864 163 5CEA4} + 0x02b030dd {1488 19 5CGXC7_5CGTD7} + 0x02d120dd {1485 -1 5CSEA5_5CSXC5_5CSTD5} + 0x02b220dd {1104 19 5CEA5} + 0x02b020dd {1104 19 5CGXC5_5CGTD5} + 0x02d010dd {1197 -1 5CSEA4_5CSXC4} + 0x02b120dd {1104 19 5CGXC4} + 0x02b140dd {1728 -1 5CEA9} + 0x02b010dd { 720 19 5CGXC3} + 0x02b130dd {1488 19 5CEA7} + 0x02d110dd {1197 -1 5CSEA2_5CSXC2} +} + +set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version} +foreach id [array names _CYCLONE_5_DATA] { + set cmd [concat "-expected-id" id] +} +eval $jtag_newtap_cmd + +source [find fpga/altera_common_init.cfg] pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cyclonev +jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_5_DATA}" diff --git a/tcl/fpga/altera_common_init.cfg b/tcl/fpga/altera_common_init.cfg new file mode 100644 index 0000000..683a844 --- /dev/null +++ b/tcl/fpga/altera_common_init.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +proc set_bscan_checkpos_on_setup {chipname data} { + set tapid_w_version [jtag cget $chipname.tap -idcode] + set version_mask 0x0fffffff + set tapid [format 0x%08x [expr {$tapid_w_version & $version_mask}]] + intel set_bscan $chipname.pld [lindex $data($tapid) 0] + intel set_check_pos $chipname.pld [lindex $data($tapid) 1] +} diff --git a/tcl/fpga/xilinx-dna.cfg b/tcl/fpga/xilinx-dna.cfg index 56f8c14..6b16b78 100644 --- a/tcl/fpga/xilinx-dna.cfg +++ b/tcl/fpga/xilinx-dna.cfg @@ -1,7 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-or-later +# Spartan3: Table 9-5 in https://www.xilinx.com/support/documentation/user_guides/ug332.pdf proc xilinx_dna_addr {chip} { array set addrs { + Spartan3 0x31 Spartan6 0x30 Series7 0x17 } @@ -43,3 +45,7 @@ proc xc7_get_dna {tap} { proc xc6s_get_dna {tap} { return [xilinx_get_dna $tap Spartan6] } + +proc xc3s_get_dna {tap} { + return [xilinx_get_dna $tap Spartan3] +} diff --git a/tcl/fpga/xilinx-xc3s.cfg b/tcl/fpga/xilinx-xc3s.cfg new file mode 100644 index 0000000..7c17206 --- /dev/null +++ b/tcl/fpga/xilinx-xc3s.cfg @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Xilinx Spartan3 generation +# https://www.xilinx.com/support/documentation/user_guides/ug331.pdf + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xc3s +} + +# Table 12-4 in https://www.xilinx.com/support/documentation/user_guides/ug332.pdf +# the 4 top bits (28:31) are the die stepping, ignore them. +jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \ + -expected-id 0x02210093 \ + -expected-id 0x02218093 \ + -expected-id 0x02220093 \ + -expected-id 0x02228093 \ + -expected-id 0x02230093 \ + -expected-id 0x02610093 \ + -expected-id 0x02618093 \ + -expected-id 0x02620093 \ + -expected-id 0x02628093 \ + -expected-id 0x02630093 \ + -expected-id 0x03840093 \ + -expected-id 0x0384E093 \ + -expected-id 0x01C10093 \ + -expected-id 0x01C1A093 \ + -expected-id 0x01C22093 \ + -expected-id 0x01C2E093 \ + -expected-id 0x01C3A093 \ + -expected-id 0x0140C093 \ + -expected-id 0x01414093 \ + -expected-id 0x0141C093 \ + -expected-id 0x01428093 \ + -expected-id 0x01434093 \ + -expected-id 0x01440093 \ + -expected-id 0x01448093 \ + -expected-id 0x01450093 + +pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap + +source [find fpga/xilinx-dna.cfg] diff --git a/tcl/interface/ftdi/sipeed-usb-jtag-debugger.cfg b/tcl/interface/ftdi/sipeed-usb-jtag-debugger.cfg new file mode 100644 index 0000000..8a804ec --- /dev/null +++ b/tcl/interface/ftdi/sipeed-usb-jtag-debugger.cfg @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Sipeed USB-JTAG/TTL RISC-V Debugger +# +# https://www.seeedstudio.com/Sipeed-USB-JTAG-TTL-RISC-V-Debugger-p-2910.html +# + +adapter driver ftdi +ftdi device_desc "Dual RS232" +ftdi vid_pid 0x0403 0x6010 +ftdi channel 0 + +# Every pin set as high impedance except TCK, TDI, TDO, TMS and RST +ftdi layout_init 0x0028 0x002b + +transport select jtag + +# nSRST defined on pin RST of the Debugger (pin ADBUS5 [AD5] on the FT2232D chip) +ftdi layout_signal nSRST -data 0x0020 -oe 0x0020 diff --git a/tcl/interface/nulink.cfg b/tcl/interface/nulink.cfg index 2a4bc0b..48dc20e 100644 --- a/tcl/interface/nulink.cfg +++ b/tcl/interface/nulink.cfg @@ -5,9 +5,9 @@ # adapter driver hla -hla_layout nulink -hla_device_desc "Nu-Link" -hla_vid_pid 0x0416 0x511b 0x0416 0x511c 0x0416 0x511d 0x0416 0x5200 0x0416 0x5201 +hla layout nulink +hla device_desc "Nu-Link" +hla vid_pid 0x0416 0x511b 0x0416 0x511c 0x0416 0x511d 0x0416 0x5200 0x0416 0x5201 # Only swd is supported transport select hla_swd diff --git a/tcl/interface/parport.cfg b/tcl/interface/parport.cfg index b9fceeb..8fb1c14 100644 --- a/tcl/interface/parport.cfg +++ b/tcl/interface/parport.cfg @@ -5,17 +5,6 @@ # # Addresses: 0x378/LPT1 or 0x278/LPT2 ... # +echo "DEPRECATED: use interface/parport/wiggler.cfg instead of deprecated interface/parport.cfg" -if { [info exists PARPORTADDR] } { - set _PARPORTADDR $PARPORTADDR -} else { - if {$tcl_platform(platform) eq "windows"} { - set _PARPORTADDR 0x378 - } { - set _PARPORTADDR 0 - } -} - -adapter driver parport -parport port $_PARPORTADDR -parport cable wiggler +source [find interface/parport/wiggler.cfg] diff --git a/tcl/interface/parport/dlc5.cfg b/tcl/interface/parport/dlc5.cfg new file mode 100644 index 0000000..24acea7 --- /dev/null +++ b/tcl/interface/parport/dlc5.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Xilinx Parallel Cable III 'DLC 5' (and various clones) +# +# http://www.xilinx.com/itp/xilinx4/data/docs/pac/appendixb.html +# + +if { [info exists PARPORTADDR] } { + set _PARPORTADDR $PARPORTADDR +} else { + set _PARPORTADDR 0 +} + +adapter driver parport +parport port $_PARPORTADDR +parport cable dlc5 diff --git a/tcl/interface/parport/wiggler.cfg b/tcl/interface/parport/wiggler.cfg new file mode 100644 index 0000000..b9fceeb --- /dev/null +++ b/tcl/interface/parport/wiggler.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Parallel port wiggler (many clones available) on port 0x378 +# +# Addresses: 0x378/LPT1 or 0x278/LPT2 ... +# + +if { [info exists PARPORTADDR] } { + set _PARPORTADDR $PARPORTADDR +} else { + if {$tcl_platform(platform) eq "windows"} { + set _PARPORTADDR 0x378 + } { + set _PARPORTADDR 0 + } +} + +adapter driver parport +parport port $_PARPORTADDR +parport cable wiggler diff --git a/tcl/interface/parport_dlc5.cfg b/tcl/interface/parport_dlc5.cfg index 24acea7..83f3b56 100644 --- a/tcl/interface/parport_dlc5.cfg +++ b/tcl/interface/parport_dlc5.cfg @@ -5,13 +5,6 @@ # # http://www.xilinx.com/itp/xilinx4/data/docs/pac/appendixb.html # +echo "DEPRECATED: use interface/parport/dlc5.cfg instead of deprecated interface/parport_dlc5.cfg" -if { [info exists PARPORTADDR] } { - set _PARPORTADDR $PARPORTADDR -} else { - set _PARPORTADDR 0 -} - -adapter driver parport -parport port $_PARPORTADDR -parport cable dlc5 +source [find interface/parport/dlc5.cfg] diff --git a/tcl/interface/raspberrypi-gpio-connector.cfg b/tcl/interface/raspberrypi-gpio-connector.cfg index eff73fc..af7266b 100644 --- a/tcl/interface/raspberrypi-gpio-connector.cfg +++ b/tcl/interface/raspberrypi-gpio-connector.cfg @@ -10,6 +10,12 @@ # Do not forget the GND connection, e.g. pin 20 of the GPIO header. # +if { [info exists GPIO_CHIP] } { + set _GPIO_CHIP $GPIO_CHIP +} else { + set _GPIO_CHIP 0 +} + # GPIO 25 (pin 22) previously used for TMS/SWDIO is pulled-down by default. # The JTAG/SWD specification requires pull-up at the target board # for either signal. Connecting the signal pulled-up on the target @@ -19,23 +25,23 @@ echo "Warn : TMS/SWDIO moved to GPIO 8 (pin 24). Check the wiring please!" # Each of the JTAG lines need a gpio number set: tck tms tdi tdo # Header pin numbers: 23 24 19 21 -adapter gpio tck -chip 0 11 -adapter gpio tms -chip 0 8 -adapter gpio tdi -chip 0 10 -adapter gpio tdo -chip 0 9 +adapter gpio tck -chip $_GPIO_CHIP 11 +adapter gpio tms -chip $_GPIO_CHIP 8 +adapter gpio tdi -chip $_GPIO_CHIP 10 +adapter gpio tdo -chip $_GPIO_CHIP 9 # Each of the SWD lines need a gpio number set: swclk swdio # Header pin numbers: 23 24 -adapter gpio swclk -chip 0 11 -adapter gpio swdio -chip 0 8 +adapter gpio swclk -chip $_GPIO_CHIP 11 +adapter gpio swdio -chip $_GPIO_CHIP 8 # If you define trst or srst, use appropriate reset_config # Header pin numbers: TRST - 26, SRST - 18 -# adapter gpio trst -chip 0 7 +# adapter gpio trst -chip $_GPIO_CHIP 7 # reset_config trst_only -# adapter gpio srst -chip 0 24 +# adapter gpio srst -chip $_GPIO_CHIP 24 # reset_config srst_only srst_push_pull # or if you have both connected, diff --git a/tcl/interface/raspberrypi-native.cfg b/tcl/interface/raspberrypi-native.cfg index 7224723..c80f90a 100644 --- a/tcl/interface/raspberrypi-native.cfg +++ b/tcl/interface/raspberrypi-native.cfg @@ -37,9 +37,9 @@ proc get_max_cpu_clock { default } { return $clock } - echo "WARNING: Host CPU clock unknown." - echo "WARNING: Using the highest possible value $default kHz as a safe default." - echo "WARNING: Expect JTAG/SWD clock significantly slower than requested." + echo "Warn : Host CPU clock unknown." + echo "Warn : Using the highest possible value $default kHz as a safe default." + echo "Warn : Expect JTAG/SWD clock significantly slower than requested." return $default } @@ -56,9 +56,13 @@ if {[string match *bcm2711* $compat]} { } elseif {[string match *bcm2835* $compat] || [string match *bcm2708* $compat]} { set clocks_per_timing_loop 6 set speed_offset 32 +} elseif {[string match *bcm2712* $compat]} { + echo "Error: Raspberrypi Pi 5 has moved GPIOs to PCIe connected RP1 chip." + echo "Error: Native GPIO handling is not supported, use 'raspberrypi5-gpiod.cfg'" + shutdown } else { set speed_offset 32 - echo "WARNING: Unknown type of the host SoC. Expect JTAG/SWD clock slower than requested." + echo "Warn : Unknown type of the host SoC. Expect JTAG/SWD clock slower than requested." } set clock [get_max_cpu_clock 2000000] diff --git a/tcl/interface/raspberrypi5-gpiod.cfg b/tcl/interface/raspberrypi5-gpiod.cfg new file mode 100644 index 0000000..03f3fdb --- /dev/null +++ b/tcl/interface/raspberrypi5-gpiod.cfg @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Config for Raspberry Pi 5 used as a bitbang adapter. +# https://www.raspberrypi.com/documentation/computers/raspberry-pi.html + +# Raspberry Pi 5 is not compatible with bcm2835gpio native GPIO driver. +# The linuxgpiod driver without configurable adapter speed runs at approximately +# 800 kHz (SWD writes) and 360 kHz (SWD reads) + +adapter driver linuxgpiod + +proc read_file { name } { + if {[catch {open $name r} fd]} { + return "" + } + set result [read $fd] + close $fd + return $result +} + +proc find_rp1_alias {} { + foreach f [glob -directory "/proc/device-tree/aliases" "gpio\[0-9\]"] { + if {[string match "*/rp1/*" [read_file $f]]} { + return $f + } + } +} + +set pcie_aspm [read_file /sys/module/pcie_aspm/parameters/policy] +if {![string match {*\[performance\]*} $pcie_aspm]} { + echo "Warn : Switch PCIe power saving off or the first couple of pulses gets clocked as fast as 20 MHz" + echo "Warn : Issue 'echo performance | sudo tee /sys/module/pcie_aspm/parameters/policy'" +} + +set GPIO_CHIP [string index [find_rp1_alias] end] +source [find interface/raspberrypi-gpio-connector.cfg] diff --git a/tcl/interface/spidev_example.cfg b/tcl/interface/spidev_example.cfg new file mode 100644 index 0000000..2354c78 --- /dev/null +++ b/tcl/interface/spidev_example.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Example config for using Linux spidev as a SWD adapter. + +adapter driver linuxspidev +adapter speed 3000 +spidev path "/dev/spidev0.0" +spidev mode 3 +spidev queue_entries 64 diff --git a/tcl/interface/stlink-dap.cfg b/tcl/interface/stlink-dap.cfg index 99c81c1..009fdb7 100644 --- a/tcl/interface/stlink-dap.cfg +++ b/tcl/interface/stlink-dap.cfg @@ -1,22 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-or-later -# -# STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1, STLINK-V3 in-circuit -# debugger/programmer -# -# This new interface driver creates a ST-Link wrapper for ARM-DAP named "dapdirect" -# Old ST-LINK/V1 and ST-LINK/V2 pre version V2J24 don't support "dapdirect" -# -# SWIM transport is natively supported -# +echo "WARNING: interface/stlink-dap.cfg is deprecated, please switch to interface/stlink.cfg" +source [find interface/stlink.cfg] -adapter driver st-link -st-link vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754 0x0483 0x3755 0x0483 0x3757 - -# transport select dapdirect_jtag -# transport select dapdirect_swd -# transport select swim - -# Optionally specify the serial number of usb device -# e.g. -# adapter serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f" diff --git a/tcl/interface/stlink-hla.cfg b/tcl/interface/stlink-hla.cfg new file mode 100644 index 0000000..5c4adb8 --- /dev/null +++ b/tcl/interface/stlink-hla.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1, STLINK-V3 in-circuit +# debugger/programmer +# + +echo "DEPRECATED: OpenOCD support for ST-Link HLA transport will be dropped soon!" +echo "Consider updating your ST-Link firmware to a version >= V2J24 (2015)" + +adapter driver hla +hla layout stlink +hla device_desc "ST-LINK" +hla vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754 0x0483 0x3755 0x0483 0x3757 + +# Optionally specify the serial number of ST-LINK/V2 usb device. ST-LINK/V2 +# devices seem to have serial numbers with unreadable characters. ST-LINK/V2 +# firmware version >= V2.J21.S4 recommended to avoid issues with adapter serial +# number reset issues. +# eg. +# adapter serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f" diff --git a/tcl/interface/stlink.cfg b/tcl/interface/stlink.cfg index 8578bf2..99c81c1 100644 --- a/tcl/interface/stlink.cfg +++ b/tcl/interface/stlink.cfg @@ -4,15 +4,19 @@ # STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1, STLINK-V3 in-circuit # debugger/programmer # +# This new interface driver creates a ST-Link wrapper for ARM-DAP named "dapdirect" +# Old ST-LINK/V1 and ST-LINK/V2 pre version V2J24 don't support "dapdirect" +# +# SWIM transport is natively supported +# + +adapter driver st-link +st-link vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754 0x0483 0x3755 0x0483 0x3757 -adapter driver hla -hla_layout stlink -hla_device_desc "ST-LINK" -hla_vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754 0x0483 0x3755 0x0483 0x3757 +# transport select dapdirect_jtag +# transport select dapdirect_swd +# transport select swim -# Optionally specify the serial number of ST-LINK/V2 usb device. ST-LINK/V2 -# devices seem to have serial numbers with unreadable characters. ST-LINK/V2 -# firmware version >= V2.J21.S4 recommended to avoid issues with adapter serial -# number reset issues. -# eg. +# Optionally specify the serial number of usb device +# e.g. # adapter serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f" diff --git a/tcl/interface/ti-icdi.cfg b/tcl/interface/ti-icdi.cfg index db4e1e0..c13d27e 100644 --- a/tcl/interface/ti-icdi.cfg +++ b/tcl/interface/ti-icdi.cfg @@ -10,8 +10,8 @@ # adapter driver hla -hla_layout ti-icdi -hla_vid_pid 0x1cbe 0x00fd +hla layout ti-icdi +hla vid_pid 0x1cbe 0x00fd # Optionally specify the serial number of TI-ICDI devices, for when using # multiple devices. Serial numbers can be obtained using lsusb -v diff --git a/tcl/interface/vdebug.cfg b/tcl/interface/vdebug.cfg index 7350bb9..63a5955 100644 --- a/tcl/interface/vdebug.cfg +++ b/tcl/interface/vdebug.cfg @@ -22,9 +22,9 @@ vdebug server $_VDEBUGHOST:$_VDEBUGPORT # example config listen on all interfaces, disable tcl/telnet server bindto 0.0.0.0 -#gdb_port 3333 -#telnet_port disabled -tcl_port disabled +#gdb port 3333 +#telnet port disabled +tcl port disabled # transaction batching: 0 - no batching, 1 - (default) wr, 2 - rw vdebug batching 1 diff --git a/tcl/memory.tcl b/tcl/memory.tcl index b111749..8b93b51 100644 --- a/tcl/memory.tcl +++ b/tcl/memory.tcl @@ -66,10 +66,10 @@ proc iswithin { ADDRESS BASE LEN } { proc address_info { ADDRESS } { foreach WHERE { FLASH RAM MMREGS XMEM UNKNOWN } { - if { info exists $WHERE } { + if { [info exists $WHERE] } { set lmt [set N_[set WHERE]] for { set region 0 } { $region < $lmt } { incr region } { - if { iswithin $ADDRESS $WHERE($region,BASE) $WHERE($region,LEN) } { + if { [iswithin $ADDRESS $WHERE($region,BASE) $WHERE($region,LEN)] } { return "$WHERE $region"; } } diff --git a/tcl/target/allwinner_v3s.cfg b/tcl/target/allwinner_v3s.cfg index 437bd95..6c3435e 100644 --- a/tcl/target/allwinner_v3s.cfg +++ b/tcl/target/allwinner_v3s.cfg @@ -28,7 +28,7 @@ # UART2_TX PB0 Per default disabled # UART2_RX PB1 Per default disabled # -# JTAG is enabled by default after power on on listed JTAG_* pins. So far the +# JTAG is enabled by default after power-on on listed JTAG_* pins. So far the # boot sequence is: # Time Action # 0000ms Power ON diff --git a/tcl/target/ampere_emag.cfg b/tcl/target/ampere_emag.cfg index 0b0bd9e..fd68fcd 100644 --- a/tcl/target/ampere_emag.cfg +++ b/tcl/target/ampere_emag.cfg @@ -8,7 +8,7 @@ # # Configure defaults for target -# Can be overriden in board configuration file +# Can be overridden in board configuration file # if { [info exists CHIPNAME] } { diff --git a/tcl/target/bl602.cfg b/tcl/target/bl602.cfg new file mode 100644 index 0000000..d110d3e --- /dev/null +++ b/tcl/target/bl602.cfg @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Bouffalo Labs BL602 and BL604 target +# +# https://en.bouffalolab.com/product/?type=detail&id=1 +# +# Default JTAG pins: (if not changed by eFuse configuration) +# TDO - GPIO11 +# TMS - GPIO12 +# TCK - GPIO14 +# TDI - GPIO17 +# + +if { [info exists CHIPNAME] } { + set BL602_CHIPNAME $CHIPNAME +} else { + set BL602_CHIPNAME bl602 +} + +set CPUTAPID 0x20000c05 + +# For work-area we use DTCM instead of ITCM, due ITCM is used as buffer for L1 cache and XIP +set WORKAREAADDR 0x42014000 +set WORKAREASIZE 0xC000 + +source [find target/bl602_common.cfg] + +# JTAG reset is broken. Read comment of bl602_sw_reset_hbn_wait function for more information +$_TARGETNAME configure -event reset-assert { + halt + + bl602_sw_reset_hbn_wait +} diff --git a/tcl/target/bl602_common.cfg b/tcl/target/bl602_common.cfg new file mode 100644 index 0000000..cf4bc39 --- /dev/null +++ b/tcl/target/bl602_common.cfg @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Script for Bouffalo chips with similar architecture used in BL602 +# based on SiFive E21 core + +source [find mem_helper.tcl] + +transport select jtag + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + error "you must specify a tap id" +} + +if { [info exists BL602_CHIPNAME] } { + set _CHIPNAME $BL602_CHIPNAME +} else { + error "you must specify a chip name" +} + +if { [info exists WORKAREAADDR] } { + set _WORKAREAADDR $WORKAREAADDR +} else { + error "you must specify a work area address" +} + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + error "you must specify a work area size" +} + +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME + +riscv set_mem_access sysbus +riscv set_enable_virt2phys off + +$_TARGETNAME configure -work-area-phys $_WORKAREAADDR -work-area-size $_WORKAREASIZE -work-area-backup 1 + +# Internal RC ticks on 32 MHz, so this speed should be safe to use. +adapter speed 8000 + +# Useful functions + +set dmcontrol 0x10 +set dmcontrol_dmactive [expr {1 << 0}] +set dmcontrol_ndmreset [expr {1 << 1}] +set dmcontrol_resumereq [expr {1 << 30}] +set dmcontrol_haltreq [expr {1 << 31}] + +proc bl602_restore_clock_defaults { } { + # Switch clock to internal RC32M + # In HBN_GLB, set ROOT_CLK_SEL = 0 + mmw 0x4000f030 0x0 0x00000003 + # Wait for clock switch + sleep 10 + + # GLB_REG_BCLK_DIS_FALSE + mww 0x40000ffc 0x0 + + # HCLK is RC32M, so BCLK/HCLK doesn't need divider + # In GLB_CLK_CFG0, set BCLK_DIV = 0 and HCLK_DIV = 0 + mmw 0x40000000 0x0 0x00FFFF00 + # Wait for clock to stabilize + sleep 10 +} + +# By spec, ndmreset should reset whole chip. This implementation resets only few parts of the chip. +# CTRL_PWRON_RESET register in GLB core triggers full "power-on like" reset, so we use it instead +# for full software reset. +proc bl602_sw_reset { } { + # In GLB_SWRST_CFG2, clear CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET + mmw 0x40000018 0x0 0x00000007 + + # This Software reset method resets everything, so CPU as well. + # It does that in not much good way, resulting in Debug Module being reset as well. + # This also means, that right after CPU and Debug Module are turned on, we need to + # enable Debug Module and halt CPU if needed. Additionally, we trigger this SW reset + # through system bus access directly with DMI commands, to avoid errors printed by + # OpenOCD about unsuccessful register write. + + # In GLB_SWRST_CFG2, set CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET to 1 + riscv dmi_write 0x39 0x40000018 + riscv dmi_write 0x3c 0x7 + + # We need to wait for chip to finish reset and execute BootROM + sleep 1 + + # JTAG Debug Transport Module is reset as well, so we need to get into RUN/IDLE state + runtest 10 + + # We need to enable Debug Module and halt the CPU, so we can reset Program Counter + # and to do additional clean-ups. If reset was called without halt, resume is handled + # by reset-deassert-post event handler. + + # In Debug Module Control (dmcontrol), set dmactive to 1 and then haltreq to 1 + riscv dmi_write $::dmcontrol $::dmcontrol_dmactive + riscv dmi_write $::dmcontrol [ expr {$::dmcontrol_dmactive | $::dmcontrol_haltreq} ] + + # Set Program Counter to start of BootROM + set_reg {pc 0x21000000} +} + +# On BL602 and BL702, the only way to force chip stay in BootROM (until JTAG attaches) +# is by putting infinity loop into HBN RAM (which is not reset by sw reset), and then +# configure HBN registers, which will cause BootROM to jump into our code early in BootROM. +proc bl602_sw_reset_hbn_wait {} { + # Restore clocks to defaults + bl602_restore_clock_defaults + + # In HBN RAM, write infinity loop instruction + # beq zero, zero, 0 + mww 0x40010000 0x00000063 + # In HNB, set HBN_RSV0 (Status Flag) to "EHBN" (as uint32_t) + mww 0x4000f100 0x4e424845 + # In HBN, set HBN_RSV1 (WakeUp Address) to HBN RAM address + mww 0x4000f104 0x40010000 + + # Perform software reset + bl602_sw_reset + + # Clear HBN RAM, HBN_RSV0 and HBN_RSV1 + mww 0x40010000 0x00000000 + mww 0x4000f100 0x00000000 + mww 0x4000f104 0x00000000 + + # This early jump method locks up BootROM through Trust Zone Controller. + # That means any read of BootROM returns 0xDEADBEEF. + # Only way to reset it, is through JTAG Reset, thus toggling ndmreset in dmcontrol. + riscv dmi_write $::dmcontrol [ expr {$::dmcontrol_dmactive | $::dmcontrol_ndmreset} ] + riscv dmi_write $::dmcontrol [ expr {$::dmcontrol_dmactive} ] +} + +$_TARGETNAME configure -event reset-deassert-post { + # Resume the processor if reset was triggered without halt request + if {$halt == 0} { + riscv dmi_write $::dmcontrol [ expr {$::dmcontrol_dmactive | $::dmcontrol_resumereq} ] + } +} diff --git a/tcl/target/bl702.cfg b/tcl/target/bl702.cfg new file mode 100644 index 0000000..8caf06e --- /dev/null +++ b/tcl/target/bl702.cfg @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Bouffalo Labs BL702, BL704 and BL706 target +# +# https://en.bouffalolab.com/product/?type=detail&id=8 +# +# Default JTAG pins: (if not changed by eFuse configuration) +# TMS - GPIO0 +# TDI - GPIO1 +# TCK - GPIO2 +# TDO - GPIO9 +# + +if { [info exists CHIPNAME] } { + set BL602_CHIPNAME $CHIPNAME +} else { + set BL602_CHIPNAME bl702 +} + +set CPUTAPID 0x20000e05 + +# For work-area we use DTCM instead of ITCM, due ITCM is used as buffer for L1 cache and XIP +set WORKAREAADDR 0x22014000 +set WORKAREASIZE 0xC000 + +source [find target/bl602_common.cfg] + +# JTAG reset is broken. Read comment of bl602_sw_reset_hbn_wait function for more information +$_TARGETNAME configure -event reset-assert { + halt + + bl602_sw_reset_hbn_wait +} diff --git a/tcl/target/bl702l.cfg b/tcl/target/bl702l.cfg new file mode 100644 index 0000000..467dd8c --- /dev/null +++ b/tcl/target/bl702l.cfg @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Bouffalo Labs BL702L and BL704L target +# +# https://en.bouffalolab.com/product/?type=detail&id=26 +# +# Default JTAG pins: (if not changed by eFuse configuration) +# TMS - GPIO0 +# TDI - GPIO1 +# TCK - GPIO2 +# TDO - GPIO7 +# + +if { [info exists CHIPNAME] } { + set BL602_CHIPNAME $CHIPNAME +} else { + set BL602_CHIPNAME bl702l +} + +set CPUTAPID 0x20000e05 + +# For work-area we use beginning of OCRAM, since BL702L have only ITCM, which can be taken +# by L1 cache and XIP during runtime. +set WORKAREAADDR 0x42020000 +set WORKAREASIZE 0x10000 + +source [find target/bl602_common.cfg] + +# JTAG reset is broken. Read comment of bl602_sw_reset function for more information +# On BL702L, we are forcing boot into ISP mode, so chip stays in BootROM until JTAG re-attach +$_TARGETNAME configure -event reset-assert { + halt + + # Restore clocks to defaults + bl602_restore_clock_defaults + + # In HBN_RSV2, set HBN_RELEASE_CORE to HBN_RELEASE_CORE_FLAG (4) + # and HBN_USER_BOOT_SEL to 1 (ISP) + mww 0x4000f108 0x44000000 + + # Perform software reset + bl602_sw_reset + + # Reset HBN_RSV2 so BootROM will not force ISP mode again + mww 0x4000f108 0x00000000 +} diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl index d1d3f25..ba0e4fe 100644 --- a/tcl/target/c100helper.tcl +++ b/tcl/target/c100helper.tcl @@ -176,7 +176,7 @@ proc setupAmbaClk {} { mmw $CLKCORE_AHB_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0 # wait for PLL to lock echo "Waiting for Amba PLL to lock" - while {[expr {[mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK]} == 0} { sleep 1 } + while {[mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK == 0} { sleep 1 } # remove the internal PLL bypass mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL # remove PLL from BYPASS mode using MUX @@ -250,7 +250,7 @@ proc setupArmClk {} { mmw $CLKCORE_ARM_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0 # wait for PLL to lock echo "Waiting for Amba PLL to lock" - while {[expr {[mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK]} == 0} { sleep 1 } + while {[mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK == 0} { sleep 1 } # remove the internal PLL bypass mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL # remove PLL from BYPASS mode using MUX diff --git a/tcl/target/esi32xx.cfg b/tcl/target/esi32xx.cfg index a8b0823..d29c636 100644 --- a/tcl/target/esi32xx.cfg +++ b/tcl/target/esi32xx.cfg @@ -35,4 +35,4 @@ reset_config none # The default linker scripts provided by the eSi-RISC toolchain do not # specify attributes on memory regions, which results in incorrect # application of software breakpoints by GDB. -gdb_breakpoint_override hard +gdb breakpoint_override hard diff --git a/tcl/target/esp32c2.cfg b/tcl/target/esp32c2.cfg index 42aeb0a..51de1d1 100644 --- a/tcl/target/esp32c2.cfg +++ b/tcl/target/esp32c2.cfg @@ -5,7 +5,7 @@ source [find target/esp_common.cfg] # Target specific global variables -set _CHIPNAME "riscv" +set _CHIPNAME "esp32c2" set _CPUTAPID 0x0000cc25 set _ESP_ARCH "riscv" set _ONLYCPU 1 @@ -14,7 +14,7 @@ set _ESP_SMP_BREAK 0 set _ESP_EFUSE_MAC_ADDR_REG 0x60008840 # Target specific functions should be implemented for each riscv chips. -proc riscv_wdt_disable { } { +proc esp32c2_wdt_disable { } { # Halt event can occur during config phase (before "init" is done). # Ignore it since mww commands don't work at that time. if { [string compare [command mode] config] == 0 } { @@ -32,7 +32,7 @@ proc riscv_wdt_disable { } { mww 0x600080A0 0x84B00000 } -proc riscv_soc_reset { } { +proc esp32c2_soc_reset { } { global _RISCV_DMCONTROL # This procedure does "digital system reset", i.e. resets @@ -52,7 +52,7 @@ proc riscv_soc_reset { } { sleep 10 poll # Disable the watchdogs again - riscv_wdt_disable + esp32c2_wdt_disable # Here debugger reads allresumeack and allhalted bits as set (0x330a2) # We will clean allhalted state by resuming the core. @@ -62,7 +62,7 @@ proc riscv_soc_reset { } { riscv dmi_write $_RISCV_DMCONTROL 0x80000003 } -proc riscv_memprot_is_enabled { } { +proc esp32c2_memprot_is_enabled { } { global _RISCV_ABS_CMD _RISCV_ABS_DATA0 #Â PMPADDR 0-1 covers entire valid IRAM range and PMPADDR 2-3 covers entire DRAM region diff --git a/tcl/target/esp32c3.cfg b/tcl/target/esp32c3.cfg index d266ad5..4dca653 100644 --- a/tcl/target/esp32c3.cfg +++ b/tcl/target/esp32c3.cfg @@ -5,7 +5,7 @@ source [find target/esp_common.cfg] # Target specific global variables -set _CHIPNAME "riscv" +set _CHIPNAME "esp32c3" set _CPUTAPID 0x00005c25 set _ESP_ARCH "riscv" set _ONLYCPU 1 @@ -14,7 +14,7 @@ set _ESP_SMP_BREAK 0 set _ESP_EFUSE_MAC_ADDR_REG 0x60008844 # Target specific functions should be implemented for each riscv chips. -proc riscv_wdt_disable { } { +proc esp32c3_wdt_disable { } { # Halt event can occur during config phase (before "init" is done). # Ignore it since mww commands don't work at that time. if { [string compare [command mode] config] == 0 } { @@ -36,7 +36,7 @@ proc riscv_wdt_disable { } { # This is almost identical with the esp32c2_soc_reset. #Â Will be refactored with the other common settings. -proc riscv_soc_reset { } { +proc esp32c3_soc_reset { } { global _RISCV_DMCONTROL # This procedure does "digital system reset", i.e. resets @@ -56,7 +56,7 @@ proc riscv_soc_reset { } { sleep 10 poll # Disable the watchdogs again - riscv_wdt_disable + esp32c3_wdt_disable # Here debugger reads allresumeack and allhalted bits as set (0x330a2) # We will clean allhalted state by resuming the core. @@ -66,7 +66,7 @@ proc riscv_soc_reset { } { riscv dmi_write $_RISCV_DMCONTROL 0x80000003 } -proc riscv_memprot_is_enabled { } { +proc esp32c3_memprot_is_enabled { } { # IRAM0 PMS lock, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG if { [get_mmr_bit 0x600C10A8 0] != 0 } { return 1 diff --git a/tcl/target/esp32c6.cfg b/tcl/target/esp32c6.cfg index e1ef10a..14b6a91 100644 --- a/tcl/target/esp32c6.cfg +++ b/tcl/target/esp32c6.cfg @@ -5,7 +5,7 @@ source [find target/esp_common.cfg] # Target specific global variables -set _CHIPNAME "riscv" +set _CHIPNAME "esp32c6" set _CPUTAPID 0x0000dc25 set _ESP_ARCH "riscv" set _ONLYCPU 1 @@ -14,7 +14,7 @@ set _ESP_SMP_BREAK 0 set _ESP_EFUSE_MAC_ADDR_REG 0x600B0844 # Target specific functions should be implemented for each riscv chips. -proc riscv_wdt_disable { } { +proc esp32c6_wdt_disable { } { # Halt event can occur during config phase (before "init" is done). # Ignore it since mww commands don't work at that time. if { [string compare [command mode] config] == 0 } { @@ -34,7 +34,7 @@ proc riscv_wdt_disable { } { mww 0x600b1c1c 0x40000000 } -proc riscv_soc_reset { } { +proc esp32c6_soc_reset { } { global _RISCV_DMCONTROL _RISCV_SB_CS _RISCV_SB_ADDR0 _RISCV_SB_DATA0 riscv dmi_write $_RISCV_DMCONTROL 0x80000001 @@ -59,7 +59,7 @@ proc riscv_soc_reset { } { # Here debugger reads dmstatus as 0x3a2 # Disable the watchdogs again - riscv_wdt_disable + esp32c6_wdt_disable # Here debugger reads anyhalted and allhalted bits as set (0x3a2) # We will clean allhalted state by resuming the core. @@ -69,7 +69,7 @@ proc riscv_soc_reset { } { riscv dmi_write $_RISCV_DMCONTROL 0x80000003 } -proc riscv_memprot_is_enabled { } { +proc esp32c6_memprot_is_enabled { } { global _RISCV_ABS_CMD _RISCV_ABS_DATA0 # If IRAM/DRAM split is enabled TOR address match mode is used. diff --git a/tcl/target/esp32h2.cfg b/tcl/target/esp32h2.cfg index 45f598f..b9c4f56 100644 --- a/tcl/target/esp32h2.cfg +++ b/tcl/target/esp32h2.cfg @@ -5,7 +5,7 @@ source [find target/esp_common.cfg] # Target specific global variables -set _CHIPNAME "riscv" +set _CHIPNAME "esp32h2" set _CPUTAPID 0x00010c25 set _ESP_ARCH "riscv" set _ONLYCPU 1 @@ -14,7 +14,7 @@ set _ESP_SMP_BREAK 0 set _ESP_EFUSE_MAC_ADDR_REG 0x600B0844 # Target specific functions should be implemented for each riscv chips. -proc riscv_wdt_disable { } { +proc esp32h2_wdt_disable { } { # Halt event can occur during config phase (before "init" is done). # Ignore it since mww commands don't work at that time. if { [string compare [command mode] config] == 0 } { @@ -34,7 +34,7 @@ proc riscv_wdt_disable { } { #mww 0x600b1c1c 0x84B00000 } -proc riscv_soc_reset { } { +proc esp32h2_soc_reset { } { global _RISCV_DMCONTROL _RISCV_SB_CS _RISCV_SB_ADDR0 _RISCV_SB_DATA0 riscv dmi_write $_RISCV_DMCONTROL 0x80000001 @@ -59,7 +59,7 @@ proc riscv_soc_reset { } { # Here debugger reads dmstatus as 0x3a2 # Disable the watchdogs again - riscv_wdt_disable + esp32h2_wdt_disable # Here debugger reads anyhalted and allhalted bits as set (0x3a2) # We will clean allhalted state by resuming the core. @@ -69,7 +69,7 @@ proc riscv_soc_reset { } { riscv dmi_write $_RISCV_DMCONTROL 0x80000003 } -proc riscv_memprot_is_enabled { } { +proc esp32h2_memprot_is_enabled { } { global _RISCV_ABS_CMD _RISCV_ABS_DATA0 #Â If IRAM/DRAM split is enabled, PMPADDR 5-6 will cover valid IRAM region and PMPADDR 7 will cover valid DRAM region # Only TOR mode is used for IRAM and DRAM protections. diff --git a/tcl/target/esp_common.cfg b/tcl/target/esp_common.cfg index af2f6ad..7914865 100644 --- a/tcl/target/esp_common.cfg +++ b/tcl/target/esp_common.cfg @@ -33,6 +33,7 @@ proc set_esp_common_variables { } { global _CHIPNAME _ONLYCPU _ESP_SMP_TARGET global _CPUNAME_0 _CPUNAME_1 _TARGETNAME_0 _TARGETNAME_1 _TAPNAME_0 _TAPNAME_1 global _ESP_WDT_DISABLE _ESP_SOC_RESET _ESP_MEMPROT_IS_ENABLED + global _TARGET_TYPE _ESP_ARCH # For now we support dual core at most. if { $_ONLYCPU == 1 && $_ESP_SMP_TARGET == 0} { @@ -51,6 +52,12 @@ proc set_esp_common_variables { } { set _ESP_WDT_DISABLE "${_CHIPNAME}_wdt_disable" set _ESP_SOC_RESET "${_CHIPNAME}_soc_reset" set _ESP_MEMPROT_IS_ENABLED "${_CHIPNAME}_memprot_is_enabled" + + if {$_ESP_ARCH == "riscv"} { + set _TARGET_TYPE $_ESP_ARCH + } else { + set _TARGET_TYPE $_CHIPNAME + } } proc create_esp_jtag { } { @@ -64,11 +71,11 @@ proc create_esp_jtag { } { } proc create_openocd_targets { } { - global _TARGETNAME_0 _TARGETNAME_1 _TAPNAME_0 _TAPNAME_1 _RTOS _CHIPNAME _ONLYCPU + global _TARGETNAME_0 _TARGETNAME_1 _TAPNAME_0 _TAPNAME_1 _RTOS _CHIPNAME _ONLYCPU _TARGET_TYPE - target create $_TARGETNAME_0 $_CHIPNAME -chain-position $_TAPNAME_0 -coreid 0 -rtos $_RTOS + target create $_TARGETNAME_0 $_TARGET_TYPE -chain-position $_TAPNAME_0 -coreid 0 -rtos $_RTOS if { $_ONLYCPU != 1 } { - target create $_TARGETNAME_1 $_CHIPNAME -chain-position $_TAPNAME_1 -coreid 1 -rtos $_RTOS + target create $_TARGETNAME_1 $_TARGET_TYPE -chain-position $_TAPNAME_1 -coreid 1 -rtos $_RTOS target smp $_TARGETNAME_0 $_TARGETNAME_1 } } @@ -200,7 +207,7 @@ proc configure_esp_xtensa_default_settings { } { $_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut } - gdb_breakpoint_override hard + gdb breakpoint_override hard if { [info exists _FLASH_VOLTAGE] } { $_TARGETNAME_0 $_CHIPNAME flashbootstrap $_FLASH_VOLTAGE diff --git a/tcl/target/icepick.cfg b/tcl/target/icepick.cfg index 5509532..e5d5706 100644 --- a/tcl/target/icepick.cfg +++ b/tcl/target/icepick.cfg @@ -6,7 +6,7 @@ # # Utilities for TI ICEpick-C/D used in most TI SoCs -# Details about the ICEPick are available in the the TRM for each SoC +# Details about the ICEPick are available in the TRM for each SoC # and http://processors.wiki.ti.com/index.php/ICEPICK # create "constants" diff --git a/tcl/target/imx8mp.cfg b/tcl/target/imx8mp.cfg new file mode 100644 index 0000000..bddbcfd --- /dev/null +++ b/tcl/target/imx8mp.cfg @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# configuration file for NXP i.MX8M Plus SoCs +# +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx8m +} + +if { [info exists CHIPCORES] } { + set _cores $CHIPCORES +} else { + set _cores 1 +} + +# CoreSight Debug Access Port +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x5ba00477 +} + +# the DAP tap +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \ + -expected-id $_DAP_TAPID + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.a53 +set _CTINAME $_CHIPNAME.cti + +set DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000} +set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000} + +for { set _core 0 } { $_core < $_cores } { incr _core } { + + cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \ + -baseaddr [lindex $CTIBASE $_core] + + target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \ + -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core +} + +# declare the auxiliary Cortex-M7 core on AP #4 +target create ${_CHIPNAME}.m7 cortex_m -dap ${_CHIPNAME}.dap -ap-num 4 + +# AHB-AP for direct access to soc bus +target create ${_CHIPNAME}.ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 0 + +# default target is A53 core 0 +targets $_TARGETNAME.0 diff --git a/tcl/target/ngultra.cfg b/tcl/target/ngultra.cfg index 956fdbb..9f9814f 100644 --- a/tcl/target/ngultra.cfg +++ b/tcl/target/ngultra.cfg @@ -36,12 +36,11 @@ dap create $_CHIPNAME.coresight.dap -chain-position $_CHIPNAME.coresight.cpu for { set _core 0 } { $_core < $_cores } { incr _core } { cti create cti.$_core -dap $_CHIPNAME.coresight.dap -ap-num 0 \ -baseaddr [lindex $CTIBASE $_core] -# Cores are armv8-r but works with aarch64 (since armv8-r not directly supported by openocd yet). if { $_core == 0} { - target create core.$_core aarch64 -dap $_CHIPNAME.coresight.dap \ + target create core.$_core armv8r -dap $_CHIPNAME.coresight.dap \ -ap-num 0 -dbgbase [lindex $DBGBASE $_core] -cti cti.$_core } else { - target create core.$_core aarch64 -dap $_CHIPNAME.coresight.dap \ + target create core.$_core armv8r -dap $_CHIPNAME.coresight.dap \ -ap-num 0 -dbgbase [lindex $DBGBASE $_core] -cti cti.$_core -defer-examine } } diff --git a/tcl/target/nordic/nrf54l.cfg b/tcl/target/nordic/nrf54l.cfg new file mode 100644 index 0000000..3e14055 --- /dev/null +++ b/tcl/target/nordic/nrf54l.cfg @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Nordic nRF54L series +# +# Arm Cortex-M33 processor with RISC-V coprocessor +# +# The device uses resistive RAM (RRAM) as non-volatile memory. +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME nrf54l +} + +# Work-area is a space in RAM used for flash programming, by default use 16 KiB. +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x4000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x6ba02477 +} + +# Multidrop instance ID should be configurable by FW in TAD TINSTANCE register. +# Writes to the register are ignored due to a silicon erratum. +if { [info exists SWD_INSTANCE_ID] } { + set _SWD_INSTANCE_ID $SWD_INSTANCE_ID +} else { + set _SWD_INSTANCE_ID 0 +} + +transport select swd + +swd newdap $_CHIPNAME cpu -expected-id $_CPUTAPID + +if { [info exists SWD_MULTIDROP] } { + dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -dp-id 0x001c0289 -instance-id $_SWD_INSTANCE_ID +} else { + dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap -ap-num 0 + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# Create target for the AUX access port (AUX-AP). +target create $_CHIPNAME.aux mem_ap -dap $_CHIPNAME.dap -ap-num 1 + +# AUX-AP is accessible only if CSW Prot[0] bit (Data Access) is set +$_CHIPNAME.dap apsel 1 +$_CHIPNAME.dap apcsw 0x01000000 0x01000000 + +adapter speed 1000 + +# Use main processor as default target. +targets $_TARGETNAME + +if {![using_hla]} { + $_TARGETNAME cortex_m reset_config sysresetreq +} diff --git a/tcl/target/nrf53.cfg b/tcl/target/nrf53.cfg new file mode 100644 index 0000000..307df90 --- /dev/null +++ b/tcl/target/nrf53.cfg @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Nordic nRF53 series: dual ARM Cortex-M33, multidrop SWD +# + +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME nrf53 +} + +# Work-area is a space in RAM used for flash programming +# By default use 16kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x4000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x6ba02477 +} + +# Configurable instance ID resides in application UICR TINSTANCE +if { [info exists SWD_INSTANCE_ID] } { + set _SWD_INSTANCE_ID $SWD_INSTANCE_ID +} else { + set _SWD_INSTANCE_ID 0 +} + +swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID + +if { [info exists SWD_MULTIDROP] } { + dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -dp-id 0x0070289 -instance-id $_SWD_INSTANCE_ID +} else { + dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +} + +set _TARGETNAME_APP $_CHIPNAME.cpuapp +target create $_TARGETNAME_APP cortex_m -dap $_CHIPNAME.dap + +$_TARGETNAME_APP configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# The network core is not accessible over HLA +if { ![using_hla] } { + set _TARGETNAME_NET $_CHIPNAME.cpunet + target create $_TARGETNAME_NET cortex_m -dap $_CHIPNAME.dap -ap-num 1 -defer-examine + + targets $_TARGETNAME_APP + + $_TARGETNAME_NET configure -work-area-phys 0x21000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 +} + +# Keep adapter speed less or equal 2000 kHz or flash programming fails! +adapter speed 1000 + +source [find target/nrf_common.cfg] + +flash bank $_CHIPNAME.app.flash nrf5 0x00000000 0 0 0 $_TARGETNAME_APP +flash bank $_CHIPNAME.app.uicr nrf5 0x00FF8000 0 0 0 $_TARGETNAME_APP + +if { ![using_hla] } { + + flash bank $_CHIPNAME.net.flash nrf5 0x01000000 0 0 0 $_TARGETNAME_NET + flash bank $_CHIPNAME.net.uicr nrf5 0x01FF8000 0 0 0 $_TARGETNAME_NET + + # System reset sets NETWORK.FORCEOFF which keeps the network core in reset + # Don't touch network core during reset + $_TARGETNAME_NET configure -event reset-assert {} + # and start it after application core reset is finished to make all flash accessible + $_TARGETNAME_APP configure -event reset-init "nrf53_cpunet_release $_CHIPNAME" + + $_TARGETNAME_APP cortex_m reset_config sysresetreq + $_TARGETNAME_NET cortex_m reset_config sysresetreq + + $_TARGETNAME_APP configure -event examine-fail { _nrf_check_ap_lock 2 3 } + $_TARGETNAME_NET configure -event examine-fail { _nrf_check_ap_lock 3 3 } + + $_TARGETNAME_NET configure -event gdb-attach "_nrf53_cpunet_gdb_attach $_CHIPNAME" + + proc _nrf53_cpunet_gdb_attach { _CHIPNAME } { + set _TARGETNAME_APP $_CHIPNAME.cpuapp + set _TARGETNAME_NET $_CHIPNAME.cpunet + set RESET_NETWORK_FORCEOFF 0x50005614 + + set is_off [$_TARGETNAME_APP read_memory $RESET_NETWORK_FORCEOFF 32 1] + if { $is_off } { + nrf53_cpunet_release $_CHIPNAME + $_TARGETNAME_NET arp_poll + $_TARGETNAME_NET arp_waitstate halted 100 + } else { + if { ![$_TARGETNAME_NET was_examined] } { + $_TARGETNAME_NET arp_examine + $_TARGETNAME_NET arp_poll + } + set s [$_TARGETNAME_NET curstate] + if { ![string compare $s "halted"] } { + halt + } + } + } + lappend _telnet_autocomplete_skip _nrf53_cpunet_gdb_attach + + # Release the network core + proc nrf53_cpunet_release { {_CHIPNAME nrf53} } { + set _TARGETNAME_APP $_CHIPNAME.cpuapp + set _TARGETNAME_NET $_CHIPNAME.cpunet + set RESET_NETWORK_FORCEOFF 0x50005614 + set RESET_NETWORK_WORKAROUND 0x50005618 + set CORTEX_M_DCB_DEMCR 0xE000EDFC + + $_TARGETNAME_APP mww $RESET_NETWORK_WORKAROUND 1 + $_TARGETNAME_APP mww $RESET_NETWORK_FORCEOFF 0 + $_TARGETNAME_APP mww $RESET_NETWORK_FORCEOFF 1 + set err [catch {$_TARGETNAME_NET arp_examine}] + if { $err } { + if { ![_nrf_check_ap_lock 3 3] } { + echo "Error: \[$_TARGETNAME_NET\] examination failed" + } + return + } + # set TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET + $_TARGETNAME_NET mww $CORTEX_M_DCB_DEMCR 0x01000501 + # Write DEMCR directly intead of permanetly setting by cortex_m vector_catch reset + # following cortex_m_endreset_event() restores the original DEMCR value + $_TARGETNAME_APP mww $RESET_NETWORK_FORCEOFF 0 + $_TARGETNAME_APP mww $RESET_NETWORK_WORKAROUND 0 + } + + # Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #2 or #3) + proc nrf53_cpuapp_recover {} { + _nrf_ctrl_ap_recover 2 + } + add_help_text nrf53_cpuapp_recover "Mass erase flash and unlock nRF53 application CPU" + + proc nrf53_recover {} { + _nrf_ctrl_ap_recover 3 1 + } + add_help_text nrf53_recover "Mass erase all device flash and unlock nRF53" +} diff --git a/tcl/target/nrf91.cfg b/tcl/target/nrf91.cfg new file mode 100644 index 0000000..e0ff4e5 --- /dev/null +++ b/tcl/target/nrf91.cfg @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Nordic nRF91 series: ARM Cortex-M33, SWD only +# + +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME nrf91 +} + +# Work-area is a space in RAM used for flash programming +# By default use 16kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x4000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x6ba02477 +} + +swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID + +# Contrary to the product specification at least nRF9161 supports multidrop SWD. +# The instance ID is fixed, no more than one nRF91 can be connected to one SWD bus. +if { [info exists SWD_MULTIDROP] } { + dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -dp-id 0x0090289 -instance-id 0 +} else { + dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +# Keep adapter speed less or equal 2000 kHz or flash programming fails! +adapter speed 1000 + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +source [find target/nrf_common.cfg] + +flash bank $_CHIPNAME.flash nrf5 0x00000000 0 0 0 $_TARGETNAME +flash bank $_CHIPNAME.uicr nrf5 0x00FF8000 0 0 0 $_TARGETNAME + +if { ![using_hla] } { + $_TARGETNAME cortex_m reset_config sysresetreq + + $_TARGETNAME configure -event examine-fail { _nrf_check_ap_lock 4 3 } +} + +# Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #4) +proc nrf91_recover {} { + _nrf_ctrl_ap_recover 4 +} +add_help_text nrf91_recover "Mass erase and unlock nRF91 device" diff --git a/tcl/target/nrf_common.cfg b/tcl/target/nrf_common.cfg new file mode 100644 index 0000000..2ae5011 --- /dev/null +++ b/tcl/target/nrf_common.cfg @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Nordic nRF52, nRF53 and nRF91 CTRL-AP handling +# + +if { [using_hla] } { + echo "" + echo "nRF device has a CTRL-AP dedicated to recover the device from AP lock." + echo "A high level adapter (like a ST-Link) you are currently using cannot access" + echo "the CTRL-AP so 'nrfxx_recover' command will not work." + echo "Do not enable UICR APPROTECT." + echo "" +} else { + + # Test if debug/MEM-AP is locked by UICR APPROTECT + proc _nrf_check_ap_lock { ctrl_ap_num unlocked_value } { + set target [target current] + set dap [$target cget -dap] + set err [catch {set APPROTECTSTATUS [$dap apreg $ctrl_ap_num 0xc]}] + if {$err == 0 && $APPROTECTSTATUS < $unlocked_value} { + echo "" + echo "****** WARNING ******" + echo "\[$target\] device has AP lock engaged (see UICR APPROTECT register)." + echo "Debug access is denied." + echo "Use 'nrfxx_recover' to erase and unlock the device." + echo "" + poll off + return 1 + } + return 0 + } + + # Mass erase and unlock the device using proprietary nRF CTRL-AP + proc _nrf_ctrl_ap_recover { ctrl_ap_num {is_cpunet 0} } { + set target [target current] + set dap [$target cget -dap] + + set IDR [$dap apreg $ctrl_ap_num 0xfc] + if {$IDR != 0x12880000} { + echo "Error: Cannot access nRF CTRL-AP!" + return + } + + poll off + + # Reset and trigger ERASEALL task + $dap apreg $ctrl_ap_num 4 0 + $dap apreg $ctrl_ap_num 4 1 + + for {set i 0} {1} {incr i} { + set ERASEALLSTATUS [$dap apreg $ctrl_ap_num 8] + if {$ERASEALLSTATUS == 0} { + echo "\[$target\] device has been successfully erased and unlocked." + break + } + if {$i == 0} { + echo "Waiting for chip erase..." + } + if {$i >= 150} { + echo "Error: \[$target\] recovery failed." + break + } + sleep 100 + } + + # Assert reset + $dap apreg $ctrl_ap_num 0 1 + + # Deassert reset + $dap apreg $ctrl_ap_num 0 0 + + # Reset ERASEALL task + $dap apreg $ctrl_ap_num 4 0 + + if { $is_cpunet } { + reset init + } else { + sleep 100 + $target arp_examine + poll on + } + } + + lappend _telnet_autocomplete_skip _nrf_check_ap_lock _nrf_ctrl_ap_recover +} diff --git a/tcl/target/omap4430.cfg b/tcl/target/omap4430.cfg index a448550..4bc7fe1 100644 --- a/tcl/target/omap4430.cfg +++ b/tcl/target/omap4430.cfg @@ -128,4 +128,4 @@ $_CHIPNAME.m30 configure -event reset-assert { } $_CHIPNAME.m31 configure -event reset-assert { } # Soft breakpoints don't currently work due to broken cache handling -gdb_breakpoint_override hard +gdb breakpoint_override hard diff --git a/tcl/target/omap4460.cfg b/tcl/target/omap4460.cfg index bbc824b..85ba96c 100644 --- a/tcl/target/omap4460.cfg +++ b/tcl/target/omap4460.cfg @@ -128,4 +128,4 @@ $_CHIPNAME.m30 configure -event reset-assert { } $_CHIPNAME.m31 configure -event reset-assert { } # Soft breakpoints don't currently work due to broken cache handling -gdb_breakpoint_override hard +gdb breakpoint_override hard diff --git a/tcl/target/omapl138.cfg b/tcl/target/omapl138.cfg index 2d670b9..78c456d 100644 --- a/tcl/target/omapl138.cfg +++ b/tcl/target/omapl138.cfg @@ -64,5 +64,5 @@ arm7_9 dcc_downloads enable etm config $_TARGETNAME 16 normal full etb etb config $_TARGETNAME $_CHIPNAME.etb -gdb_breakpoint_override hard +gdb breakpoint_override hard arm7_9 dbgrq enable diff --git a/tcl/target/psoc6.cfg b/tcl/target/psoc6.cfg index d69515c..52b04f5 100644 --- a/tcl/target/psoc6.cfg +++ b/tcl/target/psoc6.cfg @@ -113,7 +113,7 @@ proc psoc6_deassert_post { target } { } if { $_ENABLE_CM0 } { - target create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 + target create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 ${TARGET}.cm0 configure -work-area-phys $_WORKAREAADDR_CM0 -work-area-size $_WORKAREASIZE_CM0 -work-area-backup 0 flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 ${TARGET}.cm0 @@ -128,7 +128,7 @@ if { $_ENABLE_CM0 } { } if { $_ENABLE_CM4 } { - target create ${TARGET}.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1 + target create ${TARGET}.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 ${TARGET}.cm4 configure -work-area-phys $_WORKAREAADDR_CM4 -work-area-size $_WORKAREASIZE_CM4 -work-area-backup 0 flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 ${TARGET}.cm4 diff --git a/tcl/target/renesas_rcar_gen3.cfg b/tcl/target/renesas_rcar_gen3.cfg index 8dc0e7a..f6bc5e4 100644 --- a/tcl/target/renesas_rcar_gen3.cfg +++ b/tcl/target/renesas_rcar_gen3.cfg @@ -90,6 +90,18 @@ switch $_soc { set _num_cr52 1 set _boot_core CA76 } + V4H { + set _CHIPNAME r8a779g0 + set _num_ca76 4 + set _num_cr52 3 + set _boot_core CR52 + } + V4M { + set _CHIPNAME r8a779h0 + set _num_ca76 4 + set _num_cr52 3 + set _boot_core CR52 + } default { error "'$_soc' is invalid!" } @@ -126,8 +138,8 @@ set CA57_DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000} set CA57_CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000} set CA53_DBGBASE {0x80C10000 0x80D10000 0x80E10000 0x80F10000} set CA53_CTIBASE {0x80C20000 0x80D20000 0x80E20000 0x80F20000} -set CR52_DBGBASE 0x80c10000 -set CR52_CTIBASE 0x80c20000 +set CR52_DBGBASE {0x80C10000 0x80D10000 0x80E10000} +set CR52_CTIBASE {0x80C20000 0x80D20000 0x80E20000} set CR7_DBGBASE 0x80910000 set CR7_CTIBASE 0x80918000 @@ -159,23 +171,27 @@ proc setup_a5x {core_name dbgbase ctibase num boot} { proc setup_crx {core_name dbgbase ctibase num boot} { global _CHIPNAME global _DAPNAME + global smp_targets + global _targets for { set _core 0 } { $_core < $num } { incr _core } { - set _TARGETNAME $_CHIPNAME.$core_name + set _TARGETNAME $_CHIPNAME.$core_name.$_core set _CTINAME $_TARGETNAME.cti - cti create $_CTINAME -dap $_DAPNAME -ap-num 1 -baseaddr $ctibase + cti create $_CTINAME -dap $_DAPNAME -ap-num 1 -baseaddr [lindex $ctibase $_core] if { $core_name == "r52" } { set _command "target create $_TARGETNAME armv8r -dap $_DAPNAME \ - -ap-num 1 -dbgbase $dbgbase -cti $_CTINAME" + -ap-num 1 -dbgbase [lindex $dbgbase $_core] -cti $_CTINAME" } else { set _command "target create $_TARGETNAME cortex_r4 -dap $_DAPNAME \ - -ap-num 1 -dbgbase $dbgbase" + -ap-num 1 -dbgbase [lindex $dbgbase $_core]" } - if { $boot == 1 } { + if { $_core == 0 && $boot == 1 } { set _targets "$_TARGETNAME" } else { set _command "$_command -defer-examine" } + set smp_targets "$smp_targets $_TARGETNAME" eval $_command + $_TARGETNAME configure -event examine-end { halt } } } diff --git a/tcl/target/renesas_rz_g2.cfg b/tcl/target/renesas_rz.cfg index a3d5f48..a0489de 100644 --- a/tcl/target/renesas_rz_g2.cfg +++ b/tcl/target/renesas_rz.cfg @@ -1,23 +1,25 @@ # SPDX-License-Identifier: GPL-2.0-or-later -# Renesas RZ/G2 SOCs +# Renesas RZ SOCs # - There are a combination of Cortex-A57s, Cortex-A53s, Cortex-A55, Cortex-R7 # and Cortex-M33 for each SOC -# - Each SOC can boot through the Cortex-A5x cores +# - Each SOC can boot through the Cortex-A5x cores or the Cortex-M33 -# Supported RZ/G2 SOCs and their cores: +# Supported RZ SOCs and their cores: # RZ/G2H: Cortex-A57 x4, Cortex-A53 x4, Cortex-R7 # RZ/G2M: Cortex-A57 x2, Cortex-A53 x4, Cortex-R7 # RZ/G2N: Cortex-A57 x2, Cortex-R7 # RZ/G2E: Cortex-A53 x2, Cortex-R7 # RZ/G2L: Cortex-A55 x2, Cortex-M33 +# RZ/V2L: Cortex-A55 x2, Cortex-M33 # RZ/G2LC: Cortex-A55 x2, Cortex-M33 # RZ/G2UL: Cortex-A55 x1, Cortex-M33 +# RZ/G3S: Cortex-A55 x1, Cortex-M33 x2 # Usage: # There are 2 configuration options: # SOC: Selects the supported SOC. (Default 'G2L') -# BOOT_CORE: Selects the booting core. 'CA57', 'CA53' or 'CA55' +# BOOT_CORE: Selects the booting core. 'CA57', 'CA53', 'CA55' or CM33 transport select jtag reset_config trst_and_srst srst_gates_jtag @@ -77,6 +79,13 @@ switch $_soc { set _boot_core CA55 set _ap_num 0 } + V2L { + set _CHIPNAME r9a07g054l + set _num_ca55 2 + set _num_cm33 1 + set _boot_core CA55 + set _ap_num 0 + } G2LC { set _CHIPNAME r9a07g044c set _num_ca55 2 @@ -91,6 +100,13 @@ switch $_soc { set _boot_core CA55 set _ap_num 0 } + G3S { + set _CHIPNAME r9a08g045s + set _num_ca55 1 + set _num_cm33 2 + set _boot_core CA55 + set _ap_num 0 + } default { error "'$_soc' is invalid!" } @@ -112,16 +128,16 @@ if { [info exists DAP_TAPID] } { set _DAP_TAPID 0x6ba00477 } -echo "\t$_soc - $_num_ca57 CA57(s), $_num_ca55 CA55(s), $_num_ca53 CA53(s), $_num_cr7 CR7(s), \ - $_num_cm33 CM33(s)" +echo "\t$_soc - $_num_ca57 CA57(s), $_num_ca55 CA55(s), $_num_ca53 CA53(s), \ + $_num_cr7 CR7(s), $_num_cm33 CM33(s)" echo "\tBoot Core - $_boot_core\n" set _DAPNAME $_CHIPNAME.dap # TAP and DAP -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID \ - -ignore-version +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \ + -expected-id $_DAP_TAPID -ignore-version dap create $_DAPNAME -chain-position $_CHIPNAME.cpu echo "$_CHIPNAME.cpu" @@ -133,8 +149,8 @@ set CA53_DBGBASE {0x80C10000 0x80D10000 0x80E10000 0x80F10000} set CA53_CTIBASE {0x80C20000 0x80D20000 0x80E20000 0x80F20000} set CR7_DBGBASE 0x80910000 set CR7_CTIBASE 0x80918000 -set CM33_DBGBASE 0xE000E000 -set CM33_CTIBASE 0xE0042000 +set CM33_DBGBASE {0xE000E000 0xE010E000} +set CM33_CTIBASE {0xE0042000 0xE0142000} set smp_targets "" @@ -145,7 +161,8 @@ proc setup_a5x {core_name dbgbase ctibase num boot} { cti create $_CTINAME -dap $::_DAPNAME -ap-num $::_ap_num \ -baseaddr [lindex $ctibase $_core] target create $_TARGETNAME aarch64 -dap $::_DAPNAME \ - -ap-num $::_ap_num -dbgbase [lindex $dbgbase $_core] -cti $_CTINAME + -ap-num $::_ap_num -dbgbase [lindex $dbgbase $_core] \ + -cti $_CTINAME if { $_core > 0 || $boot == 0 } { $_TARGETNAME configure -defer-examine } @@ -160,13 +177,29 @@ proc setup_cr7 {dbgbase ctibase} { target create $_TARGETNAME cortex_r4 -dap $::_DAPNAME \ -ap-num 1 -dbgbase $dbgbase -defer-examine } - -proc setup_cm33 {dbgbase ctibase} { - set _TARGETNAME $::_CHIPNAME.m33 - set _CTINAME $_TARGETNAME.cti - cti create $_CTINAME -dap $::_DAPNAME -ap-num 2 -baseaddr $ctibase - target create $_TARGETNAME cortex_m -dap $::_DAPNAME \ - -ap-num 2 -dbgbase $dbgbase -defer-examine +proc setup_cm33 {dbgbase ctibase num boot} { + if { $::_soc == "G2L" || $::_soc == "V2L" \ + || $::_soc == "G2LC" || $::_soc == "G2UL" } { + set _ap_num 2 + } elseif { $::_soc == "G3S" } { + set _ap_num 3 + } + for { set _core 0 } { $_core < $num } { incr _core } { + if { $num <= 1 } { + set _TARGETNAME $::_CHIPNAME.m33 + } else { + set _TARGETNAME $::_CHIPNAME.m33.$_core + } + set _CTINAME $_TARGETNAME.cti + cti create $_CTINAME -dap $::_DAPNAME -ap-num $_ap_num \ + -baseaddr [lindex $ctibase $_core] + target create $_TARGETNAME cortex_m -dap $::_DAPNAME \ + -ap-num $_ap_num -dbgbase [lindex $dbgbase $_core] + if { $boot == 0 } { + $_TARGETNAME configure -defer-examine + } + incr $_ap_num + } } # Organize target list based on the boot core @@ -180,12 +213,17 @@ if { $_boot_core == "CA57" } { setup_cr7 $CR7_DBGBASE $CR7_CTIBASE } elseif { $_boot_core == "CA55" } { setup_a5x a55 $CA55_DBGBASE $CA55_CTIBASE $_num_ca55 1 - setup_cm33 $CM33_DBGBASE $CM33_CTIBASE + setup_cm33 $CM33_DBGBASE $CM33_CTIBASE $_num_cm33 0 +} elseif { $_boot_core == "CM33" } { + setup_a5x a55 $CA55_DBGBASE $CA55_CTIBASE $_num_ca55 0 + setup_cm33 $CM33_DBGBASE $CM33_CTIBASE $_num_cm33 1 } + echo "SMP targets:$smp_targets" eval "target smp $smp_targets" -if { $_soc == "G2L" || $_soc == "G2LC" || $_soc == "G2UL" } { +if { $_soc == "G2L" || $_soc == "V2L" || $_soc == "G2LC" \ +|| $_soc == "G2UL" || $_soc == "G3S"} { target create $_CHIPNAME.axi_ap mem_ap -dap $_DAPNAME -ap-num 1 } diff --git a/tcl/target/rp2040.cfg b/tcl/target/rp2040.cfg index de76b4e..5e78c69 100644 --- a/tcl/target/rp2040.cfg +++ b/tcl/target/rp2040.cfg @@ -96,7 +96,7 @@ if { $_USE_CORE == 1 } { set _FLASH_TARGET $_TARGETNAME_0 } # Backup the work area. The flash probe runs an algorithm on the target CPU. -# The flash is probed during gdb connect if gdb_memory_map is enabled (by default). +# The flash is probed during gdb connect if gdb memory_map is enabled (by default). $_FLASH_TARGET configure -work-area-phys 0x20010000 -work-area-size $_WORKAREASIZE -work-area-backup 1 set _FLASHNAME $_CHIPNAME.flash flash bank $_FLASHNAME rp2040_flash 0x10000000 0 0 0 $_FLASH_TARGET diff --git a/tcl/target/spacemit-k1.cfg b/tcl/target/spacemit-k1.cfg new file mode 100644 index 0000000..ef5d783 --- /dev/null +++ b/tcl/target/spacemit-k1.cfg @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# SpacemiT Key Stone K1 target +# +# https://www.spacemit.com/key-stone-k1 +# + +transport select jtag + +adapter speed 2000 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME k1 +} + +if { [info exists CORES] } { + set _cores $CORES +} else { + set _cores 1 +} + +if { [info exists SECJTAG] } { + jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10000E21 +} else { + jtag newtap pre unknown -irlen 1 -expected-id 0x00000000 -disable + jtag configure pre.unknown -event tap-enable "" + + jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10000E21 -disable + jtag configure $_CHIPNAME.cpu -event tap-enable "" + + jtag newtap post unknown -irlen 9 -expected-id 0x08501C0D -ignore-version + + jtag configure post.unknown -event setup { + global _CHIPNAME + + irscan post.unknown 0x98 + drscan post.unknown 16 0xa + + jtag tapenable pre.unknown + jtag tapenable $_CHIPNAME.cpu + } +} + +set _TARGETNAME $_CHIPNAME.cpu +set DBGBASE {0x0 0x400} +set _smp_command "target smp" + +for { set _core 0 } { $_core < $_cores } { incr _core } { + target create $_TARGETNAME.$_core riscv -chain-position $_TARGETNAME \ + -coreid [expr {$_core % 4}] -dbgbase [lindex $DBGBASE [expr {$_core / 4}]] + + if { [expr {$_core % 4}] == 0 } { + $_TARGETNAME.$_core configure -rtos hwthread + } + + set _smp_command "$_smp_command $_TARGETNAME.$_core" +} + +eval $_smp_command + +set _SPEED 8000 + +$_TARGETNAME.0 configure -event examine-start { + adapter speed $_SPEED + puts [ adapter speed ] +} + +foreach t [target names] { + # $t riscv set_mem_access sysbus progbuf + $t riscv set_mem_access progbuf +} diff --git a/tcl/target/stm32u0x.cfg b/tcl/target/stm32u0x.cfg new file mode 100644 index 0000000..d3aaed3 --- /dev/null +++ b/tcl/target/stm32u0x.cfg @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Configuration file for STM32U0x series. +# +# STM32U0 devices support only SWD transport. +# + +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32u0x +} + +# Work-area is a space in RAM used for flash programming, by default use 4 KiB. +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x1000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x6ba02477 +} + +swd newdap $_CHIPNAME cpu -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME +flash bank $_CHIPNAME.otp stm32l4x 0x1FFF6800 0 0 0 $_TARGETNAME + +adapter speed 2000 + +if {![using_hla]} { + # Use SYSRESETREQ to perform a soft reset if SRST is not fitted. + cortex_m reset_config sysresetreq +} + +$_TARGETNAME configure -event examine-end { + # Enable debug during low power modes (uses more power). + # DBGMCU_CR |= DBG_STANDBY | DBG_STOP + mmw 0x40015804 0x00000006 0 + + # Stop watchdog counters when core is halted. + # DBGMCU_APB1_FZR |= DBG_IWDG_STOP | DBG_WWDG_STOP + mmw 0x40015808 0x00001800 0 +} diff --git a/tcl/target/ti_cc26x2x7.cfg b/tcl/target/ti_cc26x2x7.cfg new file mode 100644 index 0000000..91c1a80 --- /dev/null +++ b/tcl/target/ti_cc26x2x7.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Texas Instruments CC26x2 - ARM Cortex-M4 +# +# http://www.ti.com +# + +set CHIPNAME cc26x2x7 +set JRC_TAPID 0x1BB7702F +set WORKAREASIZE 0x7000 + +source [find target/ti_cc26x0.cfg] diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg index ebea821..0dee74e 100644 --- a/tcl/target/ti_k3.cfg +++ b/tcl/target/ti_k3.cfg @@ -4,8 +4,12 @@ # Texas Instruments K3 devices: # * AM243: https://www.ti.com/lit/pdf/spruim2 # Has 4 R5 Cores, M4F and an M3 +# * AM261: https://www.ti.com/lit/pdf/sprujb6 +# Has 2 R5 Cores and an M4F # * AM263: https://www.ti.com/lit/pdf/spruj17 # Has 4 R5 Cores and an M3 +# * AM263P: https://www.ti.com/lit/pdf/spruj55 +# Has 4 R5 Cores and an M4F # * AM273: https://www.ti.com/lit/pdf/spruiu0 # Has 2 R5 Cores and an M3 # * AM625: https://www.ti.com/lit/pdf/spruiv7a @@ -14,6 +18,8 @@ # Has 4 ARMV8 Cores and 2 R5 Cores # * AM62P: https://www.ti.com/lit/pdf/spruj83 # Has 4 ARMV8 Cores and 2 R5 Cores +# * AM62L: https://www.ti.com/lit/pdf/sprujb4 +# Has 2 ARMv8 Cores only # * AM642: https://www.ti.com/lit/pdf/spruim2 # Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3 # * AM654x: https://www.ti.com/lit/pdf/spruid7 @@ -77,8 +83,16 @@ set _gp_mcu_ap_unlock_offsets {0xf0 0x60} # Generic mem-ap port number set _mem_ap_num 2 +# Generic AP_SEL PWR Register number +set _power_ap_num 3 + +# Generic SPREC RESET BANK and Field number +set _powerap_sprec_reset 0xf0 + # Set configuration overrides for each SOC switch $_soc { + am261 - + am263p - am263 { set _K3_DAP_TAPID 0x2bb7d02f @@ -94,6 +108,16 @@ switch $_soc { set R5_DBGBASE {0x90030000 0x90032000 0x90050000 0x90052000} set R5_CTIBASE {0x90038000 0x90039000 0x90058000 0x90059000} set _r5_ap_num 5 + + set _power_ap_num 7 + + if { "$_soc" == "am263p" } { + set _K3_DAP_TAPID 0x1bb9502f + } + if { "$_soc" == "am261" } { + set _K3_DAP_TAPID 0x1bba602f + set _r5_cores 2 + } } am273 { set _K3_DAP_TAPID 0x1bb6a02f @@ -209,6 +233,16 @@ switch $_soc { # Sysctrl power-ap unlock offsets set _sysctrl_ap_unlock_offsets {0xf0 0x78} + # Setup DMEM access descriptions + # DAPBUS (Debugger) description + set _dmem_base_address 0x740002000 + set _dmem_ap_address_offset 0x100 + set _dmem_max_aps 10 + # Emulated AP description + set _dmem_emu_base_address 0x760000000 + set _dmem_emu_base_address_map_to 0x1d500000 + set _dmem_emu_ap_list 1 + # Overrides for am62p if { "$_soc" == "am62p" } { set _K3_DAP_TAPID 0x0bb9d02f @@ -223,6 +257,18 @@ switch $_soc { set R5_CTIBASE {0x9d418000 0x9d518000 0x9d818000} } } + am62l { + set _K3_DAP_TAPID 0x0bba702f + + # AM62Lx has 1 cluster of 2 A53 cores. + set _armv8_cpu_name a53 + set _armv8_cores 2 + set ARMV8_DBGBASE {0x90010000 0x90110000} + set ARMV8_CTIBASE {0x90020000 0x90120000} + + # Has no supporting microcontrollers + set _r5_cores 0 + } j721e { set _K3_DAP_TAPID 0x0bb6402f # J721E has 1 cluster of 2 A72 cores. @@ -489,3 +535,10 @@ if { 0 == [string compare [adapter name] dmem ] } { # AXI AP access port for SoC address map target create $_CHIPNAME.axi_ap mem_ap -dap $_CHIPNAME.dap -ap-num $_mem_ap_num } + +# Reset system using (Debug Reset) SPREC Register,SYSTEMRESET bit field via apreg +proc dbg_sys_reset {} { + $::_CHIPNAME.dap apreg $::_power_ap_num $::_powerap_sprec_reset 0x1 +} + +add_help_text dbg_sys_reset "Debugger initiated system reset attempt via Power-AP" diff --git a/tcl/target/ti_mspm0.cfg b/tcl/target/ti_mspm0.cfg new file mode 100644 index 0000000..4e9b89c --- /dev/null +++ b/tcl/target/ti_mspm0.cfg @@ -0,0 +1,199 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2023-2025 Texas Instruments Incorporated - https://www.ti.com/ +# +# Texas Instruments MSPM0L/G - ARM Cortex-M0 @ 32MHz +# https://www.ti.com/microcontrollers-mcus-processors/arm-based-microcontrollers/arm-cortex-m0-mcus/overview.html +# + +source [find bitsbytes.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + # Meant to work with MSPM0L and MSPM0G class of devices. + set _CHIPNAME mspm0x +} + +if { [info exists CPUTAPID] } { + set _DAP_TAPID $CPUTAPID +} else { + set _DAP_TAPID 0x4ba00477 +} + +if { [info exists DAP_SWD_ID] } { + set _DAP_SWD_ID $DAP_SWD_ID +} else { + set _DAP_SWD_ID 0x2ba01477 +} + +source [find target/swj-dp.tcl] + +# MSPM0 only supports swd, so set it here and save a line for custom boards +transport select swd + +set _DAP_ID $_DAP_SWD_ID + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_ID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +if { [info exists WORKAREABASE] } { + set _WORKAREABASE $WORKAREABASE +} else { + set _WORKAREABASE 0x20000000 +} +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + # Smallest SRAM size is 1K SRAM. + set _WORKAREASIZE 0x400 +} + +# +# MSPM0 Debug SubSystem Mailbox (DSSM) Communication helpers +# + +proc _mspm0_wait_for_dssm_response {command} { + # Wait for SECAP::RCR rx_valid to be set + set timeout 1000 + while { [expr { [$::_CHIPNAME.dap apreg 2 0xc] & 0x1}] != 0x1 } { + sleep 1 + set timeout [expr {$timeout - 1}] + if { $timeout == 0 } { + set rcr [$::_CHIPNAME.dap apreg 2 0xc] + return -code error [format "MSPM0 SECAP RCR=0x%08x timeout rx_valid" $rcr] + } + } + + # Read SECAP::RXD to clear the RX_VALID bit + set rxd [$::_CHIPNAME.dap apreg 2 0x8] + # Read SECAP::RCR + set rcr [$::_CHIPNAME.dap apreg 2 0xc] + + # Check if we got successful response. This is denoted as: + # 8 LSBits of $command should matchup with SECAP::RCR + # and + # SECAP::RXD should be 0x10003 + if { ([expr { $command & 0xff}] == $rcr) && ($rxd == 0x10003) } { + return 0 + } + + # Provide some debug log for users to report back if CMD fails. + return -code error [format "MSPM0 SECAP CMD FAIL! RXD: 0x%08X RCR: 0x%08X" $rxd $rcr] +} + +proc _mspm0_dssm_command {command} { + # SECAP::TCR = command + $::_CHIPNAME.dap apreg 2 0x4 $command + # SECAP::TDR = 0x0 + $::_CHIPNAME.dap apreg 2 0x0 0x0 + # Read SECAP::RCR and RXD to clear up any prev pending reads + set rxd [$::_CHIPNAME.dap apreg 2 0x8] + set rcr [$::_CHIPNAME.dap apreg 2 0xc] + # Make sure everything is synced + sleep 1000 + # Trigger nRST + mspm0_board_reset + + # Wait for ROM to do it's magic and respond back + set res [_mspm0_wait_for_dssm_response $command] + if { $res } { + return $res + } + # Paranoid.. make sure ROM does what it is meant to do + # RX valid should have been cleared after the operation is + # complete + sleep 1000 + + # Trigger nRST to get back to sane system + mspm0_board_reset + sleep 1000 + + return 0 +} + +# NOTE: Password authentication scheme is NOT supported atm. +# mspm0_factory_reset: Factory reset the board +proc mspm0_factory_reset {} { + set res [_mspm0_dssm_command 0x020a] + if { $res } { + echo "Factory Reset failed!" + } else { + echo "Factory reset success! Halting processor" + # We need to halt the processor else the WDT fires! + halt + } + return $res +} + +add_help_text mspm0_factory_reset "Force Factory reset to recover 'bricked' board" + +# NOTE: Password authentication scheme is NOT supported atm. +# mspm0_mass_erase: Mass erase flash +proc mspm0_mass_erase {} { + set res [_mspm0_dssm_command 0x020c] + if { $res } { + echo "Mass Erase failed!" + } else { + echo "Mass Erase success! Halting Processor" + # We need to halt the processor else the WDT fires! + halt + } + return $res +} + +add_help_text mspm0_mass_erase "Mass erase flash" + +# mspm0_start_bootloader: Ask explicitly for bootloader startup +proc mspm0_start_bootloader {} { + set res [_mspm0_dssm_command 0x0108] + if { $res } { + echo "Start BL failed!" + } + return $res +} + +add_help_text mspm0_start_bootloader "Ask explicitly for bootloader startup" + +# MSPM0 requires board level NRST reset to be toggled for +# Factory reset operations to function. +# However this cannot be the default configuration as this +# prevents reset init reset halt to function properly +# since the Debug Subsystem (debugss) logic or coresight +# seems impacted by nRST. +# This can be overridden in board file as required. +# +# mspm0_board_reset: Board level reset +proc mspm0_board_reset {} { + set user_reset_config [reset_config] + reset_config srst_only + set errno [catch {reset}] + eval reset_config $user_reset_config + if {$errno} {error} +} + +add_help_text mspm0_board_reset "Request a board level reset" + +# If the flash is empty or the device is already in low-power state, then +# debug access is not available. to handle this, explicitly control power ap +# to provide access. Refer to Technical Reference Manual for further info. +proc _mspm0_enable_low_power_mode { } { + # PWR_AP::DPREC <= FRCACT(3)=1, RST_CTL(14:16)=1, IHIB_SLP(20)=1 + $::_CHIPNAME.dap apreg 4 0x00 0x104008 + # PWR_AP::SPREC <= SYSRST=1 + $::_CHIPNAME.dap apreg 4 0xF0 0x01 + # PWR_AP::DPREC <= FRCACT(3)=1, IHIB_SLP(20)=1 + $::_CHIPNAME.dap apreg 4 0x00 0x100008 +} + +$_TARGETNAME configure -event examine-start { _mspm0_enable_low_power_mode } +$_TARGETNAME configure -work-area-phys $_WORKAREABASE -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME.main mspm0 0 0 0 0 $_TARGETNAME +flash bank $_FLASHNAME.nonmain mspm0 0x41c00000 0 0 0 $_TARGETNAME +flash bank $_FLASHNAME.data mspm0 0x41d00000 0 0 0 $_TARGETNAME + +cortex_m reset_config sysresetreq diff --git a/tcl/target/u8500.cfg b/tcl/target/u8500.cfg index 417fdd1..1fdc11f 100644 --- a/tcl/target/u8500.cfg +++ b/tcl/target/u8500.cfg @@ -142,9 +142,9 @@ proc enable_apetap {} { } } -tcl_port 5555 -telnet_port 4444 -gdb_port 3333 +tcl port 5555 +telnet port 4444 +gdb port 3333 if { [info exists CHIPNAME] } { global _CHIPNAME @@ -319,7 +319,7 @@ global _MAXSPEED adapter speed $_MAXSPEED -gdb_breakpoint_override hard +gdb breakpoint_override hard set mem inaccessible-by-default-off jtag_ntrst_delay 100 diff --git a/tcl/target/xtensa.cfg b/tcl/target/xtensa.cfg index 561131d..c277673 100644 --- a/tcl/target/xtensa.cfg +++ b/tcl/target/xtensa.cfg @@ -67,4 +67,4 @@ if { $_XTENSA_NUM_CORES == 1 } { $_TARGETNAME configure -event reset-assert-post { soft_reset_halt } } -gdb_report_register_access_error enable +gdb report_register_access_error enable |