diff options
Diffstat (limited to 'tcl/target/esp32c3.cfg')
| -rw-r--r-- | tcl/target/esp32c3.cfg | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/tcl/target/esp32c3.cfg b/tcl/target/esp32c3.cfg index d266ad5..4dca653 100644 --- a/tcl/target/esp32c3.cfg +++ b/tcl/target/esp32c3.cfg @@ -5,7 +5,7 @@ source [find target/esp_common.cfg] # Target specific global variables -set _CHIPNAME "riscv" +set _CHIPNAME "esp32c3" set _CPUTAPID 0x00005c25 set _ESP_ARCH "riscv" set _ONLYCPU 1 @@ -14,7 +14,7 @@ set _ESP_SMP_BREAK 0 set _ESP_EFUSE_MAC_ADDR_REG 0x60008844 # Target specific functions should be implemented for each riscv chips. -proc riscv_wdt_disable { } { +proc esp32c3_wdt_disable { } { # Halt event can occur during config phase (before "init" is done). # Ignore it since mww commands don't work at that time. if { [string compare [command mode] config] == 0 } { @@ -36,7 +36,7 @@ proc riscv_wdt_disable { } { # This is almost identical with the esp32c2_soc_reset. # Will be refactored with the other common settings. -proc riscv_soc_reset { } { +proc esp32c3_soc_reset { } { global _RISCV_DMCONTROL # This procedure does "digital system reset", i.e. resets @@ -56,7 +56,7 @@ proc riscv_soc_reset { } { sleep 10 poll # Disable the watchdogs again - riscv_wdt_disable + esp32c3_wdt_disable # Here debugger reads allresumeack and allhalted bits as set (0x330a2) # We will clean allhalted state by resuming the core. @@ -66,7 +66,7 @@ proc riscv_soc_reset { } { riscv dmi_write $_RISCV_DMCONTROL 0x80000003 } -proc riscv_memprot_is_enabled { } { +proc esp32c3_memprot_is_enabled { } { # IRAM0 PMS lock, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG if { [get_mmr_bit 0x600C10A8 0] != 0 } { return 1 |