diff options
Diffstat (limited to 'tcl/target/esp32c6.cfg')
| -rw-r--r-- | tcl/target/esp32c6.cfg | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/tcl/target/esp32c6.cfg b/tcl/target/esp32c6.cfg index e1ef10a..14b6a91 100644 --- a/tcl/target/esp32c6.cfg +++ b/tcl/target/esp32c6.cfg @@ -5,7 +5,7 @@ source [find target/esp_common.cfg] # Target specific global variables -set _CHIPNAME "riscv" +set _CHIPNAME "esp32c6" set _CPUTAPID 0x0000dc25 set _ESP_ARCH "riscv" set _ONLYCPU 1 @@ -14,7 +14,7 @@ set _ESP_SMP_BREAK 0 set _ESP_EFUSE_MAC_ADDR_REG 0x600B0844 # Target specific functions should be implemented for each riscv chips. -proc riscv_wdt_disable { } { +proc esp32c6_wdt_disable { } { # Halt event can occur during config phase (before "init" is done). # Ignore it since mww commands don't work at that time. if { [string compare [command mode] config] == 0 } { @@ -34,7 +34,7 @@ proc riscv_wdt_disable { } { mww 0x600b1c1c 0x40000000 } -proc riscv_soc_reset { } { +proc esp32c6_soc_reset { } { global _RISCV_DMCONTROL _RISCV_SB_CS _RISCV_SB_ADDR0 _RISCV_SB_DATA0 riscv dmi_write $_RISCV_DMCONTROL 0x80000001 @@ -59,7 +59,7 @@ proc riscv_soc_reset { } { # Here debugger reads dmstatus as 0x3a2 # Disable the watchdogs again - riscv_wdt_disable + esp32c6_wdt_disable # Here debugger reads anyhalted and allhalted bits as set (0x3a2) # We will clean allhalted state by resuming the core. @@ -69,7 +69,7 @@ proc riscv_soc_reset { } { riscv dmi_write $_RISCV_DMCONTROL 0x80000003 } -proc riscv_memprot_is_enabled { } { +proc esp32c6_memprot_is_enabled { } { global _RISCV_ABS_CMD _RISCV_ABS_DATA0 # If IRAM/DRAM split is enabled TOR address match mode is used. |