tcl: replace the deprecated commands with "adapter ..."

Avoid annoying "deprecated" messages while running the scripts
distributed with OpenOCD code.
Change automatically created with commands
	sed -i 's/adapter_khz/adapter speed/g' $(find tcl/ -type f)
	sed -i 's/adapter_nsrst_delay/adapter srst delay/g' $(find tcl/ -type f)
	sed -i 's/adapter_nsrst_assert_width/adapter srst pulse_width/g' $(find tcl/ -type f)

Minor indentation issue fixed manually in
	tcl/board/at91sam9g20-ek.cfg
	tcl/target/at91sam9260_ext_RAM_ext_flash.cfg

Change-Id: I425fd56c0c88cd6b06124621306eeb89166dfe71
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5284
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>

110 files changed, 191 insertions, 191 deletions

diff --git a/tcl/target/1986ве1т.cfg b/tcl/target/1986ве1т.cfg
index ecb3f8a..b7c9d63 100644
--- a/tcl/target/1986ве1т.cfg
+++ b/tcl/target/1986ве1т.cfg
@@ -50,9 +50,9 @@ if { [info exists IMEMORY] && [string equal $IMEMORY true] } {
 }
 
 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
+adapter speed 1000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
    jtag_ntrst_delay 100
 }
diff --git a/tcl/target/aduc702x.cfg b/tcl/target/aduc702x.cfg
index fca0a7f..9c756be 100644
--- a/tcl/target/aduc702x.cfg
+++ b/tcl/target/aduc702x.cfg
@@ -17,7 +17,7 @@ if { [info exists CPUTAPID] } {
    set _CPUTAPID 0x3f0f0f0f
 }
 
-adapter_nsrst_delay 200
+adapter srst delay 200
 jtag_ntrst_delay 200
 
 ## JTAG scan chain
diff --git a/tcl/target/aducm360.cfg b/tcl/target/aducm360.cfg
index ca4bc68..caee965 100755
--- a/tcl/target/aducm360.cfg
+++ b/tcl/target/aducm360.cfg
@@ -36,7 +36,7 @@ swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 # SWD/JTAG speed
-adapter_khz 1000
+adapter speed 1000
 
 ##
 ## Target configuration
@@ -51,6 +51,6 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME aducm360 0x00 0 0 0 $_TARGETNAME
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 
 cortex_m reset_config sysresetreq
diff --git a/tcl/target/allwinner_v3s.cfg b/tcl/target/allwinner_v3s.cfg
index 32fd188..d8d78bd 100644
--- a/tcl/target/allwinner_v3s.cfg
+++ b/tcl/target/allwinner_v3s.cfg
@@ -34,7 +34,7 @@
 # 0220ms	JTAG pins switched to SD mode
 #
 # The time frame of 20ms can be not enough to init and halt the CPU. In this
-# case I would recommend to set: "adapter_khz 15000"
+# case I would recommend to set: "adapter speed 15000"
 # To get more or less precise timings, the board should provide reset pin,
 # or some bench power supply with remote function. In my case I used
 # EEZ H24005 with this command to power on and halt the target:
diff --git a/tcl/target/altera_fpgasoc.cfg b/tcl/target/altera_fpgasoc.cfg
index 9a83b5c..0fc8d67 100644
--- a/tcl/target/altera_fpgasoc.cfg
+++ b/tcl/target/altera_fpgasoc.cfg
@@ -36,7 +36,7 @@ jtag newtap $_CHIPNAME.fpga tap -irlen 10 -ircapture 0x01 -irmask 0x3 -expected-
 # core 1  -  0x80112000
 
 # Slow speed to be sure it will work
-adapter_khz 1000
+adapter speed 1000
 
 set _TARGETNAME1 $_CHIPNAME.cpu.0
 set _TARGETNAME2 $_CHIPNAME.cpu.1
@@ -46,7 +46,7 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 target create $_TARGETNAME1 cortex_a -dap $_CHIPNAME.dap \
         -coreid 0 -dbgbase 0x80110000
 
-$_TARGETNAME1 configure -event reset-start { adapter_khz 1000 }
+$_TARGETNAME1 configure -event reset-start { adapter speed 1000 }
 $_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
 
 
@@ -54,7 +54,7 @@ $_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
 #target create $_TARGETNAME2 cortex_a -dap $_CHIPNAME.dap \
 #        -coreid 1 -dbgbase 0x80112000
 
-#$_TARGETNAME2 configure -event reset-start { adapter_khz 1000 }
+#$_TARGETNAME2 configure -event reset-start { adapter speed 1000 }
 #$_TARGETNAME2 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME2"
 
 proc cycv_dbginit {target} {
diff --git a/tcl/target/amdm37x.cfg b/tcl/target/amdm37x.cfg
index 5c4e315..7098adf 100644
--- a/tcl/target/amdm37x.cfg
+++ b/tcl/target/amdm37x.cfg
@@ -45,7 +45,7 @@ if { [info exists CHIPTYPE] } {
 
 # Run the adapter at the fastest acceptable speed with the slowest possible
 # core clock.
-adapter_khz 10
+adapter speed 10
 
 ###############################################################################
 # JTAG setup
@@ -157,7 +157,7 @@ $_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
 #  slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up
 #  *after* PLL and clock tree setup.
 
-$_TARGETNAME configure -event "reset-start" { adapter_khz 10 }
+$_TARGETNAME configure -event "reset-start" { adapter speed 10 }
 
 # Describe the reset assert process for openocd - this is asserted with the
 # ICEPick
@@ -176,7 +176,7 @@ $_TARGETNAME configure -event reset-assert-post {
 
    global _TARGETNAME
    amdm37x_dbginit $_TARGETNAME
-   adapter_khz 1000
+   adapter speed 1000
 }
 
 $_TARGETNAME configure -event gdb-attach {
diff --git a/tcl/target/ar71xx.cfg b/tcl/target/ar71xx.cfg
index 196b048..0c64a96 100644
--- a/tcl/target/ar71xx.cfg
+++ b/tcl/target/ar71xx.cfg
@@ -1,7 +1,7 @@
 # Atheros AR71xx MIPS 24Kc SoC.
 # tested on PB44 refererence board
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 
 reset_config trst_and_srst
diff --git a/tcl/target/at91sam3XXX.cfg b/tcl/target/at91sam3XXX.cfg
index e7dec4b..7d01ccd 100644
--- a/tcl/target/at91sam3XXX.cfg
+++ b/tcl/target/at91sam3XXX.cfg
@@ -74,9 +74,9 @@ $_TARGETNAME configure -event gdb-flash-erase-start {
 # running off a crystal, we can run closer to the limit. Note
 # that there can be a pretty wide band where things are more or less stable.
 
-adapter_khz 500
+adapter speed 500
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
    jtag_ntrst_delay 100
 }
diff --git a/tcl/target/at91sam4XXX.cfg b/tcl/target/at91sam4XXX.cfg
index ff73670..ebb7eed 100644
--- a/tcl/target/at91sam4XXX.cfg
+++ b/tcl/target/at91sam4XXX.cfg
@@ -50,9 +50,9 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 # running off a crystal, we can run closer to the limit. Note
 # that there can be a pretty wide band where things are more or less stable.
 
-adapter_khz 500
+adapter speed 500
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
diff --git a/tcl/target/at91sam4lXX.cfg b/tcl/target/at91sam4lXX.cfg
index 4aee7d0..b73babc 100644
--- a/tcl/target/at91sam4lXX.cfg
+++ b/tcl/target/at91sam4lXX.cfg
@@ -21,7 +21,7 @@ reset_config srst_gates_jtag
 # Datasheet does not specify SYSCLK to JTAG/SWD clock ratio.
 # Usually used SYSCLK/6 is hell slow, testing shows that debugging can work @ SYSCLK/2
 # but your mileage may vary.
-adapter_khz 50
+adapter speed 50
 
 # System RC oscillator RCSYS starts in 3 cycles
-adapter_nsrst_delay 0
+adapter srst delay 0
diff --git a/tcl/target/at91sam9.cfg b/tcl/target/at91sam9.cfg
index bf99fb2..e0ea316 100644
--- a/tcl/target/at91sam9.cfg
+++ b/tcl/target/at91sam9.cfg
@@ -24,10 +24,10 @@ reset_config trst_and_srst separate trst_push_pull srst_open_drain
 
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
-adapter_nsrst_delay 300
+adapter srst delay 300
 jtag_ntrst_delay 200
 
-adapter_khz 3
+adapter speed 3
 
 ######################
 # Target configuration
diff --git a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
index 9ab7409..3e4b7d7 100644
--- a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
+++ b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
@@ -6,15 +6,15 @@ source [find target/at91sam9261.cfg]
 
 reset_config trst_and_srst
 
-adapter_khz 4
+adapter speed 4
 
-adapter_nsrst_delay 200
+adapter srst delay 200
 jtag_ntrst_delay 200
 
 scan_chain
 $_TARGETNAME configure -event reset-start {
 	# at reset chip runs at 32khz
-	adapter_khz 8
+	adapter speed 8
 }
 
 $_TARGETNAME configure -event reset-init {at91sam_init}
@@ -46,7 +46,7 @@ proc at91sam_init { } {
 	sleep 10                          ;# wait 10 ms
 
 	# Now run at anything fast... ie: 10mhz!
-	adapter_khz 10000                    ;# Increase JTAG Speed to 6 MHz
+	adapter speed 10000               ;# Increase JTAG Speed to 6 MHz
 
 	mww 0xffffec00 0x0a0a0a0a         ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
 	mww 0xffffec04 0x0b0b0b0b         ;# SMC_PULSE0
diff --git a/tcl/target/at91sam9g20.cfg b/tcl/target/at91sam9g20.cfg
index 3f5e3c6..6e45df2 100644
--- a/tcl/target/at91sam9g20.cfg
+++ b/tcl/target/at91sam9g20.cfg
@@ -12,7 +12,7 @@ source [find target/at91sam9.cfg]
 
 # Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock).
 
-adapter_khz 5
+adapter speed 5
 
 # Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc.  The
 # AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000.
diff --git a/tcl/target/at91samdXX.cfg b/tcl/target/at91samdXX.cfg
index f0644d1..9a396fa 100644
--- a/tcl/target/at91samdXX.cfg
+++ b/tcl/target/at91samdXX.cfg
@@ -66,12 +66,12 @@ reset_config srst_gates_jtag
 # This limit is most probably imposed by incorrectly handled SWD WAIT
 # on some SWD adapters.
 
-adapter_khz 400
+adapter speed 400
 
 # Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works
 # without problem at maximal clock speed. Atmel recommends
 # adapter speed less than 10 * CPU clock.
-# adapter_khz 5000
+# adapter speed 5000
 
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
diff --git a/tcl/target/atheros_ar9331.cfg b/tcl/target/atheros_ar9331.cfg
index bea37ed..6ab238c 100644
--- a/tcl/target/atheros_ar9331.cfg
+++ b/tcl/target/atheros_ar9331.cfg
@@ -41,12 +41,12 @@ reset_config none srst_pulls_trst
 # For SRST based variant we still need proper timings.
 # For ETH part the reset should be asserted at least for 10ms
 # Since there is no other information let's take 100ms to be sure.
-adapter_nsrst_assert_width 100
+adapter srst pulse_width 100
 
 # according to the SoC documentation it should take at least 5ms from
 # reset end till bootstrap end. In the practice we need 8ms to get JTAG back
 # to live.
-adapter_nsrst_delay 8
+adapter srst delay 8
 
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $_CHIPNAME
diff --git a/tcl/target/atmega128.cfg b/tcl/target/atmega128.cfg
index b8f7d01..07161d5 100644
--- a/tcl/target/atmega128.cfg
+++ b/tcl/target/atmega128.cfg
@@ -4,10 +4,10 @@
    set _ENDIAN little
 
 # jtag speed
-adapter_khz 4500
+adapter speed 4500
 
 reset_config srst_only
-adapter_nsrst_delay 100
+adapter srst delay 100
 
 #jtag scan chain
 if { [info exists CPUTAPID] } {
@@ -27,7 +27,7 @@ flash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME
 
 #to use it, script will be like:
 #init
-#adapter_khz 4500
+#adapter speed 4500
 #reset init
 #verify_ircapture disable
 #
diff --git a/tcl/target/atmega128rfa1.cfg b/tcl/target/atmega128rfa1.cfg
index 2c12a61..cda439d 100644
--- a/tcl/target/atmega128rfa1.cfg
+++ b/tcl/target/atmega128rfa1.cfg
@@ -2,7 +2,7 @@ set _CHIPNAME avr
 set _ENDIAN little
 
 # jtag speed
-adapter_khz 4500
+adapter speed 4500
 
 # avr jtag docs never connect RSTN
 reset_config none
diff --git a/tcl/target/atsame5x.cfg b/tcl/target/atsame5x.cfg
index 61949cf..351a2ca 100644
--- a/tcl/target/atsame5x.cfg
+++ b/tcl/target/atsame5x.cfg
@@ -63,7 +63,7 @@ reset_config srst_gates_jtag
 # Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works
 # without problem at clock speed over 5000 khz. Atmel recommends
 # adapter speed less than 10 * CPU clock.
-adapter_khz 2000
+adapter speed 2000
 
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
diff --git a/tcl/target/atsamv.cfg b/tcl/target/atsamv.cfg
index 43962de..4c136ea 100644
--- a/tcl/target/atsamv.cfg
+++ b/tcl/target/atsamv.cfg
@@ -39,7 +39,7 @@ target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20400000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
-adapter_khz 1800
+adapter speed 1800
 
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
diff --git a/tcl/target/avr32.cfg b/tcl/target/avr32.cfg
index f5ee1a4..7808127 100644
--- a/tcl/target/avr32.cfg
+++ b/tcl/target/avr32.cfg
@@ -3,7 +3,7 @@ set _ENDIAN big
 
 set _CPUTAPID 0x21e8203f
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 
 reset_config trst_and_srst separate
diff --git a/tcl/target/bcm6348.cfg b/tcl/target/bcm6348.cfg
index 2540b51..a9be559 100644
--- a/tcl/target/bcm6348.cfg
+++ b/tcl/target/bcm6348.cfg
@@ -1,7 +1,7 @@
 set _CHIPNAME bcm6348
 set _CPUID 0x0634817f
 
-adapter_khz 1000
+adapter speed 1000
 
 jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID
 
diff --git a/tcl/target/bluenrg-x.cfg b/tcl/target/bluenrg-x.cfg
index b0dd61a..109db17 100644
--- a/tcl/target/bluenrg-x.cfg
+++ b/tcl/target/bluenrg-x.cfg
@@ -20,7 +20,7 @@ if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE 0x5F00
 }
 
-adapter_khz 4000
+adapter speed 4000
 
 if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
diff --git a/tcl/target/c100.cfg b/tcl/target/c100.cfg
index 1eaa8fe..5b4354e 100644
--- a/tcl/target/c100.cfg
+++ b/tcl/target/c100.cfg
@@ -3,7 +3,7 @@
 # this script only configures one core (that is used to run Linux)
 
 # assume no PLL lock, start slowly
-adapter_khz 100
+adapter speed 100
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl
index c9124cb..9da3730 100644
--- a/tcl/target/c100helper.tcl
+++ b/tcl/target/c100helper.tcl
@@ -491,7 +491,7 @@ proc reboot {} {
     mww $TIMER_WDT_HIGH_BOUND  0xffffff
     mww $TIMER_WDT_CURRENT_COUNT 0x0
     echo "JTAG speed lowered to 100kHz"
-    adapter_khz 100
+    adapter speed 100
     mww $TIMER_WDT_CONTROL 0x1
     # wait until the reset
     echo -n "Wating for watchdog to trigger..."
diff --git a/tcl/target/cc2538.cfg b/tcl/target/cc2538.cfg
index 63fd9c2..8d232f4 100755
--- a/tcl/target/cc2538.cfg
+++ b/tcl/target/cc2538.cfg
@@ -1,7 +1,7 @@
 # Config for Texas Instruments low power RF SoC CC2538
 # http://www.ti.com/lit/pdf/swru319
 
-adapter_khz 100
+adapter speed 100
 
 source [find target/icepick.cfg]
 source [find target/ti-cjtag.cfg]
diff --git a/tcl/target/dragonite.cfg b/tcl/target/dragonite.cfg
index 750fd64..1277cca 100644
--- a/tcl/target/dragonite.cfg
+++ b/tcl/target/dragonite.cfg
@@ -26,6 +26,6 @@ set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME dragonite -endian $_ENDIAN -chain-position $_TARGETNAME
 
 reset_config trst_and_srst
-adapter_nsrst_delay 200
+adapter srst delay 200
 jtag_ntrst_delay 200
 
diff --git a/tcl/target/dsp56321.cfg b/tcl/target/dsp56321.cfg
index 6f32223..0ac0ce8 100644
--- a/tcl/target/dsp56321.cfg
+++ b/tcl/target/dsp56321.cfg
@@ -21,7 +21,7 @@ if { [info exists CPUTAPID] } {
 }
 
 #jtag speed
-adapter_khz 4500
+adapter speed 4500
 
 #has only srst
 reset_config srst_only
diff --git a/tcl/target/dsp568013.cfg b/tcl/target/dsp568013.cfg
index 0c491fa..98110c2 100644
--- a/tcl/target/dsp568013.cfg
+++ b/tcl/target/dsp568013.cfg
@@ -20,7 +20,7 @@ if { [info exists CPUTAPID] } {
 }
 
 #jtag speed
-adapter_khz 800
+adapter speed 800
 
 reset_config srst_only
 
diff --git a/tcl/target/dsp568037.cfg b/tcl/target/dsp568037.cfg
index 01194d0..010d06f 100644
--- a/tcl/target/dsp568037.cfg
+++ b/tcl/target/dsp568037.cfg
@@ -20,7 +20,7 @@ if { [info exists CPUTAPID] } {
 }
 
 #jtag speed
-adapter_khz 800
+adapter speed 800
 
 reset_config srst_only
 
diff --git a/tcl/target/efm32.cfg b/tcl/target/efm32.cfg
index e22ce5c..c789efc 100644
--- a/tcl/target/efm32.cfg
+++ b/tcl/target/efm32.cfg
@@ -34,7 +34,7 @@ if { [info exists CPUTAPID] } {
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
-adapter_khz 1000
+adapter speed 1000
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
diff --git a/tcl/target/epc9301.cfg b/tcl/target/epc9301.cfg
index f186d37..252bbab 100644
--- a/tcl/target/epc9301.cfg
+++ b/tcl/target/epc9301.cfg
@@ -20,7 +20,7 @@ if { [info exists CPUTAPID] } {
 }
 
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 
 set _TARGETNAME $_CHIPNAME.cpu
diff --git a/tcl/target/esi32xx.cfg b/tcl/target/esi32xx.cfg
index d32af39..6be84ab 100644
--- a/tcl/target/esi32xx.cfg
+++ b/tcl/target/esi32xx.cfg
@@ -26,7 +26,7 @@ if { [info exists CACHEARCH] } {
     $_TARGETNAME esirisc cache_arch $CACHEARCH
 }
 
-adapter_khz 2000
+adapter speed 2000
 
 reset_config none
 
diff --git a/tcl/target/feroceon.cfg b/tcl/target/feroceon.cfg
index 389576e..b934426 100644
--- a/tcl/target/feroceon.cfg
+++ b/tcl/target/feroceon.cfg
@@ -26,6 +26,6 @@ set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME feroceon -endian $_ENDIAN -chain-position $_TARGETNAME
 
 reset_config trst_and_srst
-adapter_nsrst_delay 200
+adapter srst delay 200
 jtag_ntrst_delay 200
 
diff --git a/tcl/target/fm3.cfg b/tcl/target/fm3.cfg
index a0610ce..376320e 100644
--- a/tcl/target/fm3.cfg
+++ b/tcl/target/fm3.cfg
@@ -22,7 +22,7 @@ if { [info exists CPUTAPID] } {
 }
 
 # delays on reset lines
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
    jtag_ntrst_delay 100
 }
@@ -45,7 +45,7 @@ set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
 
 # 4MHz / 6 = 666kHz, so use 500
-adapter_khz 500
+adapter speed 500
 
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
diff --git a/tcl/target/fm4.cfg b/tcl/target/fm4.cfg
index b79634d..bfe7115 100644
--- a/tcl/target/fm4.cfg
+++ b/tcl/target/fm4.cfg
@@ -24,7 +24,7 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
 
-adapter_khz 500
+adapter speed 500
 
 if {![using_hla]} {
 	cortex_m reset_config sysresetreq
diff --git a/tcl/target/gp326xxxa.cfg b/tcl/target/gp326xxxa.cfg
index feb7554..df42c44 100644
--- a/tcl/target/gp326xxxa.cfg
+++ b/tcl/target/gp326xxxa.cfg
@@ -33,11 +33,11 @@ $_TARGETNAME configure -work-area-phys 0xf8000000 -work-area-size 0x8000 -work-a
 reset_config trst_and_srst srst_pulls_trst
 # This delay is needed otherwise communication with the target would
 # be unreliable
-adapter_nsrst_delay 100
+adapter srst delay 100
 
 # Set the adapter speed ridiculously low just in case we are
 # running off of a 32kHz clock
-adapter_khz 2
+adapter speed 2
 
 proc gp32xxxa_halt_and_reset_control_registers {} {
 	# System control registers
@@ -57,7 +57,7 @@ proc gp32xxxa_halt_and_reset_control_registers {} {
 
 	# Set the adapter speed ridiculously low just in case we are
 	# running off of a 32kHz clock
-	adapter_khz 2
+	adapter speed 2
 
 	# Disable any advanced features at this stage
 	arm7_9 dcc_downloads disable
@@ -86,7 +86,7 @@ proc gp32xxxa_halt_and_reset_control_registers {} {
 
 	# Now that we know that we are running at 48Mhz
 	# Increase JTAG speed and enable speed optimization features
-	adapter_khz 5000
+	adapter speed 5000
 	arm7_9 dcc_downloads enable
 	arm7_9 fast_memory_access enable
 }
diff --git a/tcl/target/imx28.cfg b/tcl/target/imx28.cfg
index 4cc3950..1fea3fa 100644
--- a/tcl/target/imx28.cfg
+++ b/tcl/target/imx28.cfg
@@ -4,7 +4,7 @@
 reset_config trst_and_srst
 
 #jtag nTRST and nSRST delay
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 
 if { [info exists CHIPNAME] } {
diff --git a/tcl/target/imx31.cfg b/tcl/target/imx31.cfg
index ca63951..d850657 100644
--- a/tcl/target/imx31.cfg
+++ b/tcl/target/imx31.cfg
@@ -3,7 +3,7 @@
 
 reset_config trst_and_srst srst_gates_jtag
 
-adapter_nsrst_delay 5
+adapter srst delay 5
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/imx6.cfg b/tcl/target/imx6.cfg
index f359346..2945334 100644
--- a/tcl/target/imx6.cfg
+++ b/tcl/target/imx6.cfg
@@ -75,7 +75,7 @@ proc imx6_dbginit {target} {
 }
 
 # Slow speed to be sure it will work
-adapter_khz 1000
-$_TARGETNAME configure -event reset-start { adapter_khz 1000 }
+adapter speed 1000
+$_TARGETNAME configure -event reset-start { adapter speed 1000 }
 
 $_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME"
diff --git a/tcl/target/is5114.cfg b/tcl/target/is5114.cfg
index 31f1aa1..1a06b09 100644
--- a/tcl/target/is5114.cfg
+++ b/tcl/target/is5114.cfg
@@ -23,7 +23,7 @@ if { [info exists CPUTAPID] } {
 }
 
 # jtag speed. We need to stick to 16kHz until we've finished reset.
-adapter_khz 16
+adapter speed 16
 
 reset_config trst_and_srst
 
@@ -38,9 +38,9 @@ jtag newtap $_CHIPNAME unknown2 -irlen 5 -ircapture 1 -irmask 1
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
 
-$_TARGETNAME configure -event reset-start { adapter_khz 16 }
+$_TARGETNAME configure -event reset-start { adapter speed 16 }
 $_TARGETNAME configure -event reset-init {
 	# We can increase speed now that we know the target is halted.
-	adapter_khz 3000
+	adapter speed 3000
 }
 $_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 1
diff --git a/tcl/target/k1921vk01t.cfg b/tcl/target/k1921vk01t.cfg
index 1a84021..926f3c7 100755
--- a/tcl/target/k1921vk01t.cfg
+++ b/tcl/target/k1921vk01t.cfg
@@ -40,9 +40,9 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 
 flash bank $_CHIPNAME.flash niietcm4 0 0 0 0 $_TARGETNAME
 
-adapter_khz 2000
+adapter speed 2000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
    jtag_ntrst_delay 100
 }
diff --git a/tcl/target/ke0x.cfg b/tcl/target/ke0x.cfg
index 8239400..b92721f 100644
--- a/tcl/target/ke0x.cfg
+++ b/tcl/target/ke0x.cfg
@@ -35,7 +35,7 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
 
-adapter_khz 1000
+adapter speed 1000
 
 reset_config srst_nogate
 
diff --git a/tcl/target/klx.cfg b/tcl/target/klx.cfg
index 5d9286a..36b6ed5 100644
--- a/tcl/target/klx.cfg
+++ b/tcl/target/klx.cfg
@@ -40,7 +40,7 @@ kinetis create_banks
 # Table 5-1. Clock Summary of KL25 Sub-Family Reference Manual
 # specifies up to 1MHz for VLPR mode and up to 24MHz for run mode;
 # Table 17 of Sub-Family Data Sheet rev4 lists 25MHz as the maximum frequency.
-adapter_khz 1000
+adapter speed 1000
 
 reset_config srst_nogate
 
diff --git a/tcl/target/ks869x.cfg b/tcl/target/ks869x.cfg
index 0f6829c..78cc402 100644
--- a/tcl/target/ks869x.cfg
+++ b/tcl/target/ks869x.cfg
@@ -18,7 +18,7 @@ if { [info exists CPUTAPID] } {
    set  _CPUTAPID 0x00922f0f
 }
 
-adapter_khz 6000
+adapter speed 6000
 
 # jtag scan chain
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
diff --git a/tcl/target/kx.cfg b/tcl/target/kx.cfg
index 73ee62a..0ff5b0c 100644
--- a/tcl/target/kx.cfg
+++ b/tcl/target/kx.cfg
@@ -41,7 +41,7 @@ set _FLASHNAME $_CHIPNAME.pflash
 flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
 kinetis create_banks
 
-adapter_khz 1000
+adapter speed 1000
 
 reset_config srst_nogate
 
diff --git a/tcl/target/lpc1850.cfg b/tcl/target/lpc1850.cfg
index 925a049..481dc8a 100644
--- a/tcl/target/lpc1850.cfg
+++ b/tcl/target/lpc1850.cfg
@@ -1,6 +1,6 @@
 source [find target/swj-dp.tcl]
 
-adapter_khz 500
+adapter speed 500
 
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/lpc1xxx.cfg b/tcl/target/lpc1xxx.cfg
index 1969e46..946d1ce 100644
--- a/tcl/target/lpc1xxx.cfg
+++ b/tcl/target/lpc1xxx.cfg
@@ -145,10 +145,10 @@ if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "l
 # Run with *real slow* clock by default since the
 # boot rom could have been playing with the PLL, so
 # we have no idea what clock the target is running at.
-adapter_khz 10
+adapter speed 10
 
 # delays on reset lines
-adapter_nsrst_delay 200
+adapter srst delay 200
 if {[using_jtag]} {
  jtag_ntrst_delay 200
 }
diff --git a/tcl/target/lpc2xxx.cfg b/tcl/target/lpc2xxx.cfg
index 11f1c48..4c3394c 100644
--- a/tcl/target/lpc2xxx.cfg
+++ b/tcl/target/lpc2xxx.cfg
@@ -13,10 +13,10 @@ proc setup_lpc2xxx {chip_name cputapids flash_size flash_variant workarea_size c
 	reset_config trst_and_srst
 
 	# reset delays
-	adapter_nsrst_delay 100
+	adapter srst delay 100
 	jtag_ntrst_delay 100
 
-	adapter_khz $adapter_freq_khz
+	adapter speed $adapter_freq_khz
 
 	foreach i $cputapids {
 		append expected_ids "-expected-id " $i " "
diff --git a/tcl/target/lpc3131.cfg b/tcl/target/lpc3131.cfg
index 27c1f67..185c0aa 100644
--- a/tcl/target/lpc3131.cfg
+++ b/tcl/target/lpc3131.cfg
@@ -52,7 +52,7 @@ dict set lpc313x wdt			0x13002400
 # Target configuration
 ##################################################################
 
-adapter_nsrst_delay 1000
+adapter srst delay 1000
 jtag_ntrst_delay 0
 
 set _TARGETNAME $_CHIPNAME.cpu
diff --git a/tcl/target/lpc4350.cfg b/tcl/target/lpc4350.cfg
index 2b72884..0c6d0ff 100644
--- a/tcl/target/lpc4350.cfg
+++ b/tcl/target/lpc4350.cfg
@@ -1,6 +1,6 @@
 source [find target/swj-dp.tcl]
 
-adapter_khz 500
+adapter speed 500
 
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/lpc4370.cfg b/tcl/target/lpc4370.cfg
index 1374ef2..9db2b9e 100644
--- a/tcl/target/lpc4370.cfg
+++ b/tcl/target/lpc4370.cfg
@@ -2,7 +2,7 @@
 # NXP LPC4370 - 1x ARM Cortex-M4 + 2x ARM Cortex-M0 @ up to 204 MHz each
 #
 
-adapter_khz 500
+adapter speed 500
 
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/lpc8nxx.cfg b/tcl/target/lpc8nxx.cfg
index b933290..1bc77b2 100644
--- a/tcl/target/lpc8nxx.cfg
+++ b/tcl/target/lpc8nxx.cfg
@@ -22,7 +22,7 @@ if {![using_hla]} {
 	# If srst is not fitted use SYSRESETREQ to  perform a soft reset
 	cortex_m reset_config sysresetreq
 }
-adapter_nsrst_delay 100
+adapter srst delay 100
 
 $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x1ff0 -work-area-backup 0
 
diff --git a/tcl/target/ls1012a.cfg b/tcl/target/ls1012a.cfg
index 9a9e684..19d3e58 100644
--- a/tcl/target/ls1012a.cfg
+++ b/tcl/target/ls1012a.cfg
@@ -32,4 +32,4 @@ target create $_TARGETNAME aarch64 -dap $_CHIPNAME.dap -dbgbase 0x80410000 -cti
 
 target smp $_TARGETNAME
 
-adapter_khz 2000
+adapter speed 2000
diff --git a/tcl/target/max32620.cfg b/tcl/target/max32620.cfg
index 80cb25a..6187bb9 100644
--- a/tcl/target/max32620.cfg
+++ b/tcl/target/max32620.cfg
@@ -2,7 +2,7 @@
 # www.maximintegrated.com
 
 # adapter speed
-adapter_khz 4000
+adapter speed 4000
 
 # reset pin configuration
 reset_config srst_only
diff --git a/tcl/target/max32625.cfg b/tcl/target/max32625.cfg
index 7182b23..159b360 100644
--- a/tcl/target/max32625.cfg
+++ b/tcl/target/max32625.cfg
@@ -2,7 +2,7 @@
 # www.maximintegrated.com
 
 # adapter speed
-adapter_khz 4000
+adapter speed 4000
 
 # reset pin configuration
 reset_config srst_only
diff --git a/tcl/target/max3263x.cfg b/tcl/target/max3263x.cfg
index f23b0b6..fc7d11f 100644
--- a/tcl/target/max3263x.cfg
+++ b/tcl/target/max3263x.cfg
@@ -2,7 +2,7 @@
 # www.maximintegrated.com
 
 # adapter speed
-adapter_khz 4000
+adapter speed 4000
 
 # reset pin configuration
 reset_config srst_only
diff --git a/tcl/target/mc13224v.cfg b/tcl/target/mc13224v.cfg
index 27ac8c3..f756dd9 100644
--- a/tcl/target/mc13224v.cfg
+++ b/tcl/target/mc13224v.cfg
@@ -35,8 +35,8 @@ reset_config srst_only
 jtag_ntrst_delay 200
 
 # rclk hasn't been working well. This maybe the mc13224v or something else.
-#adapter_khz 2000
-adapter_khz 2000
+#adapter speed 2000
+adapter speed 2000
 
 ######################
 # Target configuration
diff --git a/tcl/target/mdr32f9q2i.cfg b/tcl/target/mdr32f9q2i.cfg
index 6748102..820d2dd 100644
--- a/tcl/target/mdr32f9q2i.cfg
+++ b/tcl/target/mdr32f9q2i.cfg
@@ -49,9 +49,9 @@ if { [info exists IMEMORY] && [string equal $IMEMORY true] } {
 }
 
 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
+adapter speed 1000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
    jtag_ntrst_delay 100
 }
diff --git a/tcl/target/nrf51.cfg b/tcl/target/nrf51.cfg
index 4f24020..d51a50e 100644
--- a/tcl/target/nrf51.cfg
+++ b/tcl/target/nrf51.cfg
@@ -50,7 +50,7 @@ flash bank $_CHIPNAME.uicr nrf51 0x10001000 0 1 1 $_TARGETNAME
 #  The chip should start up from internal 16Mhz RC, so setting adapter
 #  clock to 1Mhz should be OK
 #
-adapter_khz 1000
+adapter speed 1000
 
 proc enable_all_ram {} {
 	# nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM banks
diff --git a/tcl/target/nrf52.cfg b/tcl/target/nrf52.cfg
index c29adbd..00901bf 100644
--- a/tcl/target/nrf52.cfg
+++ b/tcl/target/nrf52.cfg
@@ -30,7 +30,7 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
 
-adapter_khz 1000
+adapter speed 1000
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
diff --git a/tcl/target/numicro.cfg b/tcl/target/numicro.cfg
index c42dfbc..73022df 100644
--- a/tcl/target/numicro.cfg
+++ b/tcl/target/numicro.cfg
@@ -48,7 +48,7 @@ set _FLASHNAME $_CHIPNAME.flash_config
 flash bank $_FLASHNAME numicro 0x00300000 0 0 0 $_TARGETNAME
 
 # set default SWCLK frequency
-adapter_khz 1000
+adapter speed 1000
 
 # set default srst setting "none"
 reset_config none
diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg
index 078d7f2..dcf7c51 100644
--- a/tcl/target/omap3530.cfg
+++ b/tcl/target/omap3530.cfg
@@ -63,8 +63,8 @@ proc omap3_dbginit {target} {
 # be absolutely certain the JTAG clock will work with the worst-case
 # 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
 # OK to speed up *after* PLL and clock tree setup.
-adapter_khz 1000
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1000 }
+adapter speed 1000
+$_TARGETNAME configure -event "reset-start" { adapter speed 1000 }
 
 # Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
 # ourselves using PRM_RSTCTRL.  RST_GS (2) is a warm reset, like ICEpick
diff --git a/tcl/target/omap5912.cfg b/tcl/target/omap5912.cfg
index c4ff40e..2f9338b 100644
--- a/tcl/target/omap5912.cfg
+++ b/tcl/target/omap5912.cfg
@@ -14,7 +14,7 @@ if { [info exists CPUTAPID] } {
    set _CPUTAPID 0x0692602f
 }
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 
 # NOTE: presumes irlen 38 is the C55x DSP, matching BSDL for
 # its standalone siblings (like TMS320VC5502) of the same era
diff --git a/tcl/target/omapl138.cfg b/tcl/target/omapl138.cfg
index fd9ff4c..30cf23c 100644
--- a/tcl/target/omapl138.cfg
+++ b/tcl/target/omapl138.cfg
@@ -52,8 +52,8 @@ $_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000
 # be absolutely certain the JTAG clock will work with the worst-case
 # CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
 # on the PLL and starts using it.  OK to speed up after clock setup.
-adapter_khz 1500
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
 
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable
diff --git a/tcl/target/pic32mx.cfg b/tcl/target/pic32mx.cfg
index d53b99a..51a6bbd 100644
--- a/tcl/target/pic32mx.cfg
+++ b/tcl/target/pic32mx.cfg
@@ -23,7 +23,7 @@ if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE 0x4000
 }
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 
 #jtag scan chain
diff --git a/tcl/target/psoc4.cfg b/tcl/target/psoc4.cfg
index 544e109..b568282 100644
--- a/tcl/target/psoc4.cfg
+++ b/tcl/target/psoc4.cfg
@@ -36,7 +36,7 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
 
-adapter_khz 1500
+adapter speed 1500
 
 # Reset, bloody PSoC 4 reset
 #
@@ -118,7 +118,7 @@ proc ocd_process_reset_inner { MODE } {
 	}
 
 	if { ! [info exists PSOC4_USE_ACQUIRE] } {
-		if { 0 == [string compare [adapter_name] kitprog ] } {
+		if { 0 == [string compare [adapter name] kitprog ] } {
 			set PSOC4_USE_ACQUIRE 1
 		} else {
 			set PSOC4_USE_ACQUIRE 0
@@ -138,7 +138,7 @@ proc ocd_process_reset_inner { MODE } {
 	$t invoke-event reset-assert-pre
 
 	if { $halt && $PSOC4_USE_ACQUIRE } {
-		catch { [adapter_name] acquire_psoc }
+		catch { [adapter name] acquire_psoc }
 		$t arp_examine
 	} else {
 		if { $PSOC4_TEST_MODE_WORKAROUND } {
diff --git a/tcl/target/psoc6.cfg b/tcl/target/psoc6.cfg
index fc0c711..51d032b 100644
--- a/tcl/target/psoc6.cfg
+++ b/tcl/target/psoc6.cfg
@@ -6,7 +6,7 @@
 
 source [find target/swj-dp.tcl]
 
-adapter_khz 1000
+adapter speed 1000
 
 global _CHIPNAME
 if { [info exists CHIPNAME] } {
diff --git a/tcl/target/pxa255.cfg b/tcl/target/pxa255.cfg
index 4b222de..73518bf 100644
--- a/tcl/target/pxa255.cfg
+++ b/tcl/target/pxa255.cfg
@@ -28,8 +28,8 @@ target create $_TARGETNAME xscale -endian $_ENDIAN \
 # PXA255 comes out of reset using 3.6864 MHz oscillator.
 # Until the PLL kicks in, keep the JTAG clock slow enough
 # that we get no errors.
-adapter_khz 300
-$_TARGETNAME configure -event "reset-start" { adapter_khz 300 }
+adapter speed 300
+$_TARGETNAME configure -event "reset-start" { adapter speed 300 }
 
 # both TRST and SRST are *required* for debug
 # DCSR is often accessed with SRST active
diff --git a/tcl/target/pxa270.cfg b/tcl/target/pxa270.cfg
index 95f7f16..bd904b5 100644
--- a/tcl/target/pxa270.cfg
+++ b/tcl/target/pxa270.cfg
@@ -34,9 +34,9 @@ if { [info exists CPUTAPID3] } {
    set _CPUTAPID3 0x89265013
 }
 
-# set adapter_nsrst_delay to the delay introduced by your reset circuit
+# set adapter srst delay to the delay introduced by your reset circuit
 # the rest of the needed delays are built into the openocd program
-adapter_nsrst_delay 260
+adapter srst delay 260
 # set the jtag_ntrst_delay to the delay introduced by a reset circuit
 # the rest of the needed delays are built into the openocd program
 jtag_ntrst_delay 250
diff --git a/tcl/target/pxa3xx.cfg b/tcl/target/pxa3xx.cfg
index c459f6e..1a4539c 100644
--- a/tcl/target/pxa3xx.cfg
+++ b/tcl/target/pxa3xx.cfg
@@ -59,9 +59,9 @@ if { [info exists CPUTAPID_PXA32X_C0] } {
    set _CPUTAPID_PXA32X_C0 0x7E642013
 }
 
-# set adapter_nsrst_delay to the delay introduced by your reset circuit
+# set adapter srst delay to the delay introduced by your reset circuit
 # the rest of the needed delays are built into the openocd program
-adapter_nsrst_delay 260
+adapter srst delay 260
 
 # set the jtag_ntrst_delay to the delay introduced by a reset circuit
 # the rest of the needed delays are built into the openocd program
diff --git a/tcl/target/qualcomm_qca4531.cfg b/tcl/target/qualcomm_qca4531.cfg
index 3d21578..0b046b8 100644
--- a/tcl/target/qualcomm_qca4531.cfg
+++ b/tcl/target/qualcomm_qca4531.cfg
@@ -38,12 +38,12 @@ reset_config none srst_pulls_trst
 # For SRST based variant we still need proper timings.
 # For ETH part the reset should be asserted at least for 10ms
 # Since there is no other information let's take 100ms to be sure.
-adapter_nsrst_assert_width 100
+adapter srst pulse_width 100
 
 # according to the SoC documentation it should take at least 5ms from
 # reset end till bootstrap end. In the practice we need 8ms to get JTAG back
 # to live.
-adapter_nsrst_delay 8
+adapter srst delay 8
 
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $_CHIPNAME
diff --git a/tcl/target/readme.txt b/tcl/target/readme.txt
index f028b11..2c3cc8d 100644
--- a/tcl/target/readme.txt
+++ b/tcl/target/readme.txt
@@ -26,12 +26,12 @@ assumed that all write-protect mechanisms should be disabled.
 flash write_image [file] <parameters>
 verify_image [file] <parameters>
 
-4. adapter_khz sets the maximum speed (or alternatively RCLK). If invoked
+4. adapter speed sets the maximum speed (or alternatively RCLK). If invoked
 multiple times only the last setting is used.
 
 interface/xxx.cfg files are always executed *before* target/xxx.cfg
-files, so any adapter_khz in interface/xxx.cfg will be overridden by
-target/xxx.cfg. adapter_khz in interface/xxx.cfg would then, effectively,
+files, so any adapter speed in interface/xxx.cfg will be overridden by
+target/xxx.cfg. adapter speed in interface/xxx.cfg would then, effectively,
 set the default JTAG speed.
 
 Note that a target/xxx.cfg file can invoke another target/yyy.cfg file,
diff --git a/tcl/target/renesas_s7g2.cfg b/tcl/target/renesas_s7g2.cfg
index 78fb3e8..b4be88f 100644
--- a/tcl/target/renesas_s7g2.cfg
+++ b/tcl/target/renesas_s7g2.cfg
@@ -48,4 +48,4 @@ if { ![using_hla] } {
 	cortex_m reset_config sysresetreq
 }
 
-adapter_khz 1000
+adapter speed 1000
diff --git a/tcl/target/samsung_s3c2450.cfg b/tcl/target/samsung_s3c2450.cfg
index 1bc4f2d..2482557 100644
--- a/tcl/target/samsung_s3c2450.cfg
+++ b/tcl/target/samsung_s3c2450.cfg
@@ -7,11 +7,11 @@
 #
 # RCLK?
 #
-# adapter_khz 0
+# adapter speed 0
 #
 # Really low clock during reset?
 #
-# adapter_khz 1
+# adapter speed 1
 
 if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/samsung_s3c6410.cfg b/tcl/target/samsung_s3c6410.cfg
index 88fe966..9f7c2cd 100644
--- a/tcl/target/samsung_s3c6410.cfg
+++ b/tcl/target/samsung_s3c6410.cfg
@@ -40,7 +40,7 @@ jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_C
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
 
-adapter_nsrst_delay 500
+adapter srst delay 500
 jtag_ntrst_delay 500
 
 #reset configuration
diff --git a/tcl/target/sim3x.cfg b/tcl/target/sim3x.cfg
index ed46a3b..3d3fc5c 100755
--- a/tcl/target/sim3x.cfg
+++ b/tcl/target/sim3x.cfg
@@ -48,9 +48,9 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
 
-adapter_khz 1000
+adapter speed 1000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
diff --git a/tcl/target/smp8634.cfg b/tcl/target/smp8634.cfg
index c13414c..e95f633 100644
--- a/tcl/target/smp8634.cfg
+++ b/tcl/target/smp8634.cfg
@@ -18,7 +18,7 @@ if { [info exists CPUTAPID] } {
    set _CPUTAPID 0x08630001
 }
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 
 reset_config trst_and_srst separate
diff --git a/tcl/target/stellaris.cfg b/tcl/target/stellaris.cfg
index 7fffd2a..fb591c2 100644
--- a/tcl/target/stellaris.cfg
+++ b/tcl/target/stellaris.cfg
@@ -68,7 +68,7 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 # NOTE: this may be increased by a reset-init handler, after it
 # configures and enables the PLL.  Or you might need to decrease
 # this, if you're using a slower clock.
-adapter_khz 500
+adapter speed 500
 
 source [find mem_helper.tcl]
 
@@ -132,7 +132,7 @@ proc reset_peripherals {family} {
 }
 
 $_TARGETNAME configure -event reset-start {
-	adapter_khz 500
+	adapter speed 500
 
 	#
 	# When nRST is asserted on most Stellaris devices, it clears some of
diff --git a/tcl/target/stm32f0x.cfg b/tcl/target/stm32f0x.cfg
index baac9b6..b20d036 100644
--- a/tcl/target/stm32f0x.cfg
+++ b/tcl/target/stm32f0x.cfg
@@ -52,9 +52,9 @@ set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
 
 # adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
+adapter speed 1000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 
 reset_config srst_nogate
 
@@ -66,7 +66,7 @@ if {![using_hla]} {
 
 proc stm32f0x_default_reset_start {} {
 	# Reset clock is HSI (8 MHz)
-	adapter_khz 1000
+	adapter speed 1000
 }
 
 proc stm32f0x_default_examine_end {} {
@@ -86,7 +86,7 @@ proc stm32f0x_default_reset_init {} {
 	mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
 
 	# Boost JTAG frequency
-	adapter_khz 8000
+	adapter speed 8000
 }
 
 # Default hooks
diff --git a/tcl/target/stm32f1x.cfg b/tcl/target/stm32f1x.cfg
index 471878d..3e85fb2 100644
--- a/tcl/target/stm32f1x.cfg
+++ b/tcl/target/stm32f1x.cfg
@@ -60,9 +60,9 @@ set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
 
 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
+adapter speed 1000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
diff --git a/tcl/target/stm32f2x.cfg b/tcl/target/stm32f2x.cfg
index 1e8b94a..d790feb 100644
--- a/tcl/target/stm32f2x.cfg
+++ b/tcl/target/stm32f2x.cfg
@@ -28,9 +28,9 @@ if { [info exists WORKAREASIZE] } {
 # bit more to be on the safe side. Perhaps superstition, but if are
 # running off a crystal, we can run closer to the limit. Note
 # that there can be a pretty wide band where things are more or less stable.
-adapter_khz 1000
+adapter speed 1000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg
index 86e9f59..e3f1a34 100644
--- a/tcl/target/stm32f3x.cfg
+++ b/tcl/target/stm32f3x.cfg
@@ -28,9 +28,9 @@ if { [info exists WORKAREASIZE] } {
 # bit more to be on the safe side. Perhaps superstition, but if are
 # running off a crystal, we can run closer to the limit. Note
 # that there can be a pretty wide band where things are more or less stable.
-adapter_khz 1000
+adapter speed 1000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
@@ -73,7 +73,7 @@ if {![using_hla]} {
 
 proc stm32f3x_default_reset_start {} {
 	# Reset clock is HSI (8 MHz)
-	adapter_khz 1000
+	adapter speed 1000
 }
 
 proc stm32f3x_default_examine_end {} {
@@ -93,7 +93,7 @@ proc stm32f3x_default_reset_init {} {
 	mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
 
 	# Boost JTAG frequency
-	adapter_khz 8000
+	adapter speed 8000
 }
 
 # Default hooks
diff --git a/tcl/target/stm32f4x.cfg b/tcl/target/stm32f4x.cfg
index 09ce14a..b95e783 100644
--- a/tcl/target/stm32f4x.cfg
+++ b/tcl/target/stm32f4x.cfg
@@ -58,9 +58,9 @@ flash bank $_CHIPNAME.otp stm32f2x 0x1fff7800 0 0 0 $_TARGETNAME
 # bit more to be on the safe side. Perhaps superstition, but if are
 # running off a crystal, we can run closer to the limit. Note
 # that there can be a pretty wide band where things are more or less stable.
-adapter_khz 2000
+adapter speed 2000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
@@ -100,10 +100,10 @@ $_TARGETNAME configure -event reset-init {
 	mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
 
 	# Boost JTAG frequency
-	adapter_khz 8000
+	adapter speed 8000
 }
 
 $_TARGETNAME configure -event reset-start {
 	# Reduce speed since CPU speed will slow down to 16MHz with the reset
-	adapter_khz 2000
+	adapter speed 2000
 }
diff --git a/tcl/target/stm32f7x.cfg b/tcl/target/stm32f7x.cfg
index ba1d12f..db1794c 100755
--- a/tcl/target/stm32f7x.cfg
+++ b/tcl/target/stm32f7x.cfg
@@ -65,9 +65,9 @@ flash bank $_CHIPNAME.otp stm32f2x 0x1ff0f000 0 0 0 $_TARGETNAME
 flash bank $_CHIPNAME.itcm-flash.alias virtual 0x00200000 0 0 0 $_TARGETNAME $_FLASHNAME
 
 # adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
-adapter_khz 2000
+adapter speed 2000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
@@ -162,12 +162,12 @@ $_TARGETNAME configure -event reset-init {
 	if {[using_jtag]} {
 		[[target current] cget -dap] memaccess 16
 	} {
-		adapter_khz 8000
+		adapter speed 8000
 	}
 }
 
 $_TARGETNAME configure -event reset-start {
 	# Reduce speed since CPU speed will slow down to 16MHz with the reset
-	adapter_khz 2000
+	adapter speed 2000
 }
 
diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg
index 1d11654..2d92eca 100644
--- a/tcl/target/stm32h7x.cfg
+++ b/tcl/target/stm32h7x.cfg
@@ -105,9 +105,9 @@ if {[set $_CHIPNAME.DUAL_CORE]} {
 targets $_CHIPNAME.cpu0
 
 # Clock after reset is HSI at 64 MHz, no need of PLL
-adapter_khz 1800
+adapter speed 1800
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
@@ -170,7 +170,7 @@ $_CHIPNAME.cpu0 configure -event trace-config {
 
 $_CHIPNAME.cpu0 configure -event reset-init {
 	# Clock after reset is HSI at 64 MHz, no need of PLL
-	adapter_khz 4000
+	adapter speed 4000
 }
 
 if {[set $_CHIPNAME.DUAL_CORE]} {
diff --git a/tcl/target/stm32l0.cfg b/tcl/target/stm32l0.cfg
index e09af80..7653d13 100644
--- a/tcl/target/stm32l0.cfg
+++ b/tcl/target/stm32l0.cfg
@@ -24,9 +24,9 @@ if { [info exists WORKAREASIZE] } {
 
 # JTAG speed should be <= F_CPU/6.
 # F_CPU after reset is ~2MHz, so use F_JTAG max = 333kHz
-adapter_khz 300
+adapter speed 300
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 
 if { [info exists CPUTAPID] } {
     set _CPUTAPID $CPUTAPID
@@ -70,7 +70,7 @@ proc stm32l0_enable_HSI16 {} {
 	while { ([ mrw 0x4002100c ] & 0x0c) != 0x04 } { }
 
 	# Increase speed
-	adapter_khz 2500
+	adapter speed 2500
 }
 
 $_TARGETNAME configure -event reset-init {
@@ -78,7 +78,7 @@ $_TARGETNAME configure -event reset-init {
 }
 
 $_TARGETNAME configure -event reset-start {
-	adapter_khz 300
+	adapter speed 300
 }
 
 $_TARGETNAME configure -event examine-end {
diff --git a/tcl/target/stm32l1.cfg b/tcl/target/stm32l1.cfg
index 0933151..a81d7c7 100644
--- a/tcl/target/stm32l1.cfg
+++ b/tcl/target/stm32l1.cfg
@@ -23,9 +23,9 @@ if { [info exists WORKAREASIZE] } {
 
 # JTAG speed should be <= F_CPU/6.
 # F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz
-adapter_khz 300
+adapter speed 300
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
@@ -79,7 +79,7 @@ proc stm32l_enable_HSI {} {
 	mmw 0x40023808 0x00000001 0
 
 	# Increase JTAG speed
-	adapter_khz 2000
+	adapter speed 2000
 }
 
 $_TARGETNAME configure -event reset-init {
@@ -87,7 +87,7 @@ $_TARGETNAME configure -event reset-init {
 }
 
 $_TARGETNAME configure -event reset-start {
-	adapter_khz 300
+	adapter speed 300
 }
 
 $_TARGETNAME configure -event examine-end {
diff --git a/tcl/target/stm32l4x.cfg b/tcl/target/stm32l4x.cfg
index 496b47a..46e6f7e 100644
--- a/tcl/target/stm32l4x.cfg
+++ b/tcl/target/stm32l4x.cfg
@@ -56,9 +56,9 @@ flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
 #
 # Note that there is a pretty wide band where things are
 # more or less stable, see http://openocd.zylin.com/#/c/3366/
-adapter_khz 500
+adapter speed 500
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
@@ -78,12 +78,12 @@ $_TARGETNAME configure -event reset-init {
 	mww 0x40022000 0x00000103   ;# FLASH_ACR = PRFTBE | 3(Latency)
 	mww 0x40021000 0x00000099   ;# RCC_CR = MSI_ON | MSIRGSEL | MSI Range 9
 	# Boost JTAG frequency
-	adapter_khz 4000
+	adapter speed 4000
 }
 
 $_TARGETNAME configure -event reset-start {
 	# Reset clock is MSI (4 MHz)
-	adapter_khz 500
+	adapter speed 500
 }
 
 $_TARGETNAME configure -event examine-end {
diff --git a/tcl/target/stm8l.cfg b/tcl/target/stm8l.cfg
index 5cc99e1..386f371 100644
--- a/tcl/target/stm8l.cfg
+++ b/tcl/target/stm8l.cfg
@@ -79,7 +79,7 @@ $_TARGETNAME configure -optionstart $_OPTIONSTART -optionend $_OPTIONEND -blocks
 $_TARGETNAME configure -enable_stm8l
 
 # The khz rate does not apply here, only slow <0> and fast <1>
-adapter_khz 1
+adapter speed 1
 
 reset_config srst_only
 
diff --git a/tcl/target/stm8s.cfg b/tcl/target/stm8s.cfg
index d55e61b..4768068 100644
--- a/tcl/target/stm8s.cfg
+++ b/tcl/target/stm8s.cfg
@@ -76,7 +76,7 @@ $_TARGETNAME configure -optionstart $_OPTIONSTART -optionend $_OPTIONEND -blocks
 #$_TARGETNAME configure -enable_step_irq
 
 # The khz rate does not apply here, only slow <0> and fast <1>
-adapter_khz 1
+adapter speed 1
 
 reset_config srst_only
 
diff --git a/tcl/target/str710.cfg b/tcl/target/str710.cfg
index d26a8b1..29faaaa 100644
--- a/tcl/target/str710.cfg
+++ b/tcl/target/str710.cfg
@@ -1,5 +1,5 @@
 #start slow, speed up after reset
-adapter_khz 10
+adapter speed 10
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
@@ -29,9 +29,9 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_C
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
 
-$_TARGETNAME configure -event reset-start { adapter_khz 10 }
+$_TARGETNAME configure -event reset-start { adapter speed 10 }
 $_TARGETNAME configure -event reset-init {
-	adapter_khz 6000
+	adapter speed 6000
 
 # Because the hardware cannot be interrogated for the protection state
 # of sectors, initialize all the sectors to be unprotected. The initial
diff --git a/tcl/target/str730.cfg b/tcl/target/str730.cfg
index 48d3134..9a27194 100644
--- a/tcl/target/str730.cfg
+++ b/tcl/target/str730.cfg
@@ -1,6 +1,6 @@
 #STR730 CPU
 
-adapter_khz 3000
+adapter speed 3000
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
@@ -27,15 +27,15 @@ reset_config trst_and_srst srst_pulls_trst
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
 
 #jtag nTRST and nSRST delay
-adapter_nsrst_delay 500
+adapter srst delay 500
 jtag_ntrst_delay 500
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm7tdmi -endian little -chain-position 0
 
-$_TARGETNAME configure -event reset-start { adapter_khz 10 }
+$_TARGETNAME configure -event reset-start { adapter speed 10 }
 $_TARGETNAME configure -event reset-init {
-	adapter_khz 3000
+	adapter speed 3000
 
 # Because the hardware cannot be interrogated for the protection state
 # of sectors, initialize all the sectors to be unprotected. The initial
diff --git a/tcl/target/str750.cfg b/tcl/target/str750.cfg
index ef6e795..335d5ad 100644
--- a/tcl/target/str750.cfg
+++ b/tcl/target/str750.cfg
@@ -19,7 +19,7 @@ if { [info exists CPUTAPID] } {
 }
 
 # jtag speed
-adapter_khz 10
+adapter speed 10
 
 #use combined on interfaces or targets that can't set TRST/SRST separately
 reset_config trst_and_srst srst_pulls_trst
@@ -29,15 +29,15 @@ reset_config trst_and_srst srst_pulls_trst
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
 
 #jtag nTRST and nSRST delay
-adapter_nsrst_delay 500
+adapter srst delay 500
 jtag_ntrst_delay 500
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm7tdmi -endian little -chain-position 0
 
-$_TARGETNAME configure -event reset-start { adapter_khz 10 }
+$_TARGETNAME configure -event reset-start { adapter speed 10 }
 $_TARGETNAME configure -event reset-init {
-	adapter_khz 3000
+	adapter speed 3000
 
 	init_smi
 # Because the hardware cannot be interrogated for the protection state
diff --git a/tcl/target/str912.cfg b/tcl/target/str912.cfg
index 36c0b2a..7426276 100644
--- a/tcl/target/str912.cfg
+++ b/tcl/target/str912.cfg
@@ -13,9 +13,9 @@ if { [info exists ENDIAN] } {
 }
 
 # jtag speed. We need to stick to 16kHz until we've finished reset.
-adapter_khz 16
+adapter speed 16
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 
 #use combined on interfaces or targets that can't set TRST/SRST separately
@@ -48,11 +48,11 @@ jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BST
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
 
-$_TARGETNAME configure -event reset-start { adapter_khz 16 }
+$_TARGETNAME configure -event reset-start { adapter speed 16 }
 
 $_TARGETNAME configure -event reset-init {
 	# We can increase speed now that we know the target is halted.
-	#adapter_khz 3000
+	#adapter speed 3000
 
 	# -- Enable 96K RAM
 	# PFQBC enabled / DTCM & AHB wait-states disabled
diff --git a/tcl/target/ti_calypso.cfg b/tcl/target/ti_calypso.cfg
index 9d3b293..52a84fb 100644
--- a/tcl/target/ti_calypso.cfg
+++ b/tcl/target/ti_calypso.cfg
@@ -32,7 +32,7 @@ if { [info exists WORKAREASIZE] } {
 	set _WORKAREASIZE 0x10000
 }
 
-adapter_khz 1000
+adapter speed 1000
 
 reset_config trst_and_srst
 
diff --git a/tcl/target/ti_cc26x0.cfg b/tcl/target/ti_cc26x0.cfg
index 7efecb6..8d8a0df 100644
--- a/tcl/target/ti_cc26x0.cfg
+++ b/tcl/target/ti_cc26x0.cfg
@@ -53,4 +53,4 @@ set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
 
 reset_config srst_only
-adapter_nsrst_delay 100
+adapter srst delay 100
diff --git a/tcl/target/ti_cc32xx.cfg b/tcl/target/ti_cc32xx.cfg
index bc3038d..6f91d3f 100644
--- a/tcl/target/ti_cc32xx.cfg
+++ b/tcl/target/ti_cc32xx.cfg
@@ -61,4 +61,4 @@ if { [info exists WORKAREASIZE] } {
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
 reset_config srst_only
-adapter_nsrst_delay 1100
+adapter srst delay 1100
diff --git a/tcl/target/ti_dm355.cfg b/tcl/target/ti_dm355.cfg
index 4f8f523..91c0087 100644
--- a/tcl/target/ti_dm355.cfg
+++ b/tcl/target/ti_dm355.cfg
@@ -98,8 +98,8 @@ $_TARGETNAME configure \
 # be absolutely certain the JTAG clock will work with the worst-case
 # CLKIN = 24 MHz (best case: 36 MHz) even when no bootloader turns
 # on the PLL and starts using it.  OK to speed up after clock setup.
-adapter_khz 1500
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
 
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable
diff --git a/tcl/target/ti_dm365.cfg b/tcl/target/ti_dm365.cfg
index 0db83db..8b52746 100644
--- a/tcl/target/ti_dm365.cfg
+++ b/tcl/target/ti_dm365.cfg
@@ -90,8 +90,8 @@ $_TARGETNAME configure \
 # be absolutely certain the JTAG clock will work with the worst-case
 # CLKIN = 19.2 MHz (best case: 36 MHz) even when no bootloader turns
 # on the PLL and starts using it.  OK to speed up after clock setup.
-adapter_khz 1500
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
 
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable
diff --git a/tcl/target/ti_dm6446.cfg b/tcl/target/ti_dm6446.cfg
index fa1e6e9..ccc650a 100644
--- a/tcl/target/ti_dm6446.cfg
+++ b/tcl/target/ti_dm6446.cfg
@@ -70,8 +70,8 @@ $_TARGETNAME configure -work-area-phys 0x0000a000 -work-area-size 0x2000
 # be absolutely certain the JTAG clock will work with the worst-case
 # CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
 # on the PLL and starts using it.  OK to speed up after clock setup.
-adapter_khz 1500
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
 
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable
diff --git a/tcl/target/ti_msp432.cfg b/tcl/target/ti_msp432.cfg
index 3407f75..146e7ee 100644
--- a/tcl/target/ti_msp432.cfg
+++ b/tcl/target/ti_msp432.cfg
@@ -48,4 +48,4 @@ set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
 
 reset_config srst_only
-adapter_nsrst_delay 100
+adapter srst delay 100
diff --git a/tcl/target/ti_tms570.cfg b/tcl/target/ti_tms570.cfg
index ce3a176..d06ff97 100644
--- a/tcl/target/ti_tms570.cfg
+++ b/tcl/target/ti_tms570.cfg
@@ -1,4 +1,4 @@
-adapter_khz 1500
+adapter speed 1500
 
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/tmpa900.cfg b/tcl/target/tmpa900.cfg
index 3ba3591..8e70700 100644
--- a/tcl/target/tmpa900.cfg
+++ b/tcl/target/tmpa900.cfg
@@ -28,7 +28,7 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CP
 
 #use combined on interfaces or targets that can't set TRST/SRST separately
 reset_config trst_and_srst
-adapter_nsrst_delay 20
+adapter srst delay 20
 jtag_ntrst_delay 20
 
 ######################
diff --git a/tcl/target/tmpa910.cfg b/tcl/target/tmpa910.cfg
index 5d41c8c..d933c0b 100644
--- a/tcl/target/tmpa910.cfg
+++ b/tcl/target/tmpa910.cfg
@@ -28,7 +28,7 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CP
 
 #use combined on interfaces or targets that can't set TRST/SRST separately
 reset_config trst_and_srst
-adapter_nsrst_delay 20
+adapter srst delay 20
 jtag_ntrst_delay 20
 
 ######################
diff --git a/tcl/target/u8500.cfg b/tcl/target/u8500.cfg
index 7ff3929..faaf97d 100644
--- a/tcl/target/u8500.cfg
+++ b/tcl/target/u8500.cfg
@@ -314,7 +314,7 @@ global _MAXSPEED
 set _MAXSPEED $MAXSPEED
 }
 global _MAXSPEED 
-adapter_khz $_MAXSPEED
+adapter speed $_MAXSPEED
 
 
 gdb_breakpoint_override hard
diff --git a/tcl/target/vybrid_vf6xx.cfg b/tcl/target/vybrid_vf6xx.cfg
index 7cb916d..c888d25 100644
--- a/tcl/target/vybrid_vf6xx.cfg
+++ b/tcl/target/vybrid_vf6xx.cfg
@@ -34,4 +34,4 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 set _TARGETNAME $_CHIPNAME.cpu
 target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap -dbgbase 0xc0088000
 target create ${_TARGETNAME}1 cortex_m -dap $_CHIPNAME.dap -ap-num 3 -defer-examine
-adapter_khz 1000
+adapter speed 1000
diff --git a/tcl/target/xmc1xxx.cfg b/tcl/target/xmc1xxx.cfg
index e693b59..eb94d7b 100644
--- a/tcl/target/xmc1xxx.cfg
+++ b/tcl/target/xmc1xxx.cfg
@@ -38,4 +38,4 @@ $_TARGETNAME configure -work-area-phys 0x20000000 \
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME xmc1xxx 0x10000000 0 0 0 $_TARGETNAME
 
-adapter_khz 1000
+adapter speed 1000
diff --git a/tcl/target/xmc4xxx.cfg b/tcl/target/xmc4xxx.cfg
index e106d34..3020b28 100644
--- a/tcl/target/xmc4xxx.cfg
+++ b/tcl/target/xmc4xxx.cfg
@@ -57,4 +57,4 @@ if { ![using_hla] } {
 	cortex_m reset_config sysresetreq
 }
 
-adapter_khz 1000
+adapter speed 1000
diff --git a/tcl/target/zynq_7000.cfg b/tcl/target/zynq_7000.cfg
index 1562768..b4b6f9f 100644
--- a/tcl/target/zynq_7000.cfg
+++ b/tcl/target/zynq_7000.cfg
@@ -23,7 +23,7 @@ target create ${_TARGETNAME}1 cortex_a -dap $_CHIPNAME.dap \
     -coreid 1 -dbgbase 0x80092000
 target smp ${_TARGETNAME}0 ${_TARGETNAME}1
 
-adapter_khz 1000
+adapter speed 1000
 
 ${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit"
 ${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit"
diff --git a/tcl/target/к1879xб1я.cfg b/tcl/target/к1879xб1я.cfg
index 7d8c113..0a8467f 100644
--- a/tcl/target/к1879xб1я.cfg
+++ b/tcl/target/к1879xб1я.cfg
@@ -1,7 +1,7 @@
 # СБИС К1879ХБ1Я
 # http://www.module.ru/catalog/micro/mikroshema_dekodera_cifrovogo_televizionnogo_signala_sbis_k1879hb1ya/
 
-adapter_khz 1000
+adapter speed 1000
 
 if { [info exists CHIPNAME] } {
     set _CHIPNAME $CHIPNAME