Merge branch 'master' into from_upstream

Conflicts: .gitmodules .travis.yml jimtcl src/jtag/core.c src/jtag/drivers/ftdi.c src/jtag/drivers/libjaylink src/jtag/drivers/mpsse.c src/jtag/drivers/stlink_usb.c src/rtos/hwthread.c src/target/riscv/riscv-013.c src/target/riscv/riscv.c tcl/board/sifive-hifive1-revb.cfg Change-Id: I2d26ebeffb4c1374730d2e20e6e2a7710403657c
author: Tim Newsome <tim@sifive.com> 2020-06-23 13:05:43 -0700
committer: Tim Newsome <tim@sifive.com> 2020-06-23 13:05:43 -0700
commit: e07613de332d2cda48cd1a845b6e19171f084571 (patch)
tree: e32451d4730030a2b1e8539cbfd6abf590a07896 /tcl/board
parent: 4579dd93586ab361f40da6cbd9e3e0681efc866b (diff)
parent: 8833c889da07eae750bcbc11215cc84323de9b74 (diff)
download: riscv-openocd-e07613de332d2cda48cd1a845b6e19171f084571.zip
riscv-openocd-e07613de332d2cda48cd1a845b6e19171f084571.tar.gz
riscv-openocd-e07613de332d2cda48cd1a845b6e19171f084571.tar.bz2
151 files changed, 522 insertions, 396 deletions
diff --git a/tcl/board/actux3.cfg b/tcl/board/actux3.cfg
index 5435ff8..0de4cb4 100644
--- a/tcl/board/actux3.cfg
+++ b/tcl/board/actux3.cfg
@@ -4,7 +4,7 @@
 
 reset_config trst_and_srst separate
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 
 source [find target/ixp42x.cfg]
diff --git a/tcl/board/adsp-sc584-ezbrd.cfg b/tcl/board/adsp-sc584-ezbrd.cfg
index 1054a94..82df381 100644
--- a/tcl/board/adsp-sc584-ezbrd.cfg
+++ b/tcl/board/adsp-sc584-ezbrd.cfg
@@ -25,7 +25,6 @@ source [find interface/jlink.cfg]
 transport select swd
 
 # chosen speed is 'safe' choice, but your adapter may be capable of more
-adapter_khz 400
+adapter speed 400
 
 source [find target/adsp-sc58x.cfg]
-
diff --git a/tcl/board/alphascale_asm9260_ek.cfg b/tcl/board/alphascale_asm9260_ek.cfg
index 46e8a5b..1c12682 100644
--- a/tcl/board/alphascale_asm9260_ek.cfg
+++ b/tcl/board/alphascale_asm9260_ek.cfg
@@ -23,7 +23,7 @@ $_TARGETNAME configure -event reset-init {
 
 	# select PLL as main source
 	mww 0x80040120 0x1
-	# disable and enble main clk to update changes?
+	# disable and enable main clk to update changes?
 	mww 0x80040124 0x0
 	mww 0x80040124 0x1
 
diff --git a/tcl/board/altera_sockit.cfg b/tcl/board/altera_sockit.cfg
index 5694143..eb4c863 100644
--- a/tcl/board/altera_sockit.cfg
+++ b/tcl/board/altera_sockit.cfg
@@ -7,7 +7,7 @@
 
 # openocd does not currently support the on-board USB Blaster II.
 # Install the JTAG header and use a USB Blaster instead.
-interface usb_blaster
+adapter driver usb_blaster
 
 source [find target/altera_fpgasoc.cfg]
 
@@ -15,5 +15,4 @@ source [find target/altera_fpgasoc.cfg]
 #usb_blaster_vid_pid 0x6810 0x09fb
 #usb_blaster_device_desc "USB-Blaster II"
 
-adapter_khz 100
-
+adapter speed 100
diff --git a/tcl/board/am3517evm.cfg b/tcl/board/am3517evm.cfg
index 2bff512..8d6eba1 100644
--- a/tcl/board/am3517evm.cfg
+++ b/tcl/board/am3517evm.cfg
@@ -18,4 +18,3 @@ source [find target/amdm37x.cfg]
 reset_config trst_only
 
 # "amdm37x_dbginit am35x.cpu" needs to be run after init.
-
diff --git a/tcl/board/arm_evaluator7t.cfg b/tcl/board/arm_evaluator7t.cfg
index 52de57a..96d859c 100644
--- a/tcl/board/arm_evaluator7t.cfg
+++ b/tcl/board/arm_evaluator7t.cfg
@@ -7,4 +7,3 @@ source [find target/samsung_s3c4510.cfg]
 #  Add (A) sdram configuration
 #  Add (B) flash cfi programing configuration
 #
-
diff --git a/tcl/board/arm_musca_a.cfg b/tcl/board/arm_musca_a.cfg
index fa7cf5e..25f8ce6 100644
--- a/tcl/board/arm_musca_a.cfg
+++ b/tcl/board/arm_musca_a.cfg
@@ -15,7 +15,7 @@
 source [find target/swj-dp.tcl]
 
 # set a safe JTAG clock speed, can be overridden
-adapter_khz 1000
+adapter speed 1000
 
 global _CHIPNAME
 if { [info exists CHIPNAME] } {
diff --git a/tcl/board/arty_s7.cfg b/tcl/board/arty_s7.cfg
index ca7d3f1..5ab4083 100644
--- a/tcl/board/arty_s7.cfg
+++ b/tcl/board/arty_s7.cfg
@@ -10,7 +10,7 @@ source [find interface/ftdi/digilent-hs1.cfg]
 source [find cpld/xilinx-xc7.cfg]
 source [find cpld/jtagspi.cfg]
 
-adapter_khz 25000
+adapter speed 25000
 
 # Usage:
 #
diff --git a/tcl/board/at91cap7a-stk-sdram.cfg b/tcl/board/at91cap7a-stk-sdram.cfg
index 9bc02e8..8395ba3 100644
--- a/tcl/board/at91cap7a-stk-sdram.cfg
+++ b/tcl/board/at91cap7a-stk-sdram.cfg
@@ -28,7 +28,7 @@ target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAM
 
 $_TARGETNAME configure -event reset-start {
 	# start off real slow when we're running off internal RC oscillator
-	adapter_khz 32
+	adapter speed 32
 }
 
 proc peek32 {address} {
@@ -43,13 +43,13 @@ proc wait_state {expression} {
 			return
 		}
 	}
-	return -code 1 "Timed out"	
+	return -code 1 "Timed out"
 }
 
 # Use a global variable here to be able to tinker interactively with
 # post reset jtag frequency.
 global post_reset_khz
-# Danger!!!! Even 16MHz kinda works with this target, but 
+# Danger!!!! Even 16MHz kinda works with this target, but
 # it needs to be as low as 2000kHz to be stable.
 set post_reset_khz 2000
 
@@ -61,25 +61,25 @@ $_TARGETNAME configure -event reset-init {
 	mww 0xfffffd08 0xa5000001
 	# Enable main oscillator
 	mww 0xFFFFFc20  0x00000f01
-	wait_state {expr {([peek32 0xFFFFFC68] & 0x1) == 0}}  
+	wait_state {expr {([peek32 0xFFFFFC68] & 0x1) == 0}}
 
 	# Set PLLA to 96MHz
 	mww 0xFFFFFc28 0x20072801
-	wait_state {expr {([peek32 0xFFFFFC68] & 0x2) == 0}}  
+	wait_state {expr {([peek32 0xFFFFFC68] & 0x2) == 0}}
 
 	# Select prescaler
 	mww 0xFFFFFC30 0x00000004
-	wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}  
+	wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
 
 	# Select master clock to 48MHz
 	mww 0xFFFFFC30 0x00000006
-	wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}  
+	wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
 
 	echo "Master clock ok."
-	
+
 	# Now that we're up and running, crank up speed!
-	global post_reset_khz ;	adapter_khz $post_reset_khz
-	
+	global post_reset_khz ;	adapter speed $post_reset_khz
+
 	echo "Configuring the SDRAM controller..."
 
 	# Configure EBI Chip select for SDRAM
@@ -95,7 +95,7 @@ $_TARGETNAME configure -event reset-init {
 
 	# Configure SDRAMC CR
 	mww 0xFFFFEA08 0xA63392F9
- 
+
 	# NOP command
 	mww 0xFFFFEA00 0x1
 	mww 0x20000000 0
@@ -151,7 +151,7 @@ $_TARGETNAME configure -event reset-init {
 
 	#remap internal memory at address 0x0
 	mww 0xffffef00 0x3
-	
+
 	echo "SDRAM configuration ok."
 }
 
@@ -162,4 +162,3 @@ arm7_9 fast_memory_access enable
 
 #set _FLASHNAME $_CHIPNAME.flash
 #flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
-
diff --git a/tcl/board/at91eb40a.cfg b/tcl/board/at91eb40a.cfg
index d8a82a5..d314e18 100644
--- a/tcl/board/at91eb40a.cfg
+++ b/tcl/board/at91eb40a.cfg
@@ -64,4 +64,4 @@ $_TARGETNAME configure -event reset-init {
 }
 
 # This target is pretty snappy...
-adapter_khz 16000
+adapter speed 16000
diff --git a/tcl/board/at91rm9200-dk.cfg b/tcl/board/at91rm9200-dk.cfg
index f484fde..b8ec00e 100644
--- a/tcl/board/at91rm9200-dk.cfg
+++ b/tcl/board/at91rm9200-dk.cfg
@@ -19,7 +19,7 @@ flash bank $_FLASHNAME cfi 0x10000000 0x00200000 2 2 $_TARGETNAME
 proc at91rm9200_dk_init { } {
     # Try to run at 1khz... Yea, that slow!
     # Chip is really running @ 32khz
-    adapter_khz 8
+    adapter speed 8
 
     mww 0xfffffc64 0xffffffff
     ##  disable all clocks but system clock
@@ -45,7 +45,7 @@ proc at91rm9200_dk_init { } {
     #========================================
     # CPU now runs at 180mhz
     # SYS runs at 60mhz.
-    adapter_khz 40000
+    adapter speed 40000
     #========================================
 
 
diff --git a/tcl/board/at91rm9200-ek.cfg b/tcl/board/at91rm9200-ek.cfg
index a3f253a..958bc9d 100644
--- a/tcl/board/at91rm9200-ek.cfg
+++ b/tcl/board/at91rm9200-ek.cfg
@@ -19,12 +19,12 @@ set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
 
 # The chip may run @ 32khz, so set a really low JTAG speed
-adapter_khz 8
+adapter speed 8
 
 proc at91rm9200_ek_init { } {
 	# Try to run at 1khz... Yea, that slow!
 	# Chip is really running @ 32khz
-	adapter_khz 8
+	adapter speed 8
 
 	mww 0xfffffc64 0xffffffff
 	## disable all clocks but system clock
@@ -61,7 +61,7 @@ proc at91rm9200_ek_init { } {
 	#========================================
 	# CPU now runs at 180mhz
 	# SYS runs at 60mhz.
-	adapter_khz 40000
+	adapter speed 40000
 	#========================================
 
 	## Init SDRAM
diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg
index 741d601..03296c5 100644
--- a/tcl/board/at91sam9g20-ek.cfg
+++ b/tcl/board/at91sam9g20-ek.cfg
@@ -19,7 +19,7 @@ set _FLASHTYPE nandflash_cs3
 
 reset_config srst_only
 
-adapter_nsrst_delay 200
+adapter srst delay 200
 jtag_ntrst_delay 200
 
 # If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the
@@ -54,7 +54,7 @@ proc at91sam9g20_reset_start { } {
 	# jtag speed without causing GDB keep alive problem.
 
 	arm7_9 fast_memory_access disable
-	adapter_khz 2                   ;# Slow-speed oscillator enabled at reset, so run jtag speed slow.
+	adapter speed 2                 ;# Slow-speed oscillator enabled at reset, so run jtag speed slow.
 	halt                            ;# Make sure processor is halted, or error will result in following steps.
 	wait_halt 10000
 	mww 0xfffffd08 0xa5000501       ;# RSTC_MR : enable user reset.
@@ -103,7 +103,7 @@ proc at91sam9g20_reset_init { } {
 
 	# Switch over to adaptive clocking.
 
-	adapter_khz 0
+	adapter speed 0
 
 	# Enable faster DCC downloads and memory accesses.
 
@@ -139,13 +139,13 @@ proc at91sam9g20_reset_init { } {
 	# (MT29F2G08AACWP) can be established by setting four registers in order:  SMC_SETUP3,
 	# SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.  Computing the exact values of these registers
 	# is a little tedious to do here.  If you have questions about how to do this, Atmel has
-	# a decent application note #6255B that covers this process. 
+	# a decent application note #6255B that covers this process.
 
 	mww 0xffffec30 0x00020002	;# SMC_SETUP3 : 2 clock cycle setup for NRD and NWE
 	mww 0xffffec34 0x04040404	;# SMC_PULSE3 : 4 clock cycle pulse for all signals
 	mww 0xffffec38 0x00070006	;# SMC_CYCLE3 : 7 clock cycle NRD and 6 NWE cycle
-	mww 0xffffec3C 0x00020003	;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW, 
-   
+	mww 0xffffec3C 0x00020003	;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
+
 	mww 0xffffe800 0x00000001	;# ECC_CR : reset the ECC parity registers
 	mww 0xffffe804 0x00000002	;# ECC_MR : page size is 2112 words (word is 8 bits)
 
@@ -169,7 +169,7 @@ proc at91sam9g20_reset_init { } {
 	#	TRC = 9 cycles
 	#	TWR = 2 cycles
 	#	9 column, 13 row, 4 banks
-	#	refresh equal to or less then 7.8 us for commerical/industrial rated devices
+	#	refresh equal to or less then 7.8 us for commercial/industrial rated devices
 	#
 	#	Thus SDRAM_CR = 0xa6339279
 
@@ -216,4 +216,3 @@ proc at91sam9g20_reset_init { } {
 
 	mww 0xffffea04 0x0000039c
 }
-
diff --git a/tcl/board/atmel_at91sam7s-ek.cfg b/tcl/board/atmel_at91sam7s-ek.cfg
index d7e8486..48edfc9 100644
--- a/tcl/board/atmel_at91sam7s-ek.cfg
+++ b/tcl/board/atmel_at91sam7s-ek.cfg
@@ -4,5 +4,3 @@
 set CHIPNAME at91sam7s256
 
 source [find target/at91sam7sx.cfg]
-
-
diff --git a/tcl/board/atmel_sam3n_ek.cfg b/tcl/board/atmel_sam3n_ek.cfg
index 2ae73eb..e43008f 100644
--- a/tcl/board/atmel_sam3n_ek.cfg
+++ b/tcl/board/atmel_sam3n_ek.cfg
@@ -7,6 +7,6 @@ reset_config srst_only
 
 set CHIPNAME at91sam3n4c
 
-adapter_khz 32
+adapter speed 32
 
 source [find target/at91sam3nXX.cfg]
diff --git a/tcl/board/atmel_sam3u_ek.cfg b/tcl/board/atmel_sam3u_ek.cfg
index 13d930b..1584879 100644
--- a/tcl/board/atmel_sam3u_ek.cfg
+++ b/tcl/board/atmel_sam3u_ek.cfg
@@ -1,4 +1,3 @@
 source [find target/at91sam3u4e.cfg]
 
 reset_config srst_only
-
diff --git a/tcl/board/avnet_ultrazed-eg.cfg b/tcl/board/avnet_ultrazed-eg.cfg
index 9879bfc..3e4a11a 100644
--- a/tcl/board/avnet_ultrazed-eg.cfg
+++ b/tcl/board/avnet_ultrazed-eg.cfg
@@ -9,7 +9,7 @@ transport select jtag
 reset_config none
 
 # slow default clock
-adapter_khz 1000
+adapter speed 1000
 
 set CHIPNAME uscale
 
diff --git a/tcl/board/bcm28155_ap.cfg b/tcl/board/bcm28155_ap.cfg
index fb729e1..5d3d22a 100644
--- a/tcl/board/bcm28155_ap.cfg
+++ b/tcl/board/bcm28155_ap.cfg
@@ -1,9 +1,8 @@
 # BCM28155_AP
 
-adapter_khz 20000
+adapter speed 20000
 
 set CHIPNAME bcm28155
 source [find target/bcm281xx.cfg]
 
 reset_config trst_and_srst
-
diff --git a/tcl/board/bluefield.cfg b/tcl/board/bluefield.cfg
new file mode 100644
index 0000000..3058d48
--- /dev/null
+++ b/tcl/board/bluefield.cfg
@@ -0,0 +1,6 @@
+#
+# Board configuration for BlueField SoC.
+#
+
+source [find interface/rshim.cfg]
+source [find target/bluefield.cfg]
diff --git a/tcl/board/colibri.cfg b/tcl/board/colibri.cfg
index 7c1f1cb..0f30afd 100644
--- a/tcl/board/colibri.cfg
+++ b/tcl/board/colibri.cfg
@@ -1,13 +1,9 @@
 # Toradex Colibri PXA270
 source [find target/pxa270.cfg]
 reset_config trst_and_srst srst_push_pull
-adapter_nsrst_assert_width 40
+adapter srst pulse_width 40
 
 # CS0 -- one bank of CFI flash, 32 MBytes
 # the bank is 32-bits wide, two 16-bit chips in parallel
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
-
-
-
-
diff --git a/tcl/board/crossbow_tech_imote2.cfg b/tcl/board/crossbow_tech_imote2.cfg
index 002b537..277c353 100644
--- a/tcl/board/crossbow_tech_imote2.cfg
+++ b/tcl/board/crossbow_tech_imote2.cfg
@@ -4,7 +4,7 @@ set  CHIPNAME imote2
 source [find target/pxa270.cfg]
 
 # longer-than-normal reset delay
-adapter_nsrst_delay 800
+adapter srst delay 800
 
 reset_config trst_and_srst separate
 
diff --git a/tcl/board/csb337.cfg b/tcl/board/csb337.cfg
index 5e225f5..a9d0139 100644
--- a/tcl/board/csb337.cfg
+++ b/tcl/board/csb337.cfg
@@ -19,7 +19,7 @@ if { [info exists ETM_DRIVER] } {
 
 proc csb337_clk_init { } {
 	# CPU is in Slow Clock Mode (32KiHz) ... needs slow JTAG clock
-	adapter_khz 8
+	adapter speed 8
 
 	# CKGR_MOR:  start main oscillator (3.6864 MHz)
 	mww 0xfffffc20 0xff01
@@ -37,7 +37,7 @@ proc csb337_clk_init { } {
 	sleep 20
 
 	# CPU is in Normal Mode ... allows faster JTAG clock speed
-	adapter_khz 40000
+	adapter speed 40000
 }
 
 proc csb337_nor_init { } {
diff --git a/tcl/board/csb732.cfg b/tcl/board/csb732.cfg
index 4d6f0e4..35e397f 100644
--- a/tcl/board/csb732.cfg
+++ b/tcl/board/csb732.cfg
@@ -3,7 +3,7 @@ source [find target/imx35.cfg]
 
 # Determined by trial and error
 reset_config trst_and_srst combined
-adapter_nsrst_delay 200
+adapter srst delay 200
 jtag_ntrst_delay 200
 
 $_TARGETNAME configure -event gdb-attach { reset init }
diff --git a/tcl/board/digi_connectcore_wi-9c.cfg b/tcl/board/digi_connectcore_wi-9c.cfg
index 8a8d4c3..43ad1c9 100644
--- a/tcl/board/digi_connectcore_wi-9c.cfg
+++ b/tcl/board/digi_connectcore_wi-9c.cfg
@@ -36,7 +36,7 @@ if { [info exists CPUTAPID] } {
 set _TARGETNAME $_CHIPNAME.cpu
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
-adapter_nsrst_delay 200
+adapter srst delay 200
 jtag_ntrst_delay 0
 
 
diff --git a/tcl/board/digilent_analog_discovery.cfg b/tcl/board/digilent_analog_discovery.cfg
index d356fc0..954e540 100644
--- a/tcl/board/digilent_analog_discovery.cfg
+++ b/tcl/board/digilent_analog_discovery.cfg
@@ -7,12 +7,12 @@
 # https://github.com/bvanheu/urjtag-ad/commit/8bd883ee01d134f94b79cbbd00df42cd03bafd71
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Digilent USB Device"
 ftdi_vid_pid 0x0403 0x6014
 
 ftdi_layout_init 0x8008 0x800b
 
-adapter_khz 25000
+adapter speed 25000
 
 source [find cpld/xilinx-xc6s.cfg]
diff --git a/tcl/board/dk-tm4c129.cfg b/tcl/board/dk-tm4c129.cfg
index f1171af..2c7de29 100755..100644
--- a/tcl/board/dk-tm4c129.cfg
+++ b/tcl/board/dk-tm4c129.cfg
@@ -1,14 +1,3 @@
-#
-# TI Tiva C DK-TM4C129X Connected Development Kit
-#
-# http://www.ti.com/tool/dk-tm4c129x
-#
+echo "WARNING: board/dk-tm4c129.cfg is deprecated, please switch to board/ti_dk-tm4c129.cfg"
 
-source [find interface/ti-icdi.cfg]
-
-transport select hla_jtag
-
-set WORKAREASIZE 0x8000
-set CHIPNAME tm4c129xnczad
-
-source [find target/stellaris.cfg]
+source [find board/ti_dk-tm4c129.cfg]
diff --git a/tcl/board/dm365evm.cfg b/tcl/board/dm365evm.cfg
index 8f268c4..3b29dd8 100644
--- a/tcl/board/dm365evm.cfg
+++ b/tcl/board/dm365evm.cfg
@@ -103,7 +103,7 @@ proc dm365evm_init {} {
 	echo "Initialize DM365 EVM board"
 
 	# CLKIN	= 24 MHz ... can't talk quickly to ARM yet
-	adapter_khz 1500
+	adapter speed 1500
 
 	# FIXME -- PLL init
 
@@ -143,5 +143,3 @@ proc dm365evm_init {} {
 
 	flashprobe
 }
-
-
diff --git a/tcl/board/dp_busblaster_v3.cfg b/tcl/board/dp_busblaster_v3.cfg
index f21197b..a9974d9 100644
--- a/tcl/board/dp_busblaster_v3.cfg
+++ b/tcl/board/dp_busblaster_v3.cfg
@@ -4,7 +4,7 @@
 # http://dangerousprototypes.com/docs/Bus_Blaster
 #
 # To reprogram the on-board CPLD do:
-# openocd -f board/dp_busblaster_v3.cfg -c "adapter_khz 1000; init; svf <path_to_svf>; shutdown"
+# openocd -f board/dp_busblaster_v3.cfg -c "adapter speed 1000; init; svf <path_to_svf>; shutdown"
 #
 
 source [find interface/ftdi/dp_busblaster.cfg]
diff --git a/tcl/board/efm32.cfg b/tcl/board/efm32.cfg
index d2bc9a6..adbdda7 100644
--- a/tcl/board/efm32.cfg
+++ b/tcl/board/efm32.cfg
@@ -5,7 +5,7 @@
 
 source [find interface/jlink.cfg]
 transport select swd
-adapter_khz 1000
+adapter speed 1000
 
 set CHIPNAME efm32
 source [find target/efm32.cfg]
diff --git a/tcl/board/eir.cfg b/tcl/board/eir.cfg
index a014e11..422db0d 100644
--- a/tcl/board/eir.cfg
+++ b/tcl/board/eir.cfg
@@ -91,4 +91,3 @@ $_TARGETNAME configure -event reset-init {
 	#
 	mww 0xfffffd08 0xa5000001
 }
-
diff --git a/tcl/board/ek-lm3s1968.cfg b/tcl/board/ek-lm3s1968.cfg
index 8d990b1..bbb04ba 100644
--- a/tcl/board/ek-lm3s1968.cfg
+++ b/tcl/board/ek-lm3s1968.cfg
@@ -5,7 +5,7 @@
 #
 
 # NOTE:  to use J-Link instead of the on-board interface,
-# you may also need to reduce adapter_khz to be about 1200.
+# you may also need to reduce adapter speed to be about 1200.
 # source [find interface/jlink.cfg]
 
 # include the FT2232 interface config for on-board JTAG interface
diff --git a/tcl/board/ek-tm4c123gxl.cfg b/tcl/board/ek-tm4c123gxl.cfg
index 4fc1050..3e497ba 100644
--- a/tcl/board/ek-tm4c123gxl.cfg
+++ b/tcl/board/ek-tm4c123gxl.cfg
@@ -1,13 +1,3 @@
-#
-# TI Tiva C Series ek-tm4c123gxl Launchpad Evaluation Kit
-#
-# http://www.ti.com/tool/ek-tm4c123gxl
-#
+echo "WARNING: board/ek-tm4c123gxl.cfg is deprecated, please switch to board/ti_ek-tm4c123gxl.cfg"
 
-source [find interface/ti-icdi.cfg]
-
-transport select hla_jtag
-
-set WORKAREASIZE 0x8000
-set CHIPNAME tm4c123gh6pm
-source [find target/stellaris.cfg]
+source [find board/ti_ek-tm4c123gxl.cfg]
diff --git a/tcl/board/ek-tm4c1294xl.cfg b/tcl/board/ek-tm4c1294xl.cfg
index b3f384c..6763866 100644
--- a/tcl/board/ek-tm4c1294xl.cfg
+++ b/tcl/board/ek-tm4c1294xl.cfg
@@ -1,14 +1,3 @@
-#
-# TI Tiva C Series ek-tm4c1294xl Launchpad Evaluation Kit
-#
-# http://www.ti.com/tool/ek-tm4c1294xl
-#
+echo "WARNING: board/ek-tm4c1294xl.cfg is deprecated, please switch to board/ti_ek-tm4c1294xl.cfg"
 
-source [find interface/ti-icdi.cfg]
-
-transport select hla_jtag
-
-set WORKAREASIZE 0x8000
-set CHIPNAME tm4c1294ncpdt
-
-source [find target/stellaris.cfg]
+source [find board/ti_ek-tm4c1294xl.cfg]
diff --git a/tcl/board/embedded-artists_lpc2478-32.cfg b/tcl/board/embedded-artists_lpc2478-32.cfg
index b036cd6..8ef9179 100644
--- a/tcl/board/embedded-artists_lpc2478-32.cfg
+++ b/tcl/board/embedded-artists_lpc2478-32.cfg
@@ -15,7 +15,7 @@ proc read_register {register} {
 
 proc init_board {} {
     # Delays on reset lines
-    adapter_nsrst_delay 500
+    adapter srst delay 500
     jtag_ntrst_delay 1
 
     # Adaptive JTAG clocking through RTCK.
@@ -151,4 +151,3 @@ proc enable_pll {} {
     mww 0xE01FC08C 0x000000AA       ;# PLLFEED
     mww 0xE01FC08C 0x00000055       ;# PLLFEED
 }
-
diff --git a/tcl/board/emcraft_imx8m-som-bsb.cfg b/tcl/board/emcraft_imx8m-som-bsb.cfg
index 5571d0e..248c0d4 100644
--- a/tcl/board/emcraft_imx8m-som-bsb.cfg
+++ b/tcl/board/emcraft_imx8m-som-bsb.cfg
@@ -6,13 +6,13 @@
 transport select jtag
 
 # set a safe JTAG clock speed, can be overridden
-adapter_khz 1000
+adapter speed 1000
 
 # SRST and TRST are wired up
 reset_config trst_and_srst
 
 # delay after SRST goes inactive
-adapter_nsrst_delay 70
+adapter srst delay 70
 
 # board has an i.MX8MQ with 4 Cortex-A53 cores
 set CHIPNAME imx8mq
diff --git a/tcl/board/ethernut3.cfg b/tcl/board/ethernut3.cfg
index ad45527..72fc5ad 100644
--- a/tcl/board/ethernut3.cfg
+++ b/tcl/board/ethernut3.cfg
@@ -20,13 +20,13 @@ flash bank $_FLASHNAME cfi 0x10000000 0x400000 2 2 $_TARGETNAME
 # Micrel MIC2775-29YM5 Supervisor
 # Reset output will remain active for 280ms (maximum)
 #
-adapter_nsrst_delay 300
+adapter srst delay 300
 jtag_ntrst_delay 300
 
 
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable
-adapter_khz 16000
+adapter speed 16000
 
 
 # Target events
diff --git a/tcl/board/fsl_imx6q_sabresd.cfg b/tcl/board/fsl_imx6q_sabresd.cfg
index e1f0892..cf34cd1 100644
--- a/tcl/board/fsl_imx6q_sabresd.cfg
+++ b/tcl/board/fsl_imx6q_sabresd.cfg
@@ -13,7 +13,7 @@ transport select jtag
 
 # iMX6Q POR gates JTAG and the chip is completely incommunicado
 # over JTAG for at least 10ms after nSRST is deasserted
-adapter_nsrst_delay 11
+adapter srst delay 11
 
 # Source generic iMX6Q target configuration
 set CHIPNAME imx6q
@@ -144,4 +144,4 @@ $_TARGETNAME.0 configure -event reset-assert { }
 # hook the init function into the reset-init event
 $_TARGETNAME.0 configure -event reset-init { imx6q_sabresd_init }
 # set a slow default JTAG clock, can be overridden later
-adapter_khz 1000
+adapter speed 1000
diff --git a/tcl/board/glyn_tonga2.cfg b/tcl/board/glyn_tonga2.cfg
index 17ed3cf..f48702c 100644
--- a/tcl/board/glyn_tonga2.cfg
+++ b/tcl/board/glyn_tonga2.cfg
@@ -19,12 +19,12 @@ source [find target/tmpa900.cfg]
 # Initial JTAG speed should not exceed 1/6 of the initial CPU clock
 # frequency (24MHz). Be conservative and use 1/8 of the frequency.
 # (24MHz / 8 = 3MHz)
-adapter_khz 3000
+adapter speed 3000
 
 $_TARGETNAME configure -event reset-start {
 	# Upon reset, set the JTAG frequency to 3MHz again, see above.
 	echo "Setting JTAG speed to 3MHz until clocks are initialized."
-	adapter_khz 3000
+	adapter speed 3000
 
 	# Halt the CPU.
 	halt
@@ -41,7 +41,7 @@ $_TARGETNAME configure -event reset-init {
 	# Tests showed that 15MHz works OK, higher speeds can cause problems,
 	# though. Not sure if this is a CPU issue or JTAG adapter issue.
 	echo "Increasing JTAG speed to 15MHz."
-	adapter_khz 15000
+	adapter speed 15000
 
 	# Enable faster memory access.
 	arm7_9 fast_memory_access enable
@@ -197,4 +197,3 @@ proc tonga2_init { } {
 #######################
 
 # TODO: Implement NAND support.
-
diff --git a/tcl/board/gumstix-aerocore.cfg b/tcl/board/gumstix-aerocore.cfg
index ba217c0..f0103ed 100644
--- a/tcl/board/gumstix-aerocore.cfg
+++ b/tcl/board/gumstix-aerocore.cfg
@@ -1,6 +1,6 @@
 # JTAG for the STM32F4x chip used on the Gumstix AeroCore is available on
 # the first interface of a Quad FTDI chip.  nTRST is bit 4.
-interface ftdi
+adapter driver ftdi
 ftdi_vid_pid 0x0403 0x6011
 
 ftdi_layout_init 0x0000 0x001b
diff --git a/tcl/board/hilscher_nxdb500sys.cfg b/tcl/board/hilscher_nxdb500sys.cfg
index 77073e7..20fa3ea 100644
--- a/tcl/board/hilscher_nxdb500sys.cfg
+++ b/tcl/board/hilscher_nxdb500sys.cfg
@@ -5,7 +5,7 @@
 source [find target/hilscher_netx500.cfg]
 
 reset_config trst_and_srst
-adapter_nsrst_delay 500
+adapter srst delay 500
 jtag_ntrst_delay 500
 
 $_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
@@ -17,7 +17,7 @@ $_TARGETNAME configure -event reset-init {
   arm7_9 dcc_downloads enable
 
   sdram_fix
-  
+
   puts "Configuring SDRAM controller for paired K4S561632C (64MB) "
   mww 0x00100140 0
   mww 0x00100144 0x03C13261
diff --git a/tcl/board/hilscher_nxeb500hmi.cfg b/tcl/board/hilscher_nxeb500hmi.cfg
index 6439156..a51fa03 100644
--- a/tcl/board/hilscher_nxeb500hmi.cfg
+++ b/tcl/board/hilscher_nxeb500hmi.cfg
@@ -5,7 +5,7 @@
 source [find target/hilscher_netx500.cfg]
 
 reset_config trst_and_srst
-adapter_nsrst_delay 500
+adapter srst delay 500
 jtag_ntrst_delay 500
 
 $_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
@@ -17,7 +17,7 @@ $_TARGETNAME configure -event reset-init {
   arm7_9 dcc_downloads disable
 
   sdram_fix
-  
+
   puts "Configuring SDRAM controller for MT48LC8M32 (32MB) "
   mww 0x00100140 0
   mww 0x00100144 0x03C23251
diff --git a/tcl/board/hilscher_nxhx10.cfg b/tcl/board/hilscher_nxhx10.cfg
index 4ef2f3b..add424d 100644
--- a/tcl/board/hilscher_nxhx10.cfg
+++ b/tcl/board/hilscher_nxhx10.cfg
@@ -9,7 +9,7 @@ source [find target/hilscher_netx10.cfg]
 # problems try to line below
 # reset_config trst_and_srst srst_pulls_trst
 reset_config trst_and_srst
-adapter_nsrst_delay 500
+adapter srst delay 500
 jtag_ntrst_delay 500
 
 $_TARGETNAME configure -work-area-virt 0x08000000 -work-area-phys 0x08000000 -work-area-size 0x4000 -work-area-backup 1
@@ -79,4 +79,4 @@ $_TARGETNAME configure -event reset-init {
 #flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME
 
 init
-reset init
-\ No newline at end of file
+reset init
diff --git a/tcl/board/hilscher_nxhx50.cfg b/tcl/board/hilscher_nxhx50.cfg
index eebb165..0867f2e 100644
--- a/tcl/board/hilscher_nxhx50.cfg
+++ b/tcl/board/hilscher_nxhx50.cfg
@@ -5,7 +5,7 @@
 source [find target/hilscher_netx50.cfg]
 
 reset_config trst_and_srst
-adapter_nsrst_delay 500
+adapter srst delay 500
 jtag_ntrst_delay 500
 
 $_TARGETNAME configure -work-area-virt 0x10000000 -work-area-phys 0x10000000 -work-area-size 0x4000 -work-area-backup 1
diff --git a/tcl/board/hilscher_nxhx500.cfg b/tcl/board/hilscher_nxhx500.cfg
index dd3a951..2ba030e 100644
--- a/tcl/board/hilscher_nxhx500.cfg
+++ b/tcl/board/hilscher_nxhx500.cfg
@@ -5,7 +5,7 @@
 source [find target/hilscher_netx500.cfg]
 
 reset_config trst_and_srst
-adapter_nsrst_delay 500
+adapter srst delay 500
 jtag_ntrst_delay 500
 
 $_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
diff --git a/tcl/board/hilscher_nxsb100.cfg b/tcl/board/hilscher_nxsb100.cfg
index efb091b..c332bee 100644
--- a/tcl/board/hilscher_nxsb100.cfg
+++ b/tcl/board/hilscher_nxsb100.cfg
@@ -5,7 +5,7 @@
 source [find target/hilscher_netx500.cfg]
 
 reset_config trst_and_srst
-adapter_nsrst_delay 500
+adapter srst delay 500
 jtag_ntrst_delay 500
 
 $_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
@@ -17,7 +17,7 @@ $_TARGETNAME configure -event reset-init {
   arm7_9 dcc_downloads enable
 
   sdram_fix
-  
+
   puts "Configuring SDRAM controller for MT48LC2M32 (8MB) "
   mww 0x00100140 0
   mww 0x00100144 0x03C23251
diff --git a/tcl/board/hitex_lpc1768stick.cfg b/tcl/board/hitex_lpc1768stick.cfg
index 161e965..ac176ca 100644
--- a/tcl/board/hitex_lpc1768stick.cfg
+++ b/tcl/board/hitex_lpc1768stick.cfg
@@ -11,5 +11,4 @@ source [find target/lpc17xx.cfg]
 
 
 # startup @ 500kHz
-adapter_khz 500
-
+adapter speed 500
diff --git a/tcl/board/hitex_lpc2929.cfg b/tcl/board/hitex_lpc2929.cfg
index d251537..2fe1f3c 100644
--- a/tcl/board/hitex_lpc2929.cfg
+++ b/tcl/board/hitex_lpc2929.cfg
@@ -2,12 +2,12 @@
 # http://www.hitex.com/
 
 # Delays on reset lines
-adapter_nsrst_delay 50
+adapter srst delay 50
 jtag_ntrst_delay 1
 
 # Maximum of 1/8 of clock frequency (XTAL = 16 MHz).
 # Adaptive clocking through RTCK is not supported.
-adapter_khz 2000
+adapter speed 2000
 
 # Target device: LPC29xx with ETB
 # The following variables are used by the LPC2900 script:
@@ -24,7 +24,7 @@ $_TARGETNAME configure -work-area-phys 0x58000000 -work-area-size 0x10000 -work-
 # Event handlers
 $_TARGETNAME configure -event reset-start {
   # Back to the slow JTAG clock
-  adapter_khz 2000
+  adapter speed 2000
 }
 
 # External 16-bit flash at chip select CS7 (SST39VF3201-70, 4 MiB)
@@ -46,7 +46,7 @@ $_TARGETNAME configure -event reset-init {
   mww 0xFFFF8070 0x02000000     ;# SYS_CLK_CONF: PLL
 
   # Increase JTAG speed
-  adapter_khz 6000
+  adapter speed 6000
 
   # Enable external memory bus (16-bit SRAM at CS6, 16-bit flash at CS7)
   mww 0xE0001138 0x0000001F     ;# P1.14 = D0
@@ -103,4 +103,3 @@ $_TARGETNAME configure -event reset-init {
   mww 0x600000CC 0x0000000C     ;# Bank7 WST2=8
   mww 0x600000C4 0x00000002     ;# Bank7 IDCY=2
 }
-
diff --git a/tcl/board/hitex_stm32-performancestick.cfg b/tcl/board/hitex_stm32-performancestick.cfg
index 82fb169..74dc583 100644
--- a/tcl/board/hitex_stm32-performancestick.cfg
+++ b/tcl/board/hitex_stm32-performancestick.cfg
@@ -12,5 +12,4 @@ source [find target/stm32f1x.cfg]
 jtag newtap str750 cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id 0x4f1f0041
 
 # for some reason this board like to startup @ 500kHz
-adapter_khz 500
-
+adapter speed 500
diff --git a/tcl/board/hitex_str9-comstick.cfg b/tcl/board/hitex_str9-comstick.cfg
index be15331..3b92252 100644
--- a/tcl/board/hitex_str9-comstick.cfg
+++ b/tcl/board/hitex_str9-comstick.cfg
@@ -5,9 +5,9 @@
 source [find interface/ftdi/hitex_str9-comstick.cfg]
 
 # set jtag speed
-adapter_khz 3000
+adapter speed 3000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 #use combined on interfaces or targets that can't set TRST/SRST separately
 reset_config trst_and_srst
diff --git a/tcl/board/iar_lpc1768.cfg b/tcl/board/iar_lpc1768.cfg
index d8c8c2d..38ffc35 100644
--- a/tcl/board/iar_lpc1768.cfg
+++ b/tcl/board/iar_lpc1768.cfg
@@ -14,4 +14,3 @@ $_TARGETNAME configure -event reset-init {
 
 	flash probe 0
 }
-
diff --git a/tcl/board/iar_str912_sk.cfg b/tcl/board/iar_str912_sk.cfg
index ba060a0..54f517b 100644
--- a/tcl/board/iar_str912_sk.cfg
+++ b/tcl/board/iar_str912_sk.cfg
@@ -1,3 +1,3 @@
 # The IAR str912-sk evaluation kick start board has an str912
 
-source [find target/str912.cfg]
-\ No newline at end of file
+source [find target/str912.cfg]
diff --git a/tcl/board/icnova_imx53_sodimm.cfg b/tcl/board/icnova_imx53_sodimm.cfg
index aa6a148..dce9c47 100644
--- a/tcl/board/icnova_imx53_sodimm.cfg
+++ b/tcl/board/icnova_imx53_sodimm.cfg
@@ -15,14 +15,14 @@ echo "i.MX53 SO-Dimm board lodaded."
 # Set reset type
 #reset_config srst_only
 
-adapter_khz 3000
+adapter speed 3000
 
 # Slow speed to be sure it will work
 jtag_rclk 1000
 $_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
 
 $_TARGETNAME configure -event "reset-assert" {
-	echo "Reseting ...."
+	echo "Resetting ...."
 	#cortex_a dbginit
 }
 
@@ -58,7 +58,7 @@ proc sodimm_init { } {
 	arm core_state arm
 
 	jtag_rclk 3000
-#	adapter_khz 3000
+#	adapter speed 3000
 }
 
 
diff --git a/tcl/board/icnova_sam9g45_sodimm.cfg b/tcl/board/icnova_sam9g45_sodimm.cfg
index 84dab38..30dc347 100644
--- a/tcl/board/icnova_sam9g45_sodimm.cfg
+++ b/tcl/board/icnova_sam9g45_sodimm.cfg
@@ -15,7 +15,7 @@ source [find target/at91sam9g45.cfg]
 # Set reset type.
 # reset_config trst_and_srst
 
-# adapter_nsrst_delay 200
+# adapter srst delay 200
 # jtag_ntrst_delay 200
 
 
@@ -58,7 +58,7 @@ proc at91sam9g45_start { } {
 
 	arm7_9 fast_memory_access disable
     # Slow-speed oscillator enabled at reset, so run jtag speed slow.
-	adapter_khz 4
+	adapter speed 4
     # Make sure processor is halted, or error will result in following steps.
 	halt
 	wait_halt 10000
@@ -117,7 +117,7 @@ proc at91sam9g45_init { } {
 
 	# Switch over to adaptive clocking.
 
-	adapter_khz 6000
+	adapter speed 6000
 
 	# Enable faster DCC downloads.
 
@@ -274,5 +274,3 @@ proc at91sam9g45_init { } {
 
 	arm7_9 fast_memory_access enable
 }
-
-
diff --git a/tcl/board/imx27lnst.cfg b/tcl/board/imx27lnst.cfg
index e0ed057..ac5a9f3 100644
--- a/tcl/board/imx27lnst.cfg
+++ b/tcl/board/imx27lnst.cfg
@@ -8,7 +8,7 @@ proc imx27lnst_init { } {
 	# This setup puts RAM at 0xA0000000
 
 	# reset the board correctly
-	adapter_khz 500
+	adapter speed 500
 	reset run
 	reset halt
 
diff --git a/tcl/board/imx31pdk.cfg b/tcl/board/imx31pdk.cfg
index 502d407..2dce157 100644
--- a/tcl/board/imx31pdk.cfg
+++ b/tcl/board/imx31pdk.cfg
@@ -28,36 +28,36 @@ proc imx31pdk_init { } {
 
 	mww 0x53FC0000 0x040
 	mww 0x53F80000 0x074B0B7D
-	
+
 	# 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
 	#mww 0x53F80004 0xFF871D50
 	#mww 0x53F80010 0x00271C1B
-	
+
 	# Start 16 bit NorFlash Initialization on CS0
 	mww 0xb8002000 0x0000CC03
 	mww 0xb8002004 0xa0330D01
 	mww 0xb8002008 0x00220800
-	
+
 	# Configure CPLD on CS4
 	mww 0xb8002040 0x0000DCF6
 	mww 0xb8002044 0x444A4541
 	mww 0xb8002048 0x44443302
-	
+
 	# SDCLK
 	mww 0x43FAC26C 0
-	
+
 	# CAS
 	mww 0x43FAC270 0
-	
+
 	# RAS
 	mww 0x43FAC274 0
-	
+
 	# CS2 (CSD0)
 	mww 0x43FAC27C 0x1000
-	
+
 	# DQM3
 	mww 0x43FAC284 0
-	
+
 	# DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
 	mww 0x43FAC288 0
 	mww 0x43FAC28C 0
@@ -81,7 +81,7 @@ proc imx31pdk_init { } {
 	mww 0x43FAC2D4 0
 	mww 0x43FAC2D8 0
 	mww 0x43FAC2DC 0
-	
+
 	# Initialization script for 32 bit DDR on MX31 ADS
 	mww 0xB8001010 0x00000004
 	mww 0xB8001004 0x006ac73a
diff --git a/tcl/board/imx35pdk.cfg b/tcl/board/imx35pdk.cfg
index b5aa752..2a7efab 100644
--- a/tcl/board/imx35pdk.cfg
+++ b/tcl/board/imx35pdk.cfg
@@ -8,9 +8,9 @@ $_TARGETNAME configure -event reset-init { imx35pdk_init }
 jtag_rclk 10
 
 proc imx35pdk_init { } {
-	
+
 	imx3x_reset
-	
+
 	mww 0x43f00040 0x00000000
 	mww 0x43f00044 0x00000000
 	mww 0x43f00048 0x00000000
@@ -25,11 +25,11 @@ proc imx35pdk_init { } {
 	mww 0x53f00050 0x00000000
 	mww 0x53f00000 0x77777777
 	mww 0x53f00004 0x77777777
-	
+
 	# clock setup
 	mww 0x53F80004 0x00821000 ;# first need to set IPU_HND_BYP
 	mww 0x53F80004 0x00821000 ;#arm clock is 399Mhz and ahb clock is 133Mhz.
-	
+
 	#=================================================
 	# WEIM config
 	#=================================================
@@ -45,14 +45,14 @@ proc imx35pdk_init { } {
 	mww 0xB8002054 0x444a4541
 	# CS5A
 	mww 0xB8002058 0x44443302
-	
+
 	# IO SW PAD Control registers - setting of 0x0002 is high drive, mDDR
 	mww 0x43FAC368 0x00000006
 	mww 0x43FAC36C 0x00000006
 	mww 0x43FAC370 0x00000006
 	mww 0x43FAC374 0x00000006
 	mww 0x43FAC378 0x00000006
-	mww 0x43FAC37C 0x00000006	
+	mww 0x43FAC37C 0x00000006
 	mww 0x43FAC380 0x00000006
 	mww 0x43FAC384 0x00000006
 	mww 0x43FAC388 0x00000006
@@ -76,7 +76,7 @@ proc imx35pdk_init { } {
 	mww 0x43FAC3D0 0x00000006
 	mww 0x43FAC3D4 0x00000006
 	mww 0x43FAC3D8 0x00000006
-	
+
 	# DDR data bus SD 0 through 31
 	mww 0x43FAC3DC 0x00000082
 	mww 0x43FAC3E0 0x00000082
@@ -110,13 +110,13 @@ proc imx35pdk_init { } {
 	mww 0x43FAC450 0x00000082
 	mww 0x43FAC454 0x00000082
 	mww 0x43FAC458 0x00000082
-	
+
 	# DQM setup
 	mww 0x43FAC45c 0x00000082
 	mww 0x43FAC460 0x00000082
 	mww 0x43FAC464 0x00000082
 	mww 0x43FAC468 0x00000082
-	
+
 	mww 0x43FAC46c 0x00000006
 	mww 0x43FAC470 0x00000006
 	mww 0x43FAC474 0x00000006
@@ -130,30 +130,30 @@ proc imx35pdk_init { } {
 	mww 0x43FAC494 0x00000006
 	mww 0x43FAC498 0x00000006
 	mww 0x43FAC49c 0x00000006
-	mww 0x43FAC4A0 0x00000006	
+	mww 0x43FAC4A0 0x00000006
 	mww 0x43FAC4A4 0x00000006	;# RAS
 	mww 0x43FAC4A8 0x00000006	;# CAS
 	mww 0x43FAC4Ac 0x00000006	;# SDWE
 	mww 0x43FAC4B0 0x00000006 	;# SDCKE0
 	mww 0x43FAC4B4 0x00000006  ;# SDCKE1
 	mww 0x43FAC4B8 0x00000002  ;# SDCLK
-	
+
 	# SDQS0 through SDQS3
 	mww 0x43FAC4Bc 0x00000082
 	mww 0x43FAC4C0 0x00000082
 	mww 0x43FAC4C4 0x00000082
 	mww 0x43FAC4C8 0x00000082
-	
-	
+
+
 	# *==================================================
 	#  Initialization script for 32 bit DDR2 on RINGO 3DS
 	# *==================================================
-	
+
 	#--------------------------------------------
 	# Init CCM
 	#--------------------------------------------
 	mww 0x53F80028 0x7D000028
-	
+
 	#--------------------------------------------
 	# Init IOMUX for JTAG
 	#--------------------------------------------
@@ -164,24 +164,24 @@ proc imx35pdk_init { } {
 	mww 0x43FAC5FC 0x000000F3
 	mww 0x43FAC600 0x000000F3
 	mww 0x43FAC604 0x000000F3
-	
-	
+
+
 	# ESD_MISC : enable DDR2
 	mww 0xB8001010 0x00000304
-	
+
 	#--------------------------------------------
-	# Init 32-bit DDR2 memeory on CSD0
+	# Init 32-bit DDR2 memory on CSD0
 	# COL=10-bit, ROW=13-bit, BA[1:0]=Addr[26:25]
 	#--------------------------------------------
-	
-	# ESD_ESDCFG0 : set timing paramters
-	mww 0xB8001004 0x007ffC2f	
-	
+
+	# ESD_ESDCFG0 : set timing parameters
+	mww 0xB8001004 0x007ffC2f
+
 	# ESD_ESDCTL0 : select Prechare-All mode
 	mww 0xB8001000 0x92220000
 	# DDR2 : Prechare-All
 	mww 0x80000400 0x12345678
-	
+
 	# ESD_ESDCTL0 : select Load-Mode-Register mode
 	mww 0xB8001000 0xB2220000
 	# DDR2 : Load reg EMR2
@@ -192,18 +192,18 @@ proc imx35pdk_init { } {
 	mwb 0x82000400 0xda
 	# DDR2 : Load reg MR -- reset DLL
 	mwb 0x80000333 0xda
-	
+
 	# ESD_ESDCTL0 : select Prechare-All mode
 	mww 0xB8001000 0x92220000
 	# DDR2 : Prechare-All
 	mwb 0x80000400 0x12345678
-	
+
 	# ESD_ESDCTL0 : select Manual-Refresh mode
 	mww 0xB8001000 0xA2220000
 	# DDR2 : Manual-Refresh 2 times
 	mww 0x80000000 0x87654321
 	mww 0x80000000 0x87654321
-	
+
 	# ESD_ESDCTL0 : select Load-Mode-Register mode
 	mww 0xB8001000 0xB2220000
 	# DDR2 : Load reg MR -- CL=3, BL=8, end DLL reset
@@ -212,19 +212,19 @@ proc imx35pdk_init { } {
 	mwb 0x82000780 0xda
 	# DDR2 : Load reg EMR1 -- OCD exit
 	mwb 0x82000400 0xda	;# ODT disabled
-	
+
 	# ESD_ESDCTL0 : select normal-operation mode
 	# DSIZ=32-bit, BL=8, COL=10-bit, ROW=13-bit
 	# disable PWT & PRCT
 	# disable Auto-Refresh
 	mww 0xB8001000 0x82220080
-	
+
 	## ESD_ESDCTL0 : enable Auto-Refresh
 	mww 0xB8001000 0x82228080
 	## ESD_ESDCTL1 : enable Auto-Refresh
 	mww 0xB8001008 0x00002000
-	
-	
+
+
 	#***********************************************
 	# Adjust the ESDCDLY5 register
 	#***********************************************
@@ -233,20 +233,20 @@ proc imx35pdk_init { } {
 	mww 0xB8001024 0x00F48000	;# this is the default value
 	mww 0xB8001028 0x00F48000	;# this is the default value
 	mww 0xB800102c 0x00F48000	;# this is the default value
-	
-	
+
+
 	#Then you can make force measure with the dedicated bit (Bit 7 at ESDMISC)
 	mww 0xB8001010 0x00000384
 	# wait a while
 	sleep 1000
 	# now clear the force measurement bit
 	mww 0xB8001010 0x00000304
-	
+
 	# dummy write to DDR memory to set DQS low
 	mww 0x80000000 0x00000000
-	
+
 	mww 0x30000100 0x0
 	mww 0x30000104 0x31024
-	
-	
+
+
 }
diff --git a/tcl/board/imx53-m53evk.cfg b/tcl/board/imx53-m53evk.cfg
index eada27a..baeb3cd 100644
--- a/tcl/board/imx53-m53evk.cfg
+++ b/tcl/board/imx53-m53evk.cfg
@@ -18,10 +18,10 @@ echo "iMX53 M53EVK board lodaded."
 reset_config trst_and_srst separate trst_open_drain srst_open_drain
 
 # Run at 6 MHz
-adapter_khz 6000
+adapter speed 6000
 
 $_TARGETNAME configure -event "reset-assert" {
-	echo "Reseting ...."
+	echo "Resetting ...."
 	#cortex_a dbginit
 }
 
diff --git a/tcl/board/imx53loco.cfg b/tcl/board/imx53loco.cfg
index 06c3993..18caca5 100644
--- a/tcl/board/imx53loco.cfg
+++ b/tcl/board/imx53loco.cfg
@@ -13,7 +13,7 @@ echo "iMX53 Loco board lodaded."
 # Set reset type
 #reset_config srst_only
 
-adapter_khz 3000
+adapter speed 3000
 
 # Slow speed to be sure it will work
 jtag_rclk 1000
@@ -23,7 +23,7 @@ $_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
 #jtag_ntrst_delay 200
 
 $_TARGETNAME configure -event "reset-assert" {
-	echo "Reseting ...."
+	echo "Resetting ...."
 	#cortex_a dbginit
 }
 
@@ -59,7 +59,7 @@ proc loco_init { } {
 	arm core_state arm
 
 	jtag_rclk 3000
-#	adapter_khz 3000
+#	adapter speed 3000
 }
 
 
diff --git a/tcl/board/imx8mp-evk.cfg b/tcl/board/imx8mp-evk.cfg
new file mode 100644
index 0000000..97a303a
--- /dev/null
+++ b/tcl/board/imx8mp-evk.cfg
@@ -0,0 +1,15 @@
+#
+# configuration file for NXP MC-IMX8MP-EVK
+#
+# Board includes FTDI-based JTAG adapter: interface/ftdi/imx8mp-evk.cfg
+#
+
+transport select jtag
+adapter speed 1000
+reset_config srst_only
+adapter srst delay 100
+
+set CHIPNAME imx8mp
+set CHIPCORES 4
+
+source [find target/imx8m.cfg]
diff --git a/tcl/board/insignal_arndale.cfg b/tcl/board/insignal_arndale.cfg
index 25c123e..09a7223 100644
--- a/tcl/board/insignal_arndale.cfg
+++ b/tcl/board/insignal_arndale.cfg
@@ -5,4 +5,4 @@
 source [find target/exynos5250.cfg]
 
 # Experimentally determined highest working speed
-adapter_khz 200
+adapter speed 200
diff --git a/tcl/board/kasli.cfg b/tcl/board/kasli.cfg
index 2c5e268..06cc1e6 100644
--- a/tcl/board/kasli.cfg
+++ b/tcl/board/kasli.cfg
@@ -1,4 +1,4 @@
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Quad RS232-HS"
 ftdi_vid_pid 0x0403 0x6011
 ftdi_channel 0
@@ -7,7 +7,7 @@ ftdi_layout_init 0x0008 0x000b
 
 reset_config none
 transport select jtag
-adapter_khz 25000
+adapter speed 25000
 
 source [find cpld/xilinx-xc7.cfg]
 source [find cpld/jtagspi.cfg]
diff --git a/tcl/board/kc100.cfg b/tcl/board/kc100.cfg
new file mode 100644
index 0000000..1d383be
--- /dev/null
+++ b/tcl/board/kc100.cfg
@@ -0,0 +1,31 @@
+# Knovative KC-100 cable modem
+
+# TNETC4401PYP, 208-QFP U3
+source [find target/tnetc4401.cfg]
+
+# 14-pin EJTAG on JP1. Standard pinout, 1-3-5-7-9-11 = nTRST-TDI-TDO-TMS-TCK-nSRST. Use 2 for GND.
+# Was initially disabled in hardware; had to add a solder bridge reenabling R124, R125 on back.
+reset_config trst_and_srst separate
+
+# 16Mb Intel CFI flash. Note this CPU has an internal ROM at 0x1FC0000 (phys) for cold boot.
+# All that really does is some minimal checks before jumping to external flash at 0x00000000 phys.
+# That is remapped to 0xB0000000 uncached, 0x90000000 cached.
+flash bank intel cfi 0xB0000000 0x200000 2 2 $_TARGETNAME
+
+# Perform this after a clean reboot, halt, and reset init (which should also leave it halted).
+proc kc100_dump_flash {} {
+	echo "Probing 48 TSOP Intel CFI flash chip (2MB)..."
+	flash probe intel
+	echo "Dumping 2MB flash chip to flashdump.bin.
+	flash read_bank 0 flashdump.bin 0 0x200000
+}
+
+#TODO figure out memory init sequence to be able to dump from cached segment instead
+
+# There is also a serial console on JP2, 3-5-6 = TX-RX-GND. 9600/8/N/1.
+
+# Possibly of note, this modem's ancient ethernet port does not support Auto-MDIX.
+
+# This modem in many ways appears to be essentially a clone of the SB5120. See usbjtag.com.
+# The firmware/OS is also susceptible to many of the same procedures in "Hacking the Cable Modem"
+# by DerEngel (Ryan Harris), available from No Starch Press.
diff --git a/tcl/board/kc705.cfg b/tcl/board/kc705.cfg
index e032e9b..51ea14d 100644
--- a/tcl/board/kc705.cfg
+++ b/tcl/board/kc705.cfg
@@ -5,7 +5,7 @@ source [find cpld/xilinx-xc7.cfg]
 source [find cpld/jtagspi.cfg]
 source [find fpga/xilinx-xadc.cfg]
 source [find fpga/xilinx-dna.cfg]
-adapter_khz 25000
+adapter speed 25000
 
 # example command to write bitstream, soft-cpu bios and runtime:
 # openocd -f board/kc705.cfg -c "init;\
diff --git a/tcl/board/kcu105.cfg b/tcl/board/kcu105.cfg
index c8daea6..e2b68ca 100644
--- a/tcl/board/kcu105.cfg
+++ b/tcl/board/kcu105.cfg
@@ -8,4 +8,4 @@ source [find cpld/xilinx-xcu.cfg]
 
 source [find cpld/jtagspi.cfg]
 
-adapter_khz 25000
+adapter speed 25000
diff --git a/tcl/board/keil_mcb1700.cfg b/tcl/board/keil_mcb1700.cfg
index d63d3ed..05f12df 100644
--- a/tcl/board/keil_mcb1700.cfg
+++ b/tcl/board/keil_mcb1700.cfg
@@ -5,4 +5,3 @@
 #
 
 source [find target/lpc17xx.cfg]
-
diff --git a/tcl/board/keil_mcb2140.cfg b/tcl/board/keil_mcb2140.cfg
index db81efa..bb41a2a 100644
--- a/tcl/board/keil_mcb2140.cfg
+++ b/tcl/board/keil_mcb2140.cfg
@@ -5,4 +5,3 @@
 #
 
 source [find target/lpc2148.cfg]
-
diff --git a/tcl/board/kindle2.cfg b/tcl/board/kindle2.cfg
index f32b2a3..a39f15c 100644
--- a/tcl/board/kindle2.cfg
+++ b/tcl/board/kindle2.cfg
@@ -18,7 +18,7 @@ source [find target/imx31.cfg]
 source [find target/imx.cfg]
 
 $_TARGETNAME configure -event reset-init { kindle2_init }
-$_TARGETNAME configure -event reset-start { adapter_khz 1000 }
+$_TARGETNAME configure -event reset-start { adapter speed 1000 }
 
 # 8MiB NOR Flash
 set _FLASHNAME $_CHIPNAME.flash
@@ -36,7 +36,7 @@ jtag_ntrst_delay 30
 # this is broken but enabled by default
 arm11 memwrite burst disable
 
-adapter_khz 1000
+adapter speed 1000
 ftdi_tdo_sample_edge falling
 
 proc kindle2_init {} {
@@ -162,7 +162,7 @@ proc kindle2_sdram_init {} {
 	# LPDDR1 Initialization script
 	mww 0xb8001010 0x00000002
 	mww 0xb8001010 0x00000004
-	# ESDCFG0: set timing paramters
+	# ESDCFG0: set timing parameters
 	mww 0xb8001004 0x007fff7f
 	# ESDCTL0: select Prechare-All mode
 	mww 0xb8001000 0x92100000
diff --git a/tcl/board/linksys_nslu2.cfg b/tcl/board/linksys_nslu2.cfg
index e605fc1..0b0f58b 100644
--- a/tcl/board/linksys_nslu2.cfg
+++ b/tcl/board/linksys_nslu2.cfg
@@ -5,4 +5,3 @@ source [find target/ixp42x.cfg]
 # The _TARGETNAME is set by the above.
 
 $_TARGETNAME configure -work-area-phys 0x00020000 -work-area-size 0x10000 -work-area-backup 0
-
diff --git a/tcl/board/lubbock.cfg b/tcl/board/lubbock.cfg
index 298954c..d803e6f 100644
--- a/tcl/board/lubbock.cfg
+++ b/tcl/board/lubbock.cfg
@@ -4,7 +4,7 @@
 
 source [find target/pxa255.cfg]
 
-adapter_nsrst_delay 250
+adapter srst delay 250
 jtag_ntrst_delay 250
 
 # NOTE: until after pinmux and such are set up, only CS0 is
diff --git a/tcl/board/marsohod.cfg b/tcl/board/marsohod.cfg
index 681f575..b1393a9 100644
--- a/tcl/board/marsohod.cfg
+++ b/tcl/board/marsohod.cfg
@@ -6,7 +6,7 @@
 
 # Recommended MBFTDI programmer
 source [find interface/ftdi/mbftdi.cfg]
-adapter_khz 2000
+adapter speed 2000
 transport select jtag
 
 # Altera MAXII EPM240T100C CPLD
diff --git a/tcl/board/marsohod2.cfg b/tcl/board/marsohod2.cfg
index d4897c3..31819a2 100644
--- a/tcl/board/marsohod2.cfg
+++ b/tcl/board/marsohod2.cfg
@@ -6,7 +6,7 @@
 
 # Built-in MBFTDI programmer
 source [find interface/ftdi/mbftdi.cfg]
-adapter_khz 2000
+adapter speed 2000
 transport select jtag
 
 # Cyclone III EP3C10E144 FPGA
diff --git a/tcl/board/marsohod3.cfg b/tcl/board/marsohod3.cfg
index bb3c74f..fa00706 100644
--- a/tcl/board/marsohod3.cfg
+++ b/tcl/board/marsohod3.cfg
@@ -6,7 +6,7 @@
 
 # Built-in MBFTDI programmer
 source [find interface/ftdi/mbftdi.cfg]
-adapter_khz 2000
+adapter speed 2000
 transport select jtag
 
 # MAX10 10M50SAE144C8GES FPGA
diff --git a/tcl/board/mcb1700.cfg b/tcl/board/mcb1700.cfg
index 068a19b..01080a0 100644
--- a/tcl/board/mcb1700.cfg
+++ b/tcl/board/mcb1700.cfg
@@ -1,5 +1,5 @@
 # Keil MCB1700 PCB with 1768
-# 
+#
 # Reset init script sets it to 100MHz
 set CCLK 100000
 
@@ -11,7 +11,7 @@ set MCB1700_CCLK $CCLK
 $_TARGETNAME configure -event reset-start {
 	# Start *real slow* as we do not know the
     # state the boot rom left the clock in
-	adapter_khz 10
+	adapter speed 10
 }
 
 # Set up 100MHz clock to CPU
@@ -53,9 +53,9 @@ $_TARGETNAME configure -event reset-init {
 
 	# Dividing CPU clock by 8 should be pretty conservative
 	#
-	# 
+	#
 	global MCB1700_CCLK
-	adapter_khz [expr $MCB1700_CCLK / 8]
+	adapter speed [expr $MCB1700_CCLK / 8]
 
 	# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
 	# "User Flash Mode" where interrupt vectors are _not_ remapped,
diff --git a/tcl/board/microchip_same54_xplained_pro.cfg b/tcl/board/microchip_same54_xplained_pro.cfg
index db8a856..7482de4 100644
--- a/tcl/board/microchip_same54_xplained_pro.cfg
+++ b/tcl/board/microchip_same54_xplained_pro.cfg
@@ -10,4 +10,3 @@ set CHIPNAME same54
 source [find target/atsame5x.cfg]
 
 reset_config srst_only
-
diff --git a/tcl/board/microchip_saml11_xplained_pro.cfg b/tcl/board/microchip_saml11_xplained_pro.cfg
index 3558a8e..2ab6111 100644
--- a/tcl/board/microchip_saml11_xplained_pro.cfg
+++ b/tcl/board/microchip_saml11_xplained_pro.cfg
@@ -4,7 +4,7 @@
 #
 
 source [find interface/cmsis-dap.cfg]
-adapter_khz 1000
+adapter speed 1000
 
 set CHIPNAME saml11
 source [find target/atsaml1x.cfg]
diff --git a/tcl/board/mini2440.cfg b/tcl/board/mini2440.cfg
index 874f829..9dca5a3 100644
--- a/tcl/board/mini2440.cfg
+++ b/tcl/board/mini2440.cfg
@@ -111,7 +111,7 @@ target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
 $_TARGETNAME configure -work-area-phys 0x40000000  -work-area-size 0x4000 -work-area-backup 1
 
 #reset configuration
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 reset_config trst_and_srst
 
@@ -120,7 +120,7 @@ reset_config trst_and_srst
 # IMPORTANT! See README at top of this file.
 #-------------------------------------------------------------------------
 
-    adapter_khz 12000
+    adapter speed 12000
     jtag interface
 
 #-------------------------------------------------------------------------
@@ -140,7 +140,7 @@ reset_config trst_and_srst
 
     nand device s3c2440 0
 
-    adapter_nsrst_delay 100
+    adapter srst delay 100
     jtag_ntrst_delay 100
     reset_config trst_and_srst
     init
diff --git a/tcl/board/mini6410.cfg b/tcl/board/mini6410.cfg
index d00ce1f..2cee939 100644
--- a/tcl/board/mini6410.cfg
+++ b/tcl/board/mini6410.cfg
@@ -88,8 +88,8 @@ proc init_6410_flash {} {
 }
 
 
-adapter_khz 1000
-adapter_nsrst_delay 100
+adapter speed 1000
+adapter srst delay 100
 jtag_ntrst_delay 100
 reset_config trst_and_srst
 
diff --git a/tcl/board/novena-internal-fpga.cfg b/tcl/board/novena-internal-fpga.cfg
index 87495e3..0e9ff5b 100644
--- a/tcl/board/novena-internal-fpga.cfg
+++ b/tcl/board/novena-internal-fpga.cfg
@@ -14,7 +14,7 @@
 # | DISP0_DAT17 | FPGA_TMS     | 5-11 |  139  | TMS     |
 # +-------------+--------------+------+-------+---------+
 
-interface sysfsgpio
+adapter driver sysfsgpio
 
 transport select jtag
 
@@ -22,4 +22,3 @@ transport select jtag
 sysfsgpio_jtag_nums 136 139 137 138
 
 source [find cpld/xilinx-xc6s.cfg]
-
diff --git a/tcl/board/numato_mimas_a7.cfg b/tcl/board/numato_mimas_a7.cfg
index 1261fea..d4012ba 100644
--- a/tcl/board/numato_mimas_a7.cfg
+++ b/tcl/board/numato_mimas_a7.cfg
@@ -7,7 +7,7 @@
 #       Programming while powering via USB may lead to programming failure.
 #       Therefore, prefer external power supply.
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Mimas Artix 7 FPGA Module"
 ftdi_vid_pid 0x2a19 0x1009
 
@@ -30,7 +30,7 @@ ftdi_tdo_sample_edge falling
 #
 ftdi_layout_init 0x0008 0x004b
 reset_config none
-adapter_khz 30000
+adapter speed 30000
 
 source [find cpld/xilinx-xc7.cfg]
 source [find cpld/jtagspi.cfg]
diff --git a/tcl/board/nxp_imx7sabre.cfg b/tcl/board/nxp_imx7sabre.cfg
index 25b7b87..c595e3a 100644
--- a/tcl/board/nxp_imx7sabre.cfg
+++ b/tcl/board/nxp_imx7sabre.cfg
@@ -3,12 +3,12 @@
 transport select jtag
 
 # set a safe speed, can be overridden
-adapter_khz 1000
+adapter speed 1000
 
 # reset configuration has TRST and SRST support
 reset_config trst_and_srst srst_push_pull
 # need at least 100ms delay after SRST release for JTAG
-adapter_nsrst_delay 100
+adapter srst delay 100
 
 # source the target file
 source [find target/imx7.cfg]
diff --git a/tcl/board/nxp_mcimx8m-evk.cfg b/tcl/board/nxp_mcimx8m-evk.cfg
index e2d63ce..dd9bd53 100644
--- a/tcl/board/nxp_mcimx8m-evk.cfg
+++ b/tcl/board/nxp_mcimx8m-evk.cfg
@@ -6,13 +6,13 @@
 transport select jtag
 
 # set a safe JTAG clock speed, can be overridden
-adapter_khz 1000
+adapter speed 1000
 
 # default JTAG configuration has only SRST and no TRST
 reset_config srst_only srst_push_pull
 
 # delay after SRST goes inactive
-adapter_nsrst_delay 70
+adapter srst delay 70
 
 # board has an i.MX8MQ with 4 Cortex-A53 cores
 set CHIPNAME imx8mq
diff --git a/tcl/board/olimex_LPC2378STK.cfg b/tcl/board/olimex_LPC2378STK.cfg
index a4b422d..7e9e58e 100644
--- a/tcl/board/olimex_LPC2378STK.cfg
+++ b/tcl/board/olimex_LPC2378STK.cfg
@@ -8,4 +8,3 @@
 #
 
 source [find target/lpc2378.cfg]
-
diff --git a/tcl/board/olimex_lpc_h2148.cfg b/tcl/board/olimex_lpc_h2148.cfg
index 7833fde..d8fb5be 100644
--- a/tcl/board/olimex_lpc_h2148.cfg
+++ b/tcl/board/olimex_lpc_h2148.cfg
@@ -5,4 +5,3 @@
 #
 
 source [find target/lpc2148.cfg]
-
diff --git a/tcl/board/olimex_sam7_ex256.cfg b/tcl/board/olimex_sam7_ex256.cfg
index 5f83629..426ead6 100644
--- a/tcl/board/olimex_sam7_ex256.cfg
+++ b/tcl/board/olimex_sam7_ex256.cfg
@@ -1,4 +1,3 @@
 # Olimex SAM7-EX256 has a single Atmel at91sam7ex256 on it.
 
 source [find target/sam7x256.cfg]
-
diff --git a/tcl/board/olimex_sam7_la2.cfg b/tcl/board/olimex_sam7_la2.cfg
index 89d2b5a..038fe67 100644
--- a/tcl/board/olimex_sam7_la2.cfg
+++ b/tcl/board/olimex_sam7_la2.cfg
@@ -2,7 +2,7 @@ source [find target/at91sam7a2.cfg]
 
 # delays needed to get stable reads of cpu state
 jtag_ntrst_delay 10
-adapter_nsrst_delay 200
+adapter srst delay 200
 
 # board uses pullup and connects only srst
 reset_config srst_open_drain
@@ -10,9 +10,9 @@ reset_config srst_open_drain
 # srst is connected to NRESET of CPU and fully resets everything...
 reset_config srst_only srst_pulls_trst
 
-adapter_khz 1
+adapter speed 1
 $_TARGETNAME configure -event reset-start {
-	adapter_khz 1
+	adapter speed 1
 }
 
 $_TARGETNAME configure -event reset-init {
@@ -61,7 +61,7 @@ $_TARGETNAME configure -event reset-init {
 	echo "set up pll"
 
 	sleep 100
-	adapter_khz 5000
+	adapter speed 5000
 }
 
 $_TARGETNAME arm7_9 dcc_downloads enable
diff --git a/tcl/board/olimex_sam9_l9260.cfg b/tcl/board/olimex_sam9_l9260.cfg
index ad2f850..72dce87 100644
--- a/tcl/board/olimex_sam9_l9260.cfg
+++ b/tcl/board/olimex_sam9_l9260.cfg
@@ -23,15 +23,15 @@ $_TARGETNAME configure -event reset-start {
 	# RCLK is not supported.
 	jtag_rclk 5
 	halt
-	
-	# RSTC_MR : enable user reset, reset length is 64 slow clock cycles.  MMU may 
+
+	# RSTC_MR : enable user reset, reset length is 64 slow clock cycles.  MMU may
 	# be enabled... use physical address.
 	mww phys 0xfffffd08 0xa5000501
 }
 
 $_TARGETNAME configure -event reset-init {
 	mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
-	
+
 	##
 	# Clock configuration for 99.328 MHz main clock.
 	##
@@ -45,23 +45,23 @@ $_TARGETNAME configure -event reset-init {
 	mww 0xfffffc30 0x00000101 ;# PMC_MCKR : no scale on proc clock, master is proc / 2
 	sleep 10                  ;# wait 10 ms
 	mww 0xfffffc30 0x00000102 ;# PMC_MCKR : switch to PLLA (99.328 MHz)
-	
+
 	# Increase JTAG speed to 6 MHz if RCLK is not supported.
 	jtag_rclk 6000
-	
+
 	arm7_9 dcc_downloads enable ;# Enable faster DCC downloads.
-	
+
 	##
 	# SDRAM configuration for 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks.
 	##
     echo "Configuring SDRAM"
 	mww 0xfffff870 0xffff0000 ;# PIOC_ASR : select peripheral function for D15..D31
 	mww 0xfffff804 0xffff0000 ;# PIOC_PDR : disable PIO function for D15..D31
-	
+
 	mww 0xffffef1c 0x00010002 ;# EBI_CSA : assign EBI CS1 to SDRAM, VDDIOMSEL set for +3V3 memory
-	
+
 	mww 0xffffea08 0x85237259 ;# SDRAMC_CR : configure SDRAM for Samsung chips
-	
+
 	mww 0xffffea00 0x1        ;# SDRAMC_MR : issue NOP command
 	mww 0x20000000 0
 	mww 0xffffea00 0x2        ;# SDRAMC_MR : issue an 'All Banks Precharge' command
@@ -86,7 +86,7 @@ $_TARGETNAME configure -event reset-init {
 	mww 0x20000000 0
 	mww 0xffffea00 0x0        ;# SDRAMC_MR : normal mode
 	mww 0x20000000 0
-	
+
 	mww 0xffffea04 0x2b6      ;# SDRAMC_TR : set refresh timer count to 7 us
 
     ##
@@ -99,37 +99,37 @@ $_TARGETNAME configure -event reset-init {
     mww 0xfffff814 0x00002000 ;# PIOC_ODR : disable output on 13
     mww 0xfffff830 0x00004000 ;# PIOC_SODR : set 14 to disable NAND
     mww 0xfffff864 0x00002000 ;# PIOC_PUER : enable pull-up on 13
-    
+
     mww 0xffffef1c 0x0001000A ;# EBI_CSA : assign EBI CS3 to NAND, same settings as before
-    
+
     mww 0xffffec30 0x00010001 ;# SMC_SETUP3 : 1 clock cycle setup for NRD and NWE
     mww 0xffffec34 0x03030303 ;# SMC_PULSE3 : 3 clock cycle pulse for all signals
     mww 0xffffec38 0x00050005 ;# SMC_CYCLE3 : 5 clock cycle NRD and NWE cycle
-    mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW, 
+    mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
                                #             3 TDF cycles, no optimization
-    
+
     mww 0xffffe800 0x00000001 ;# ECC_CR : reset the ECC parity registers
     mww 0xffffe804 0x00000002 ;# ECC_MR : page size is 2112 words (word is 8 bits)
-    
+
     nand probe at91sam9260.flash
-    
+
     ##
     # Dataflash configuration for 1 x Atmel AT45DB161D, 16Mbit
     ##
     echo "Setting up dataflash"
-    mww 0xfffff404 0x00000807 ;# PIOA_PDR : disable PIO function for 0(SPI0_MISO), 1(SPI0_MOSI), 
+    mww 0xfffff404 0x00000807 ;# PIOA_PDR : disable PIO function for 0(SPI0_MISO), 1(SPI0_MOSI),
                                #            2(SPI0_SPCK), and 11(SPI0_NPCS1)
     mww 0xfffff470 0x00000007 ;# PIOA_ASR : select peripheral A function for 0, 1, and 2
     mww 0xfffff474 0x00000800 ;# PIOA_BSR : select peripheral B function for 11
     mww 0xfffffc10 0x00001000 ;# PMC_PCER : enable SPI0 clock
-    
+
     mww 0xfffc8000 0x00000080 ;# SPI0_CR : software reset SPI0
     mww 0xfffc8000 0x00000080 ;# SPI0_CR : again to be sure
     mww 0xfffc8004 0x000F0011 ;# SPI0_MR : master mode with nothing selected
-    
-    mww 0xfffc8034 0x011a0302 ;# SPI0_CSR1 : capture on leading edge, 8-bits/tx. 33MHz baud, 
+
+    mww 0xfffc8034 0x011a0302 ;# SPI0_CSR1 : capture on leading edge, 8-bits/tx. 33MHz baud,
                                #             250ns delay before SPCK, 250ns b/n tx
-    
+
     mww 0xfffc8004 0x000D0011 ;# SPI0_MR : same config, select NPCS1
     mww 0xfffc8000 0x00000001 ;# SPI0_CR : enable SPI0
 }
diff --git a/tcl/board/openrd.cfg b/tcl/board/openrd.cfg
index db3cb03..fda01d1 100644
--- a/tcl/board/openrd.cfg
+++ b/tcl/board/openrd.cfg
@@ -3,7 +3,7 @@
 source [find interface/ftdi/openrd.cfg]
 source [find target/feroceon.cfg]
 
-adapter_khz 2000
+adapter speed 2000
 
 $_TARGETNAME configure \
 	-work-area-phys 0x10000000 \
@@ -25,10 +25,10 @@ proc openrd_init { } {
 	# possible that initial tap examination failed.  So let's
 	# re-examine the target again here when nSRST is asserted which
 	# should then succeed.
-	jtag_reset 0 1
+	adapter assert srst
 	feroceon.cpu arp_examine
 	halt 0
-	jtag_reset 0 0
+	adapter deassert srst
 	wait_halt
 
 	arm mcr 15 0 0 1 0 0x00052078
@@ -122,4 +122,3 @@ proc openrd_load_uboot { } {
 	resume 0x00600000
 
 }
-
diff --git a/tcl/board/or1k_generic.cfg b/tcl/board/or1k_generic.cfg
index c543ebe..7c19565 100644
--- a/tcl/board/or1k_generic.cfg
+++ b/tcl/board/or1k_generic.cfg
@@ -17,7 +17,7 @@ source [find target/or1k.cfg]
 poll_period 1
 
 # Set the adapter speed
-adapter_khz 3000
+adapter speed 3000
 
 # Enable the target description feature
 gdb_target_description enable
diff --git a/tcl/board/phone_se_j100i.cfg b/tcl/board/phone_se_j100i.cfg
index 6326590..ec61425 100644
--- a/tcl/board/phone_se_j100i.cfg
+++ b/tcl/board/phone_se_j100i.cfg
@@ -1,7 +1,7 @@
 #
 # Sony Ericsson J100I Phone
 #
-# more informations can be found on
+# more information can be found on
 # http://bb.osmocom.org/trac/wiki/SonyEricssonJ100i
 #
 source [find target/ti_calypso.cfg]
diff --git a/tcl/board/phytec_lpc3250.cfg b/tcl/board/phytec_lpc3250.cfg
index 6a7e8e9..cee28cd 100644
--- a/tcl/board/phytec_lpc3250.cfg
+++ b/tcl/board/phytec_lpc3250.cfg
@@ -1,8 +1,8 @@
 source [find target/lpc3250.cfg]
 
-adapter_nsrst_delay 200
+adapter srst delay 200
 jtag_ntrst_delay 1
-adapter_khz 200
+adapter speed 200
 reset_config trst_and_srst separate
 
 arm7_9 dcc_downloads enable
@@ -11,11 +11,11 @@ $_TARGETNAME configure -event gdb-attach { reset init }
 
 $_TARGETNAME configure -event reset-start {
              arm7_9 fast_memory_access disable
-             adapter_khz 200
+             adapter speed 200
 }
 
 $_TARGETNAME configure -event reset-end {
-             adapter_khz 6000
+             adapter speed 6000
              arm7_9 fast_memory_access enable
 }
 
@@ -23,12 +23,12 @@ $_TARGETNAME configure -event reset-init { phytec_lpc3250_init }
 
 # Bare-bones initialization of core clocks and SDRAM
 proc phytec_lpc3250_init { } {
-        # Set clock dividers 
+        # Set clock dividers
         #   ARMCLK = 266.5 MHz
         #   HCLK   = 133.25 MHz
         #   PERIPHCLK = 13.325 MHz
         mww 0x400040BC 0
-        mww 0x40004050 0x140        
+        mww 0x40004050 0x140
         mww 0x40004040 0x4D
         mww 0x40004058 0x16250
 
@@ -37,7 +37,7 @@ proc phytec_lpc3250_init { } {
         sleep 1 busy
         mww 0x40004044 0x106
         sleep 1 busy
-        mww 0x40004044 0x006        
+        mww 0x40004044 0x006
         sleep 1 busy
         mww 0x40004048 0x2
 
@@ -49,7 +49,7 @@ proc phytec_lpc3250_init { } {
         mww 0x31080008 0
         mww 0x40004068 0x1C000
         mww 0x31080028 0x11
-        
+
         mww 0x31080400 0
         mww 0x31080440 0
         mww 0x31080460 0
@@ -66,7 +66,7 @@ proc phytec_lpc3250_init { } {
         mww 0x31080054 1
         mww 0x31080058 1
         mww 0x3108005C 0
-        
+
         mww 0x31080100 0x5680
         mww 0x31080104 0x302
 
diff --git a/tcl/board/pxa255_sst.cfg b/tcl/board/pxa255_sst.cfg
index 49cad5d..2b44a05 100644
--- a/tcl/board/pxa255_sst.cfg
+++ b/tcl/board/pxa255_sst.cfg
@@ -93,7 +93,7 @@ $_TARGETNAME configure -event reset-init {pxa255_sst_init}
 
 reset_config trst_and_srst
 
-adapter_nsrst_delay 200
+adapter srst delay 200
 jtag_ntrst_delay 200
 
 #xscale debug_handler 0  0xFFFF0800      ;# debug handler base address
diff --git a/tcl/board/quark_d2000_refboard.cfg b/tcl/board/quark_d2000_refboard.cfg
index d1388bb..8b8314a 100644
--- a/tcl/board/quark_d2000_refboard.cfg
+++ b/tcl/board/quark_d2000_refboard.cfg
@@ -1,7 +1,7 @@
 # Intel Quark microcontroller D2000 Reference Board (web search for doc num 333582)
 
 # the board has an onboard FTDI FT232H chip
-interface ftdi
+adapter driver ftdi
 ftdi_vid_pid 0x0403 0x6014
 ftdi_channel 0
 
@@ -10,6 +10,6 @@ ftdi_layout_signal nTRST -data 0x0100 -noe 0x0100
 
 source [find target/quark_d20xx.cfg]
 
-adapter_khz 1000
+adapter speed 1000
 
 reset_config trst_only
diff --git a/tcl/board/quark_x10xx_board.cfg b/tcl/board/quark_x10xx_board.cfg
index 8dc600b..4ecf30e 100644
--- a/tcl/board/quark_x10xx_board.cfg
+++ b/tcl/board/quark_x10xx_board.cfg
@@ -4,6 +4,6 @@
 source [find target/quark_x10xx.cfg]
 
 #default frequency but this can be adjusted at runtime
-adapter_khz 4000
+adapter speed 4000
 
 reset_config trst_only
diff --git a/tcl/board/renesas_gen2_common.cfg b/tcl/board/renesas_gen2_common.cfg
deleted file mode 100644
index 00fa777..0000000
--- a/tcl/board/renesas_gen2_common.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-# Renesas R-Car Gen2 Evaluation Board common settings
-
-reset_config trst_and_srst srst_nogate
-
-proc init_reset {mode} {
-    # Assert both resets: equivalent to a power-on reset
-    jtag_reset 1 1
-
-    # Deassert TRST to begin TAP communication
-    jtag_reset 0 1
-
-    # TAP should now be responsive, validate the scan-chain
-    jtag arp_init
-}
diff --git a/tcl/board/renesas_porter.cfg b/tcl/board/renesas_porter.cfg
index c8032f5..7f23fb6 100644
--- a/tcl/board/renesas_porter.cfg
+++ b/tcl/board/renesas_porter.cfg
@@ -1,4 +1,4 @@
 # Renesas R-Car M2 Evaluation Board
 
-source [find target/renesas_r8a7791.cfg]
-source [find board/renesas_gen2_common.cfg]
+set SOC M2
+source [find target/renesas_rcar_gen2.cfg]
diff --git a/tcl/board/renesas_salvator-xs.cfg b/tcl/board/renesas_salvator-xs.cfg
index 1558a52..6d3096e 100644
--- a/tcl/board/renesas_salvator-xs.cfg
+++ b/tcl/board/renesas_salvator-xs.cfg
@@ -7,17 +7,3 @@ if { ![info exists SOC] } {
 	set SOC H3
 }
 source [find target/renesas_rcar_gen3.cfg]
-
-reset_config trst_and_srst srst_nogate
-
-proc init_reset {mode} {
-	# Assert both resets: equivalent to a power-on reset
-	jtag_reset 1 1
-
-	# Deassert TRST to begin TAP communication
-	jtag_reset 0 1
-
-	# TAP should now be responsive, validate the scan-chain
-	jtag arp_init
-}
-
diff --git a/tcl/board/renesas_silk.cfg b/tcl/board/renesas_silk.cfg
index a026537..08bcb66 100644
--- a/tcl/board/renesas_silk.cfg
+++ b/tcl/board/renesas_silk.cfg
@@ -1,4 +1,4 @@
 # Renesas R-Car E2 Evaluation Board
 
-source [find target/renesas_r8a7794.cfg]
-source [find board/renesas_gen2_common.cfg]
+set SOC E2
+source [find target/renesas_rcar_gen2.cfg]
diff --git a/tcl/board/renesas_stout.cfg b/tcl/board/renesas_stout.cfg
index d35f874..51b53e1 100644
--- a/tcl/board/renesas_stout.cfg
+++ b/tcl/board/renesas_stout.cfg
@@ -1,4 +1,4 @@
 # Renesas R-Car H2 Evaluation Board
 
-source [find target/renesas_r8a7790.cfg]
-source [find board/renesas_gen2_common.cfg]
+set SOC H2
+source [find target/renesas_rcar_gen2.cfg]
diff --git a/tcl/board/rigado_bmd300_ek.cfg b/tcl/board/rigado_bmd300_ek.cfg
index 04e5e1f..8e1e65e 100644
--- a/tcl/board/rigado_bmd300_ek.cfg
+++ b/tcl/board/rigado_bmd300_ek.cfg
@@ -6,6 +6,6 @@
 
 source [find interface/jlink.cfg]
 transport select swd
-adapter_khz 1000
+adapter speed 1000
 
 source [find target/nrf52.cfg]
diff --git a/tcl/board/rsc-w910.cfg b/tcl/board/rsc-w910.cfg
index 636a053..574de0c 100644
--- a/tcl/board/rsc-w910.cfg
+++ b/tcl/board/rsc-w910.cfg
@@ -12,8 +12,8 @@ source [find target/nuc910.cfg]
 #
 reset_config trst_and_srst srst_pulls_trst
 
-adapter_khz 1000
-adapter_nsrst_delay 100
+adapter speed 1000
+adapter srst delay 100
 jtag_ntrst_delay 100
 
 $_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x04000000 -work-area-backup 0
@@ -28,12 +28,12 @@ nand device $_NANDNAME nuc910 $_TARGETNAME
 # Target events
 #
 
-$_TARGETNAME configure -event reset-start {adapter_khz 1000}
+$_TARGETNAME configure -event reset-start {adapter speed 1000}
 
 $_TARGETNAME configure -event reset-init {
 	# switch on PLL for 200MHz operation
 	# running from 15MHz input clock
-	
+
 	mww 0xB0000200 0x00000030 ;# CLKEN
 	mww 0xB0000204 0x00000f3c ;# CLKSEL
 	mww 0xB0000208 0x05007000 ;# CLKDIV
@@ -41,17 +41,17 @@ $_TARGETNAME configure -event reset-init {
 	mww 0xB0000210 0x00002b63 ;# PLLCON1
 	mww 0xB000000C 0x08817fa6 ;# MFSEL
 	sleep 10
-	
+
 	# we are now running @ 200MHz
 	# enable all openocd speed tweaks
-	
+
 	arm7_9 dcc_downloads enable
 	arm7_9 fast_memory_access enable
-	adapter_khz 15000
-	
+	adapter speed 15000
+
 	# map nor flash to 0x20000000
 	# map sdram to 0x00000000
-	
+
 	mww 0xb0001000 0x000530c1 ;# EBICON
 	mww 0xb0001004 0x40030084 ;# ROMCON
 	mww 0xb0001008 0x000010ee ;# SDCONF0
diff --git a/tcl/board/sayma_amc.cfg b/tcl/board/sayma_amc.cfg
index 5d338ed..009eb78 100644
--- a/tcl/board/sayma_amc.cfg
+++ b/tcl/board/sayma_amc.cfg
@@ -10,7 +10,7 @@
 # Sayma AMC is usually combined with Sayma RTM (rear transition module)
 # which features an Artix 7 FPGA.
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Quad RS232-HS"
 ftdi_vid_pid 0x0403 0x6011
 ftdi_channel 0
@@ -26,7 +26,7 @@ ftdi_layout_init 0x0098 0x008b
 #ftdi_layout_signal nTRST -data 0x0010
 reset_config none
 
-adapter_khz 5000
+adapter speed 5000
 
 transport select jtag
 
diff --git a/tcl/board/sheevaplug.cfg b/tcl/board/sheevaplug.cfg
index ff333ca..4551637 100644
--- a/tcl/board/sheevaplug.cfg
+++ b/tcl/board/sheevaplug.cfg
@@ -3,7 +3,7 @@
 source [find interface/ftdi/sheevaplug.cfg]
 source [find target/feroceon.cfg]
 
-adapter_khz 2000
+adapter speed 2000
 
 $_TARGETNAME configure \
 	-work-area-phys 0x10000000 \
@@ -25,10 +25,10 @@ proc sheevaplug_init { } {
 	# possible that initial tap examination failed.  So let's
 	# re-examine the target again here when nSRST is asserted which
 	# should then succeed.
-	jtag_reset 0 1
+	adapter assert srst
 	feroceon.cpu arp_examine
 	halt 0
-	jtag_reset 0 0
+	adapter deassert srst
 	wait_halt
 
 	arm mcr 15 0 0 1 0 0x00052078
@@ -133,4 +133,3 @@ proc sheevaplug_load_uboot { } {
 	resume 0x00600000
 
 }
-
diff --git a/tcl/board/sifive-e31arty.cfg b/tcl/board/sifive-e31arty.cfg
index ec10b27..b7a255e 100644
--- a/tcl/board/sifive-e31arty.cfg
+++ b/tcl/board/sifive-e31arty.cfg
@@ -1,7 +1,7 @@
 #
 # Be sure you include the speed and interface before this file
 # Example:
-# -c "adapter_khz 5000" -f "interface/ftdi/olimex-arm-usb-tiny-h.cfg" -f "board/sifive-e31arty.cfg"
+# -c "adapter speed 5000" -f "interface/ftdi/olimex-arm-usb-tiny-h.cfg" -f "board/sifive-e31arty.cfg"
 
 set _CHIPNAME riscv
 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
diff --git a/tcl/board/sifive-e51arty.cfg b/tcl/board/sifive-e51arty.cfg
index ffd83a0..20ad575 100644
--- a/tcl/board/sifive-e51arty.cfg
+++ b/tcl/board/sifive-e51arty.cfg
@@ -1,7 +1,7 @@
 #
 # Be sure you include the speed and interface before this file
 # Example:
-# -c "adapter_khz 5000" -f "interface/ftdi/olimex-arm-usb-tiny-h.cfg" -f "board/sifive-e51arty.cfg"
+# -c "adapter speed 5000" -f "interface/ftdi/olimex-arm-usb-tiny-h.cfg" -f "board/sifive-e51arty.cfg"
 
 set _CHIPNAME riscv
 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
diff --git a/tcl/board/sifive-hifive1-revb.cfg b/tcl/board/sifive-hifive1-revb.cfg
index 662811f..7f2a212 100644
--- a/tcl/board/sifive-hifive1-revb.cfg
+++ b/tcl/board/sifive-hifive1-revb.cfg
@@ -1,6 +1,6 @@
-adapter_khz 4000
+adapter speed 4000
 
-interface jlink
+adapter driver jlink
 transport select jtag
 
 set _CHIPNAME riscv
diff --git a/tcl/board/sifive-hifive1.cfg b/tcl/board/sifive-hifive1.cfg
index 9bc6670..196f540 100644
--- a/tcl/board/sifive-hifive1.cfg
+++ b/tcl/board/sifive-hifive1.cfg
@@ -1,6 +1,6 @@
-adapter_khz     10000
+adapter speed     10000
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Dual RS232-HS"
 ftdi_vid_pid 0x0403 0x6010
 
@@ -10,7 +10,7 @@ ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
 #Reset Stretcher logic on FE310 is ~1 second long
 #This doesn't apply if you use
 # ftdi_set_signal, but still good to document
-#adapter_nsrst_delay 1500
+#adapter srst delay 1500
 
 set _CHIPNAME riscv
 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
diff --git a/tcl/board/snps_em_sk.cfg b/tcl/board/snps_em_sk.cfg
new file mode 100644
index 0000000..3d93407
--- /dev/null
+++ b/tcl/board/snps_em_sk.cfg
@@ -0,0 +1,22 @@
+#  Copyright (C) 2014-2016,2020 Synopsys, Inc.
+#  Anton Kolesov <anton.kolesov@synopsys.com>
+#  Didin Evgeniy <didin@synopsys.com>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Synopsys DesignWare ARC EM Starter Kit v2.x
+#
+
+# Configure JTAG cable
+# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.
+source [find interface/ftdi/digilent-hs1.cfg]
+
+# 5MHz seems to work good with all cores that might happen in 2.x
+adapter speed 5000
+
+# ARCs support only JTAG.
+transport select jtag
+
+# Configure FPGA. This script supports both LX45 and LX150.
+source [find target/snps_em_sk_fpga.cfg]
diff --git a/tcl/board/snps_em_sk_v1.cfg b/tcl/board/snps_em_sk_v1.cfg
new file mode 100644
index 0000000..0c1539e
--- /dev/null
+++ b/tcl/board/snps_em_sk_v1.cfg
@@ -0,0 +1,20 @@
+#  Copyright (C) 2014-2016,2020 Synopsys, Inc.
+#  Anton Kolesov <anton.kolesov@synopsys.com>
+#  Didin Evgeniy <didin@synopsys.com>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Synopsys DesignWare ARC EM Starter Kit v1.0 and v1.1
+#
+
+# Configure JTAG cable
+# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.
+source [find interface/ftdi/digilent-hs1.cfg]
+adapter speed 10000
+
+# ARCs support only JTAG.
+transport select jtag
+
+# Configure FPGA. This script supports both LX45 and LX150.
+source [find target/snps_em_sk_fpga.cfg]
diff --git a/tcl/board/snps_em_sk_v2.1.cfg b/tcl/board/snps_em_sk_v2.1.cfg
new file mode 100644
index 0000000..c1fb232
--- /dev/null
+++ b/tcl/board/snps_em_sk_v2.1.cfg
@@ -0,0 +1,23 @@
+#  Copyright (C) 2014-2016,2020 Synopsys, Inc.
+#  Anton Kolesov <anton.kolesov@synopsys.com>
+#  Didin Evgeniy <didin@synopsys.com>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Synopsys DesignWare ARC EM Starter Kit v2.1
+#
+
+# Configure JTAG cable
+# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.
+source [find interface/ftdi/digilent-hs1.cfg]
+
+# JTAG 10MHz is too fast for EM7D FPU in EM SK 2.1 which has core frequency
+# 20MHz. 7.5 MHz seems to work fine.
+adapter speed 7500
+
+# ARCs support only JTAG.
+transport select jtag
+
+# Configure FPGA. This script supports both LX45 and LX150.
+source [find target/snps_em_sk_fpga.cfg]
diff --git a/tcl/board/snps_em_sk_v2.2.cfg b/tcl/board/snps_em_sk_v2.2.cfg
new file mode 100644
index 0000000..674d9f6
--- /dev/null
+++ b/tcl/board/snps_em_sk_v2.2.cfg
@@ -0,0 +1,22 @@
+#  Copyright (C) 2016,2020 Synopsys, Inc.
+#  Anton Kolesov <anton.kolesov@synopsys.com>
+#  Didin Evgeniy <didin@synopsys.com>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Synopsys DesignWare ARC EM Starter Kit v2.2
+#
+
+# Configure JTAG cable
+# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.
+source [find interface/ftdi/digilent-hs1.cfg]
+
+# EM11D reportedly requires 5 MHz. Other cores and board can work faster.
+adapter speed 5000
+
+# ARCs support only JTAG.
+transport select jtag
+
+# Configure FPGA. This script supports both LX45 and LX150.
+source [find target/snps_em_sk_fpga.cfg]
diff --git a/tcl/board/st_nucleo_8l152r8.cfg b/tcl/board/st_nucleo_8l152r8.cfg
new file mode 100644
index 0000000..d337269
--- /dev/null
+++ b/tcl/board/st_nucleo_8l152r8.cfg
@@ -0,0 +1,10 @@
+# This is a ST NUCLEO 8L152R8 board with a single STM8L152R8T6 chip.
+# http://www.st.com/en/evaluation-tools/nucleo-8l152r8.html
+
+source [find interface/stlink-dap.cfg]
+
+transport select swim
+
+source [find target/stm8l152.cfg]
+
+reset_config srst_only
diff --git a/tcl/board/st_nucleo_h745zi.cfg b/tcl/board/st_nucleo_h745zi.cfg
new file mode 100644
index 0000000..22d36f6
--- /dev/null
+++ b/tcl/board/st_nucleo_h745zi.cfg
@@ -0,0 +1,14 @@
+# This is an ST NUCLEO-H745ZI-Q board with single STM32H745ZITx chip.
+
+source [find interface/stlink-dap.cfg]
+transport select dapdirect_swd
+
+# STM32H745xx devices are dual core (Cortex-M7 and Cortex-M4)
+set DUAL_CORE 1
+
+# enable CTI for cross halting both cores
+set USE_CTI 1
+
+source [find target/stm32h7x_dual_bank.cfg]
+
+reset_config srst_only
diff --git a/tcl/board/st_nucleo_wb55.cfg b/tcl/board/st_nucleo_wb55.cfg
new file mode 100644
index 0000000..5b5b8f7
--- /dev/null
+++ b/tcl/board/st_nucleo_wb55.cfg
@@ -0,0 +1,11 @@
+#
+# Configuration for STM32WB55 Nucleo board (STM32WB55RGV6)
+#
+
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+source [find target/stm32wbx.cfg]
+
+reset_config srst_only
diff --git a/tcl/board/steval-idb011v1.cfg b/tcl/board/steval-idb011v1.cfg
new file mode 100644
index 0000000..5988c63
--- /dev/null
+++ b/tcl/board/steval-idb011v1.cfg
@@ -0,0 +1,3 @@
+# This is an evaluation board with a single BlueNRG-LP chip.
+set CHIPNAME bluenrg-lp
+source [find target/bluenrg-x.cfg]
diff --git a/tcl/board/steval_pcc010.cfg b/tcl/board/steval_pcc010.cfg
index ddfdbb3..94108d1 100644
--- a/tcl/board/steval_pcc010.cfg
+++ b/tcl/board/steval_pcc010.cfg
@@ -1,5 +1,5 @@
 # Use for the STM207VG plug-in board (1 MiB Flash and 112+16 KiB Ram
-# comming with the STEVAL-PCC010 board
+# coming with the STEVAL-PCC010 board
 # http://www.st.com/internet/evalboard/product/251530.jsp
 # or any other board with only a STM32F2x in the JTAG chain
 
diff --git a/tcl/board/stm3210e_eval.cfg b/tcl/board/stm3210e_eval.cfg
index 91807ce..f30253c 100644
--- a/tcl/board/stm3210e_eval.cfg
+++ b/tcl/board/stm3210e_eval.cfg
@@ -17,11 +17,11 @@ flash bank $_FLASHNAME cfi 0x64000000 0x01000000 2 2 $_TARGETNAME
 proc stm32_enable_fsmc {} {
 
 	echo "Enabling FSMC Bank 1 (NOR/PSRAM Bank 2)"
-	
+
 	# enable gpio (defg) clocks for fsmc
 	# RCC_APB2ENR
 	mww 0x40021018 0x000001E0
-	
+
 	# enable fsmc clock
 	# RCC_AHBENR
 	mww 0x40021014 0x00000114
@@ -31,29 +31,29 @@ proc stm32_enable_fsmc {} {
 	mww 0x40011400 0x44BB44BB
 	# GPIOD_CRH
 	mww 0x40011404 0xBBBBBBBB
-	
+
 	# GPIOE_CRL
 	mww 0x40011800 0xBBBBB444
 	# GPIOE_CRH
 	mww 0x40011804 0xBBBBBBBB
-	
+
 	# GPIOF_CRL
 	mww 0x40011C00 0x44BBBBBB
 	# GPIOF_CRH
 	mww 0x40011C04 0xBBBB4444
-	
+
 	# GPIOG_CRL
 	mww 0x40012000 0x44BBBBBB
 	# GPIOG_CRH
 	mww 0x40012004 0x444444B4
-	
+
 	# setup fsmc timings
 	# FSMC_BCR1
 	mww 0xA0000008 0x00001058
-	
+
 	# FSMC_BTR1
 	mww 0xA000000C 0x10000502
-	
+
 	# FSMC_BCR1 - enable fsmc
 	mww 0xA0000008 0x00001059
 }
diff --git a/tcl/board/stm32f7discovery.cfg b/tcl/board/stm32f7discovery.cfg
index 7d1bc96..7d1bc96 100755..100644
--- a/tcl/board/stm32f7discovery.cfg
+++ b/tcl/board/stm32f7discovery.cfg
diff --git a/tcl/board/stm32mp15x_dk2.cfg b/tcl/board/stm32mp15x_dk2.cfg
new file mode 100644
index 0000000..0233c6d
--- /dev/null
+++ b/tcl/board/stm32mp15x_dk2.cfg
@@ -0,0 +1,11 @@
+# board MB1272B
+# http://www.st.com/en/evaluation-tools/stm32mp157a-dk1.html
+# http://www.st.com/en/evaluation-tools/stm32mp157c-dk2.html
+
+source [find interface/stlink-dap.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32mp15x.cfg]
+
+reset_config srst_only
diff --git a/tcl/board/telo.cfg b/tcl/board/telo.cfg
index 1d3afdf..2c98ca3 100644
--- a/tcl/board/telo.cfg
+++ b/tcl/board/telo.cfg
@@ -1,5 +1,5 @@
 source [find target/c100.cfg]
-# basic register defintion for C100
+# basic register definition for C100
 source [find target/c100regs.tcl]
 # board-config info
 source [find target/c100config.tcl]
@@ -10,10 +10,10 @@ source [find target/c100helper.tcl]
 # Telo board & C100 support trst and srst
 # make the reset asserted to
 # allow RC circuit to discharge for: [ms]
-adapter_nsrst_assert_width 100
+adapter srst pulse_width 100
 jtag_ntrst_assert_width 100
 # don't talk to JTAG after reset for: [ms]
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 reset_config trst_and_srst separate
 
@@ -23,11 +23,11 @@ reset_config trst_and_srst separate
 # issue telnet: reset init
 # issue gdb: monitor reset init
 $_TARGETNAME configure -event reset-init {
-	adapter_khz 100
+	adapter speed 100
 	# this will setup Telo board
 	setupTelo
 	#turn up the JTAG speed
-	adapter_khz 3000
+	adapter speed 3000
 	echo "JTAG speek now 3MHz"
 	echo "type helpC100 to get help on C100"
 }
diff --git a/tcl/board/ti_am437x_idk.cfg b/tcl/board/ti_am437x_idk.cfg
index 65e2094..fc2b81b 100644
--- a/tcl/board/ti_am437x_idk.cfg
+++ b/tcl/board/ti_am437x_idk.cfg
@@ -4,7 +4,7 @@
 source [find interface/ftdi/xds100v2.cfg]
 
 transport select jtag
-adapter_khz 30000
+adapter speed 30000
 
 source [find target/am437x.cfg]
 $_TARGETNAME configure -event reset-init { init_platform 0x61a11b32 }
diff --git a/tcl/board/ti_am43xx_evm.cfg b/tcl/board/ti_am43xx_evm.cfg
index d536314..dbc37ae 100644
--- a/tcl/board/ti_am43xx_evm.cfg
+++ b/tcl/board/ti_am43xx_evm.cfg
@@ -1,6 +1,6 @@
 # Works on both AM437x GP EVM and AM438x ePOS EVM
 transport select jtag
-adapter_khz 16000
+adapter speed 16000
 
 source [find target/am437x.cfg]
 
diff --git a/tcl/board/ti_beagleboard_xm.cfg b/tcl/board/ti_beagleboard_xm.cfg
index e4e93e3..683f583 100644
--- a/tcl/board/ti_beagleboard_xm.cfg
+++ b/tcl/board/ti_beagleboard_xm.cfg
@@ -9,4 +9,3 @@ source [find target/amdm37x.cfg]
 reset_config trst_only
 
 # "amdm37x_dbginit dm37x.cpu" needs to be run after init.
-
diff --git a/tcl/board/ti_beaglebone.cfg b/tcl/board/ti_beaglebone.cfg
index a54ad62..7ba8c50 100644
--- a/tcl/board/ti_beaglebone.cfg
+++ b/tcl/board/ti_beaglebone.cfg
@@ -4,10 +4,8 @@
 # The JTAG interface is built directly on the board.
 source [find interface/ftdi/xds100v2.cfg]
 
-adapter_khz 16000
+adapter speed 16000
 
 reset_config trst_and_srst
 
 source [find board/ti_beaglebone-base.cfg]
-
-
diff --git a/tcl/board/ti_beaglebone_black.cfg b/tcl/board/ti_beaglebone_black.cfg
index 79fc1e8..c730814 100644
--- a/tcl/board/ti_beaglebone_black.cfg
+++ b/tcl/board/ti_beaglebone_black.cfg
@@ -1,7 +1,7 @@
 # AM335x Beaglebone Black
 #  http://beagleboard.org/bone
 
-adapter_khz 1000
+adapter speed 1000
 
 reset_config trst_and_srst
 
diff --git a/tcl/board/ti_blaze.cfg b/tcl/board/ti_blaze.cfg
index c9bbe25..4881389 100644
--- a/tcl/board/ti_blaze.cfg
+++ b/tcl/board/ti_blaze.cfg
@@ -3,4 +3,3 @@ jtag_rclk 6000
 source [find target/omap4430.cfg]
 
 reset_config trst_and_srst
-
diff --git a/tcl/board/ti_cc13x0_launchpad.cfg b/tcl/board/ti_cc13x0_launchpad.cfg
index 9e1c1ea..4fbce41 100644
--- a/tcl/board/ti_cc13x0_launchpad.cfg
+++ b/tcl/board/ti_cc13x0_launchpad.cfg
@@ -3,5 +3,5 @@
 #
 source [find interface/xds110.cfg]
 transport select jtag
-adapter_khz 2500
+adapter speed 5500
 source [find target/ti_cc13x0.cfg]
diff --git a/tcl/board/ti_cc13x2_launchpad.cfg b/tcl/board/ti_cc13x2_launchpad.cfg
index 18c5ce5..dc0c182 100644
--- a/tcl/board/ti_cc13x2_launchpad.cfg
+++ b/tcl/board/ti_cc13x2_launchpad.cfg
@@ -2,6 +2,6 @@
 # TI CC13x2 LaunchPad Evaluation Kit
 #
 source [find interface/xds110.cfg]
-adapter_khz 2500
+adapter speed 5500
 transport select jtag
 source [find target/ti_cc13x2.cfg]
diff --git a/tcl/board/ti_cc26x0_launchpad.cfg b/tcl/board/ti_cc26x0_launchpad.cfg
index 3613a47..372e57c 100644
--- a/tcl/board/ti_cc26x0_launchpad.cfg
+++ b/tcl/board/ti_cc26x0_launchpad.cfg
@@ -2,6 +2,6 @@
 # TI CC26x0 LaunchPad Evaluation Kit
 #
 source [find interface/xds110.cfg]
-adapter_khz 2500
+adapter speed 5500
 transport select jtag
 source [find target/ti_cc26x0.cfg]
diff --git a/tcl/board/ti_cc26x2_launchpad.cfg b/tcl/board/ti_cc26x2_launchpad.cfg
index 2f2b34b..c8057ad 100644
--- a/tcl/board/ti_cc26x2_launchpad.cfg
+++ b/tcl/board/ti_cc26x2_launchpad.cfg
@@ -2,6 +2,6 @@
 # TI CC26x2 LaunchPad Evaluation Kit
 #
 source [find interface/xds110.cfg]
-adapter_khz 2500
+adapter speed 5500
 transport select jtag
 source [find target/ti_cc26x2.cfg]
diff --git a/tcl/board/ti_cc3200_launchxl.cfg b/tcl/board/ti_cc3200_launchxl.cfg
index b78b09b..b37b406 100644
--- a/tcl/board/ti_cc3200_launchxl.cfg
+++ b/tcl/board/ti_cc3200_launchxl.cfg
@@ -12,9 +12,10 @@ if { [info exists TRANSPORT] } {
    transport select jtag
 }
 
-adapter_khz 2500
+adapter speed 2500
 
 set WORKAREASIZE 0x40000
 source [find target/ti_cc32xx.cfg]
 
 reset_config srst_only
+adapter srst delay 1100
diff --git a/tcl/board/ti_cc3220sf_launchpad.cfg b/tcl/board/ti_cc3220sf_launchpad.cfg
index a3dac62..7c8310a 100644
--- a/tcl/board/ti_cc3220sf_launchpad.cfg
+++ b/tcl/board/ti_cc3220sf_launchpad.cfg
@@ -2,6 +2,6 @@
 # TI CC3220SF-LaunchXL LaunchPad Evaluation Kit
 #
 source [find interface/xds110.cfg]
-adapter_khz 2500
+adapter speed 8500
 transport select swd
 source [find target/ti_cc3220sf.cfg]
diff --git a/tcl/board/ti_cc32xx_launchpad.cfg b/tcl/board/ti_cc32xx_launchpad.cfg
index f657bdf..d0f2a83 100644
--- a/tcl/board/ti_cc32xx_launchpad.cfg
+++ b/tcl/board/ti_cc32xx_launchpad.cfg
@@ -2,6 +2,9 @@
 # TI CC32xx-LaunchXL LaunchPad Evaluation Kit
 #
 source [find interface/xds110.cfg]
-adapter_khz 2500
+adapter speed 8500
 transport select swd
 source [find target/ti_cc32xx.cfg]
+
+reset_config srst_only
+adapter srst delay 1100
diff --git a/tcl/board/ti_dk-tm4c129.cfg b/tcl/board/ti_dk-tm4c129.cfg
new file mode 100644
index 0000000..f1171af
--- /dev/null
+++ b/tcl/board/ti_dk-tm4c129.cfg
@@ -0,0 +1,14 @@
+#
+# TI Tiva C DK-TM4C129X Connected Development Kit
+#
+# http://www.ti.com/tool/dk-tm4c129x
+#
+
+source [find interface/ti-icdi.cfg]
+
+transport select hla_jtag
+
+set WORKAREASIZE 0x8000
+set CHIPNAME tm4c129xnczad
+
+source [find target/stellaris.cfg]
diff --git a/tcl/board/ti_ek-tm4c123gxl.cfg b/tcl/board/ti_ek-tm4c123gxl.cfg
new file mode 100644
index 0000000..4fc1050
--- /dev/null
+++ b/tcl/board/ti_ek-tm4c123gxl.cfg
@@ -0,0 +1,13 @@
+#
+# TI Tiva C Series ek-tm4c123gxl Launchpad Evaluation Kit
+#
+# http://www.ti.com/tool/ek-tm4c123gxl
+#
+
+source [find interface/ti-icdi.cfg]
+
+transport select hla_jtag
+
+set WORKAREASIZE 0x8000
+set CHIPNAME tm4c123gh6pm
+source [find target/stellaris.cfg]
diff --git a/tcl/board/ti_ek-tm4c1294xl.cfg b/tcl/board/ti_ek-tm4c1294xl.cfg
new file mode 100644
index 0000000..b3f384c
--- /dev/null
+++ b/tcl/board/ti_ek-tm4c1294xl.cfg
@@ -0,0 +1,14 @@
+#
+# TI Tiva C Series ek-tm4c1294xl Launchpad Evaluation Kit
+#
+# http://www.ti.com/tool/ek-tm4c1294xl
+#
+
+source [find interface/ti-icdi.cfg]
+
+transport select hla_jtag
+
+set WORKAREASIZE 0x8000
+set CHIPNAME tm4c1294ncpdt
+
+source [find target/stellaris.cfg]
diff --git a/tcl/board/ti_msp432_launchpad.cfg b/tcl/board/ti_msp432_launchpad.cfg
index bfad322..6d2b15d 100644
--- a/tcl/board/ti_msp432_launchpad.cfg
+++ b/tcl/board/ti_msp432_launchpad.cfg
@@ -2,6 +2,6 @@
 # TI MSP432 LaunchPad Evaluation Kit
 #
 source [find interface/xds110.cfg]
-adapter_khz 2500
+adapter speed 10000
 transport select swd
 source [find target/ti_msp432.cfg]
diff --git a/tcl/board/ti_pandaboard.cfg b/tcl/board/ti_pandaboard.cfg
index bd2cd37..bc92596 100644
--- a/tcl/board/ti_pandaboard.cfg
+++ b/tcl/board/ti_pandaboard.cfg
@@ -3,4 +3,3 @@ jtag_rclk 6000
 source [find target/omap4430.cfg]
 
 reset_config trst_only
-
diff --git a/tcl/board/ti_pandaboard_es.cfg b/tcl/board/ti_pandaboard_es.cfg
index 2abd7e9..756fa33 100644
--- a/tcl/board/ti_pandaboard_es.cfg
+++ b/tcl/board/ti_pandaboard_es.cfg
@@ -3,4 +3,3 @@ jtag_rclk 6000
 source [find target/omap4460.cfg]
 
 reset_config trst_only
-
diff --git a/tcl/board/ti_tmdx570ls31usb.cfg b/tcl/board/ti_tmdx570ls31usb.cfg
index 5502444..6d73502 100644
--- a/tcl/board/ti_tmdx570ls31usb.cfg
+++ b/tcl/board/ti_tmdx570ls31usb.cfg
@@ -1,4 +1,4 @@
-adapter_khz 1500
+adapter speed 1500
 
 source [find interface/ftdi/xds100v2.cfg]
 source [find target/ti_tms570.cfg]
diff --git a/tcl/board/tocoding_poplar.cfg b/tcl/board/tocoding_poplar.cfg
index d8b8330..d0951ce 100644
--- a/tcl/board/tocoding_poplar.cfg
+++ b/tcl/board/tocoding_poplar.cfg
@@ -5,7 +5,7 @@
 # board does not feature anything but JTAG
 transport select jtag
 
-adapter_khz 10000
+adapter speed 10000
 
 # SRST-only reset configuration
 reset_config srst_only srst_push_pull
diff --git a/tcl/board/topas910.cfg b/tcl/board/topas910.cfg
index 90c18c4..9f994c8 100644
--- a/tcl/board/topas910.cfg
+++ b/tcl/board/topas910.cfg
@@ -30,7 +30,7 @@ proc topas910_init { } {
 # Init SDRAM
 #  _PMCDRV          = 0x00000071;
 #  //
-#  // Initialize SDRAM timing paramater
+#  // Initialize SDRAM timing parameter
 #  //
 #  _DMC_CAS_LATENCY = 0x00000006;
 #  _DMC_T_DQSS      = 0x00000000;
@@ -99,7 +99,7 @@ proc topas910_init { } {
 	mww 0xf4300004 0x00000000
 
 	sleep 10
-#	adapter_khz NNNN
+#	adapter speed NNNN
 
 # remap off in case of IROM boot
 	mww 0xf0000004 0x00000001
diff --git a/tcl/board/topasa900.cfg b/tcl/board/topasa900.cfg
index 2a388d5..4fa6383 100644
--- a/tcl/board/topasa900.cfg
+++ b/tcl/board/topasa900.cfg
@@ -37,7 +37,7 @@ proc topasa900_init { } {
 # Init SDRAM
 #  _PMCDRV          = 0x00000071;
 #  //
-#  // Initialize SDRAM timing paramater
+#  // Initialize SDRAM timing parameter
 #  //
 #  _DMC_CAS_LATENCY = 0x00000006;
 #  _DMC_T_DQSS      = 0x00000000;
@@ -105,7 +105,7 @@ proc topasa900_init { } {
 	mww 0xf4300004 0x00000000
 
 	sleep 10
-#	adapter_khz NNNN
+#	adapter speed NNNN
 
 # remap off in case of IROM boot
 	mww 0xf0000004 0x00000001
@@ -123,4 +123,3 @@ arm7_9 dcc_downloads enable       ;# Enable faster DCC downloads
 #flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME cfi 0x20000000 0x1000000 2 2 $_TARGETNAME
-
diff --git a/tcl/board/twr-k60f120m.cfg b/tcl/board/twr-k60f120m.cfg
index e96d045..c4d87db 100644
--- a/tcl/board/twr-k60f120m.cfg
+++ b/tcl/board/twr-k60f120m.cfg
@@ -5,7 +5,7 @@
 source [find target/k60.cfg]
 
 $_TARGETNAME configure -event reset-init {
-	puts "-event reset-init occured"
+	puts "-event reset-init occurred"
 }
 
 #
diff --git a/tcl/board/twr-k60n512.cfg b/tcl/board/twr-k60n512.cfg
index d2312cf..5babeb8 100644
--- a/tcl/board/twr-k60n512.cfg
+++ b/tcl/board/twr-k60n512.cfg
@@ -5,7 +5,7 @@
 source [find target/k60.cfg]
 
 $_TARGETNAME configure -event reset-init {
-	puts "-event reset-init occured"
+	puts "-event reset-init occurred"
 }
 
 #
diff --git a/tcl/board/twr-vf65gs10.cfg b/tcl/board/twr-vf65gs10.cfg
index a80407f..0d6d332 100644
--- a/tcl/board/twr-vf65gs10.cfg
+++ b/tcl/board/twr-vf65gs10.cfg
@@ -198,4 +198,4 @@ proc board_init { } {
 # hook the init function into the reset-init event
 ${_TARGETNAME}0 configure -event reset-init { board_init }
 # set a slow default JTAG clock, can be overridden later
-adapter_khz 1000
+adapter speed 1000
diff --git a/tcl/board/twr-vf65gs10_cmsisdap.cfg b/tcl/board/twr-vf65gs10_cmsisdap.cfg
index e8db754..ab4548f 100644
--- a/tcl/board/twr-vf65gs10_cmsisdap.cfg
+++ b/tcl/board/twr-vf65gs10_cmsisdap.cfg
@@ -12,4 +12,4 @@ transport select swd
 source [find board/twr-vf65gs10.cfg]
 
 # override reset configuration
-reset_config srst_only
-\ No newline at end of file
+reset_config srst_only
diff --git a/tcl/board/unknown_at91sam9260.cfg b/tcl/board/unknown_at91sam9260.cfg
index de49a69..5570ef0 100644
--- a/tcl/board/unknown_at91sam9260.cfg
+++ b/tcl/board/unknown_at91sam9260.cfg
@@ -93,5 +93,3 @@ $_TARGETNAME configure -event reset-init {
 #flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
-
-
diff --git a/tcl/board/uptech_2410.cfg b/tcl/board/uptech_2410.cfg
index 950f2a7..227cf42 100644
--- a/tcl/board/uptech_2410.cfg
+++ b/tcl/board/uptech_2410.cfg
@@ -11,28 +11,28 @@ proc init_pll_sdram { } {
 	#echo "---------- Initializing PLL and SDRAM ---------"
 	#watchdog timer disable
 	mww phys 0x53000000 0x00000000
-	
+
 	#disable all interrupts
 	mww phys 0x4a000008 0xffffffff
-	
+
 	#disable all sub-interrupts
 	mww phys 0x4a00001c 0x000007ff
-	
+
 	#clear all source pending bits
 	mww phys 0x4a000000 0xffffffff
-	
+
 	#clear all sub-source pending bits
 	mww phys 0x4a000018 0x000007ff
-	
+
 	#clear interrupt pending bit
 	mww phys 0x4a000010 0xffffffff
-	
+
 	#PLL locktime counter
 	mww phys 0x4c000000 0x00ffffff
-	
+
 	#Fin=12MHz Fout=202.8MHz
 	#mww phys 0x4c000004 0x000a1031
-	
+
 	#FCLK:HCLK:PCLK = 1:2:4
 	mww phys 0x4c000014 0x00000003
 
@@ -61,5 +61,3 @@ proc uptech2410_init { } {
 
 set _NANDNAME $_CHIPNAME.nand
 nand device $_NANDNAME s3c2410 $_TARGETNAME
-
-
diff --git a/tcl/board/verdex.cfg b/tcl/board/verdex.cfg
index 6da9875..dd267fc 100644
--- a/tcl/board/verdex.cfg
+++ b/tcl/board/verdex.cfg
@@ -8,7 +8,7 @@ source [find target/pxa270.cfg]
 reset_config trst_and_srst separate
 
 # XM4 = 400MHz, XL6P = 600MHz...let's run at 0.1*400MHz=40MHz
-adapter_khz 40000
+adapter speed 40000
 
 # flash bank <driver> <base> <size> <chip_width> <bus_width>
 # XL6P has 32 MB flash
diff --git a/tcl/board/voltcraft_dso-3062c.cfg b/tcl/board/voltcraft_dso-3062c.cfg
index 01e37e9..f300cf2 100644
--- a/tcl/board/voltcraft_dso-3062c.cfg
+++ b/tcl/board/voltcraft_dso-3062c.cfg
@@ -13,7 +13,7 @@
 
 source [find target/samsung_s3c2440.cfg]
 
-adapter_khz 16000
+adapter speed 16000
 
 # Samsung K9F1208U0C NAND flash chip (64MiB, 3.3V, 8-bit)
 nand device $_CHIPNAME.nand s3c2440 $_TARGETNAME
@@ -28,4 +28,3 @@ scan_chain
 targets
 nand probe 0
 nand list
-
diff --git a/tcl/board/zy1000.cfg b/tcl/board/zy1000.cfg
index 57deaa8..e0d1ccf 100644
--- a/tcl/board/zy1000.cfg
+++ b/tcl/board/zy1000.cfg
@@ -72,7 +72,7 @@ $_TARGETNAME configure -event gdb-attach {
 # other things than flash programming.
 $_TARGETNAME configure -work-area-phys 0x00020000 -work-area-size 0x20000 -work-area-backup 0
 
-adapter_khz 16000
+adapter speed 16000
 
 
 proc production_info {} {
author	Tim Newsome <tim@sifive.com>	2020-06-23 13:05:43 -0700
committer	Tim Newsome <tim@sifive.com>	2020-06-23 13:05:43 -0700
commit	e07613de332d2cda48cd1a845b6e19171f084571 (patch)
tree	e32451d4730030a2b1e8539cbfd6abf590a07896 /tcl/board
parent	4579dd93586ab361f40da6cbd9e3e0681efc866b (diff)
parent	8833c889da07eae750bcbc11215cc84323de9b74 (diff)
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