Merge branch 'master' into from_upstream

Conflicts: .gitmodules .travis.yml jimtcl src/jtag/core.c src/jtag/drivers/ftdi.c src/jtag/drivers/libjaylink src/jtag/drivers/mpsse.c src/jtag/drivers/stlink_usb.c src/rtos/hwthread.c src/target/riscv/riscv-013.c src/target/riscv/riscv.c tcl/board/sifive-hifive1-revb.cfg Change-Id: I2d26ebeffb4c1374730d2e20e6e2a7710403657c
author: Tim Newsome <tim@sifive.com> 2020-06-23 13:05:43 -0700
committer: Tim Newsome <tim@sifive.com> 2020-06-23 13:05:43 -0700
commit: e07613de332d2cda48cd1a845b6e19171f084571 (patch)
tree: e32451d4730030a2b1e8539cbfd6abf590a07896 /tcl
parent: 4579dd93586ab361f40da6cbd9e3e0681efc866b (diff)
parent: 8833c889da07eae750bcbc11215cc84323de9b74 (diff)
download: riscv-openocd-e07613de332d2cda48cd1a845b6e19171f084571.zip
riscv-openocd-e07613de332d2cda48cd1a845b6e19171f084571.tar.gz
riscv-openocd-e07613de332d2cda48cd1a845b6e19171f084571.tar.bz2
439 files changed, 2542 insertions, 973 deletions
diff --git a/tcl/bitsbytes.tcl b/tcl/bitsbytes.tcl
index 2c4fd29..52ca83d 100644
--- a/tcl/bitsbytes.tcl
+++ b/tcl/bitsbytes.tcl
@@ -57,5 +57,3 @@ proc show_normalize_bitfield { VALUE MSB LSB } {
     echo [format "((0x%08x & 0x%08x) -> 0x%08x) >> %2d => (0x%x) %5d " $VALUE $m $mr $LSB $sr $sr]
    return $sr
 }
-
-
diff --git a/tcl/board/actux3.cfg b/tcl/board/actux3.cfg
index 5435ff8..0de4cb4 100644
--- a/tcl/board/actux3.cfg
+++ b/tcl/board/actux3.cfg
@@ -4,7 +4,7 @@
 
 reset_config trst_and_srst separate
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 
 source [find target/ixp42x.cfg]
diff --git a/tcl/board/adsp-sc584-ezbrd.cfg b/tcl/board/adsp-sc584-ezbrd.cfg
index 1054a94..82df381 100644
--- a/tcl/board/adsp-sc584-ezbrd.cfg
+++ b/tcl/board/adsp-sc584-ezbrd.cfg
@@ -25,7 +25,6 @@ source [find interface/jlink.cfg]
 transport select swd
 
 # chosen speed is 'safe' choice, but your adapter may be capable of more
-adapter_khz 400
+adapter speed 400
 
 source [find target/adsp-sc58x.cfg]
-
diff --git a/tcl/board/alphascale_asm9260_ek.cfg b/tcl/board/alphascale_asm9260_ek.cfg
index 46e8a5b..1c12682 100644
--- a/tcl/board/alphascale_asm9260_ek.cfg
+++ b/tcl/board/alphascale_asm9260_ek.cfg
@@ -23,7 +23,7 @@ $_TARGETNAME configure -event reset-init {
 
 	# select PLL as main source
 	mww 0x80040120 0x1
-	# disable and enble main clk to update changes?
+	# disable and enable main clk to update changes?
 	mww 0x80040124 0x0
 	mww 0x80040124 0x1
 
diff --git a/tcl/board/altera_sockit.cfg b/tcl/board/altera_sockit.cfg
index 5694143..eb4c863 100644
--- a/tcl/board/altera_sockit.cfg
+++ b/tcl/board/altera_sockit.cfg
@@ -7,7 +7,7 @@
 
 # openocd does not currently support the on-board USB Blaster II.
 # Install the JTAG header and use a USB Blaster instead.
-interface usb_blaster
+adapter driver usb_blaster
 
 source [find target/altera_fpgasoc.cfg]
 
@@ -15,5 +15,4 @@ source [find target/altera_fpgasoc.cfg]
 #usb_blaster_vid_pid 0x6810 0x09fb
 #usb_blaster_device_desc "USB-Blaster II"
 
-adapter_khz 100
-
+adapter speed 100
diff --git a/tcl/board/am3517evm.cfg b/tcl/board/am3517evm.cfg
index 2bff512..8d6eba1 100644
--- a/tcl/board/am3517evm.cfg
+++ b/tcl/board/am3517evm.cfg
@@ -18,4 +18,3 @@ source [find target/amdm37x.cfg]
 reset_config trst_only
 
 # "amdm37x_dbginit am35x.cpu" needs to be run after init.
-
diff --git a/tcl/board/arm_evaluator7t.cfg b/tcl/board/arm_evaluator7t.cfg
index 52de57a..96d859c 100644
--- a/tcl/board/arm_evaluator7t.cfg
+++ b/tcl/board/arm_evaluator7t.cfg
@@ -7,4 +7,3 @@ source [find target/samsung_s3c4510.cfg]
 #  Add (A) sdram configuration
 #  Add (B) flash cfi programing configuration
 #
-
diff --git a/tcl/board/arm_musca_a.cfg b/tcl/board/arm_musca_a.cfg
index fa7cf5e..25f8ce6 100644
--- a/tcl/board/arm_musca_a.cfg
+++ b/tcl/board/arm_musca_a.cfg
@@ -15,7 +15,7 @@
 source [find target/swj-dp.tcl]
 
 # set a safe JTAG clock speed, can be overridden
-adapter_khz 1000
+adapter speed 1000
 
 global _CHIPNAME
 if { [info exists CHIPNAME] } {
diff --git a/tcl/board/arty_s7.cfg b/tcl/board/arty_s7.cfg
index ca7d3f1..5ab4083 100644
--- a/tcl/board/arty_s7.cfg
+++ b/tcl/board/arty_s7.cfg
@@ -10,7 +10,7 @@ source [find interface/ftdi/digilent-hs1.cfg]
 source [find cpld/xilinx-xc7.cfg]
 source [find cpld/jtagspi.cfg]
 
-adapter_khz 25000
+adapter speed 25000
 
 # Usage:
 #
diff --git a/tcl/board/at91cap7a-stk-sdram.cfg b/tcl/board/at91cap7a-stk-sdram.cfg
index 9bc02e8..8395ba3 100644
--- a/tcl/board/at91cap7a-stk-sdram.cfg
+++ b/tcl/board/at91cap7a-stk-sdram.cfg
@@ -28,7 +28,7 @@ target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAM
 
 $_TARGETNAME configure -event reset-start {
 	# start off real slow when we're running off internal RC oscillator
-	adapter_khz 32
+	adapter speed 32
 }
 
 proc peek32 {address} {
@@ -43,13 +43,13 @@ proc wait_state {expression} {
 			return
 		}
 	}
-	return -code 1 "Timed out"	
+	return -code 1 "Timed out"
 }
 
 # Use a global variable here to be able to tinker interactively with
 # post reset jtag frequency.
 global post_reset_khz
-# Danger!!!! Even 16MHz kinda works with this target, but 
+# Danger!!!! Even 16MHz kinda works with this target, but
 # it needs to be as low as 2000kHz to be stable.
 set post_reset_khz 2000
 
@@ -61,25 +61,25 @@ $_TARGETNAME configure -event reset-init {
 	mww 0xfffffd08 0xa5000001
 	# Enable main oscillator
 	mww 0xFFFFFc20  0x00000f01
-	wait_state {expr {([peek32 0xFFFFFC68] & 0x1) == 0}}  
+	wait_state {expr {([peek32 0xFFFFFC68] & 0x1) == 0}}
 
 	# Set PLLA to 96MHz
 	mww 0xFFFFFc28 0x20072801
-	wait_state {expr {([peek32 0xFFFFFC68] & 0x2) == 0}}  
+	wait_state {expr {([peek32 0xFFFFFC68] & 0x2) == 0}}
 
 	# Select prescaler
 	mww 0xFFFFFC30 0x00000004
-	wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}  
+	wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
 
 	# Select master clock to 48MHz
 	mww 0xFFFFFC30 0x00000006
-	wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}  
+	wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
 
 	echo "Master clock ok."
-	
+
 	# Now that we're up and running, crank up speed!
-	global post_reset_khz ;	adapter_khz $post_reset_khz
-	
+	global post_reset_khz ;	adapter speed $post_reset_khz
+
 	echo "Configuring the SDRAM controller..."
 
 	# Configure EBI Chip select for SDRAM
@@ -95,7 +95,7 @@ $_TARGETNAME configure -event reset-init {
 
 	# Configure SDRAMC CR
 	mww 0xFFFFEA08 0xA63392F9
- 
+
 	# NOP command
 	mww 0xFFFFEA00 0x1
 	mww 0x20000000 0
@@ -151,7 +151,7 @@ $_TARGETNAME configure -event reset-init {
 
 	#remap internal memory at address 0x0
 	mww 0xffffef00 0x3
-	
+
 	echo "SDRAM configuration ok."
 }
 
@@ -162,4 +162,3 @@ arm7_9 fast_memory_access enable
 
 #set _FLASHNAME $_CHIPNAME.flash
 #flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
-
diff --git a/tcl/board/at91eb40a.cfg b/tcl/board/at91eb40a.cfg
index d8a82a5..d314e18 100644
--- a/tcl/board/at91eb40a.cfg
+++ b/tcl/board/at91eb40a.cfg
@@ -64,4 +64,4 @@ $_TARGETNAME configure -event reset-init {
 }
 
 # This target is pretty snappy...
-adapter_khz 16000
+adapter speed 16000
diff --git a/tcl/board/at91rm9200-dk.cfg b/tcl/board/at91rm9200-dk.cfg
index f484fde..b8ec00e 100644
--- a/tcl/board/at91rm9200-dk.cfg
+++ b/tcl/board/at91rm9200-dk.cfg
@@ -19,7 +19,7 @@ flash bank $_FLASHNAME cfi 0x10000000 0x00200000 2 2 $_TARGETNAME
 proc at91rm9200_dk_init { } {
     # Try to run at 1khz... Yea, that slow!
     # Chip is really running @ 32khz
-    adapter_khz 8
+    adapter speed 8
 
     mww 0xfffffc64 0xffffffff
     ##  disable all clocks but system clock
@@ -45,7 +45,7 @@ proc at91rm9200_dk_init { } {
     #========================================
     # CPU now runs at 180mhz
     # SYS runs at 60mhz.
-    adapter_khz 40000
+    adapter speed 40000
     #========================================
 
 
diff --git a/tcl/board/at91rm9200-ek.cfg b/tcl/board/at91rm9200-ek.cfg
index a3f253a..958bc9d 100644
--- a/tcl/board/at91rm9200-ek.cfg
+++ b/tcl/board/at91rm9200-ek.cfg
@@ -19,12 +19,12 @@ set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
 
 # The chip may run @ 32khz, so set a really low JTAG speed
-adapter_khz 8
+adapter speed 8
 
 proc at91rm9200_ek_init { } {
 	# Try to run at 1khz... Yea, that slow!
 	# Chip is really running @ 32khz
-	adapter_khz 8
+	adapter speed 8
 
 	mww 0xfffffc64 0xffffffff
 	## disable all clocks but system clock
@@ -61,7 +61,7 @@ proc at91rm9200_ek_init { } {
 	#========================================
 	# CPU now runs at 180mhz
 	# SYS runs at 60mhz.
-	adapter_khz 40000
+	adapter speed 40000
 	#========================================
 
 	## Init SDRAM
diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg
index 741d601..03296c5 100644
--- a/tcl/board/at91sam9g20-ek.cfg
+++ b/tcl/board/at91sam9g20-ek.cfg
@@ -19,7 +19,7 @@ set _FLASHTYPE nandflash_cs3
 
 reset_config srst_only
 
-adapter_nsrst_delay 200
+adapter srst delay 200
 jtag_ntrst_delay 200
 
 # If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the
@@ -54,7 +54,7 @@ proc at91sam9g20_reset_start { } {
 	# jtag speed without causing GDB keep alive problem.
 
 	arm7_9 fast_memory_access disable
-	adapter_khz 2                   ;# Slow-speed oscillator enabled at reset, so run jtag speed slow.
+	adapter speed 2                 ;# Slow-speed oscillator enabled at reset, so run jtag speed slow.
 	halt                            ;# Make sure processor is halted, or error will result in following steps.
 	wait_halt 10000
 	mww 0xfffffd08 0xa5000501       ;# RSTC_MR : enable user reset.
@@ -103,7 +103,7 @@ proc at91sam9g20_reset_init { } {
 
 	# Switch over to adaptive clocking.
 
-	adapter_khz 0
+	adapter speed 0
 
 	# Enable faster DCC downloads and memory accesses.
 
@@ -139,13 +139,13 @@ proc at91sam9g20_reset_init { } {
 	# (MT29F2G08AACWP) can be established by setting four registers in order:  SMC_SETUP3,
 	# SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.  Computing the exact values of these registers
 	# is a little tedious to do here.  If you have questions about how to do this, Atmel has
-	# a decent application note #6255B that covers this process. 
+	# a decent application note #6255B that covers this process.
 
 	mww 0xffffec30 0x00020002	;# SMC_SETUP3 : 2 clock cycle setup for NRD and NWE
 	mww 0xffffec34 0x04040404	;# SMC_PULSE3 : 4 clock cycle pulse for all signals
 	mww 0xffffec38 0x00070006	;# SMC_CYCLE3 : 7 clock cycle NRD and 6 NWE cycle
-	mww 0xffffec3C 0x00020003	;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW, 
-   
+	mww 0xffffec3C 0x00020003	;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
+
 	mww 0xffffe800 0x00000001	;# ECC_CR : reset the ECC parity registers
 	mww 0xffffe804 0x00000002	;# ECC_MR : page size is 2112 words (word is 8 bits)
 
@@ -169,7 +169,7 @@ proc at91sam9g20_reset_init { } {
 	#	TRC = 9 cycles
 	#	TWR = 2 cycles
 	#	9 column, 13 row, 4 banks
-	#	refresh equal to or less then 7.8 us for commerical/industrial rated devices
+	#	refresh equal to or less then 7.8 us for commercial/industrial rated devices
 	#
 	#	Thus SDRAM_CR = 0xa6339279
 
@@ -216,4 +216,3 @@ proc at91sam9g20_reset_init { } {
 
 	mww 0xffffea04 0x0000039c
 }
-
diff --git a/tcl/board/atmel_at91sam7s-ek.cfg b/tcl/board/atmel_at91sam7s-ek.cfg
index d7e8486..48edfc9 100644
--- a/tcl/board/atmel_at91sam7s-ek.cfg
+++ b/tcl/board/atmel_at91sam7s-ek.cfg
@@ -4,5 +4,3 @@
 set CHIPNAME at91sam7s256
 
 source [find target/at91sam7sx.cfg]
-
-
diff --git a/tcl/board/atmel_sam3n_ek.cfg b/tcl/board/atmel_sam3n_ek.cfg
index 2ae73eb..e43008f 100644
--- a/tcl/board/atmel_sam3n_ek.cfg
+++ b/tcl/board/atmel_sam3n_ek.cfg
@@ -7,6 +7,6 @@ reset_config srst_only
 
 set CHIPNAME at91sam3n4c
 
-adapter_khz 32
+adapter speed 32
 
 source [find target/at91sam3nXX.cfg]
diff --git a/tcl/board/atmel_sam3u_ek.cfg b/tcl/board/atmel_sam3u_ek.cfg
index 13d930b..1584879 100644
--- a/tcl/board/atmel_sam3u_ek.cfg
+++ b/tcl/board/atmel_sam3u_ek.cfg
@@ -1,4 +1,3 @@
 source [find target/at91sam3u4e.cfg]
 
 reset_config srst_only
-
diff --git a/tcl/board/avnet_ultrazed-eg.cfg b/tcl/board/avnet_ultrazed-eg.cfg
index 9879bfc..3e4a11a 100644
--- a/tcl/board/avnet_ultrazed-eg.cfg
+++ b/tcl/board/avnet_ultrazed-eg.cfg
@@ -9,7 +9,7 @@ transport select jtag
 reset_config none
 
 # slow default clock
-adapter_khz 1000
+adapter speed 1000
 
 set CHIPNAME uscale
 
diff --git a/tcl/board/bcm28155_ap.cfg b/tcl/board/bcm28155_ap.cfg
index fb729e1..5d3d22a 100644
--- a/tcl/board/bcm28155_ap.cfg
+++ b/tcl/board/bcm28155_ap.cfg
@@ -1,9 +1,8 @@
 # BCM28155_AP
 
-adapter_khz 20000
+adapter speed 20000
 
 set CHIPNAME bcm28155
 source [find target/bcm281xx.cfg]
 
 reset_config trst_and_srst
-
diff --git a/tcl/board/bluefield.cfg b/tcl/board/bluefield.cfg
new file mode 100644
index 0000000..3058d48
--- /dev/null
+++ b/tcl/board/bluefield.cfg
@@ -0,0 +1,6 @@
+#
+# Board configuration for BlueField SoC.
+#
+
+source [find interface/rshim.cfg]
+source [find target/bluefield.cfg]
diff --git a/tcl/board/colibri.cfg b/tcl/board/colibri.cfg
index 7c1f1cb..0f30afd 100644
--- a/tcl/board/colibri.cfg
+++ b/tcl/board/colibri.cfg
@@ -1,13 +1,9 @@
 # Toradex Colibri PXA270
 source [find target/pxa270.cfg]
 reset_config trst_and_srst srst_push_pull
-adapter_nsrst_assert_width 40
+adapter srst pulse_width 40
 
 # CS0 -- one bank of CFI flash, 32 MBytes
 # the bank is 32-bits wide, two 16-bit chips in parallel
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
-
-
-
-
diff --git a/tcl/board/crossbow_tech_imote2.cfg b/tcl/board/crossbow_tech_imote2.cfg
index 002b537..277c353 100644
--- a/tcl/board/crossbow_tech_imote2.cfg
+++ b/tcl/board/crossbow_tech_imote2.cfg
@@ -4,7 +4,7 @@ set  CHIPNAME imote2
 source [find target/pxa270.cfg]
 
 # longer-than-normal reset delay
-adapter_nsrst_delay 800
+adapter srst delay 800
 
 reset_config trst_and_srst separate
 
diff --git a/tcl/board/csb337.cfg b/tcl/board/csb337.cfg
index 5e225f5..a9d0139 100644
--- a/tcl/board/csb337.cfg
+++ b/tcl/board/csb337.cfg
@@ -19,7 +19,7 @@ if { [info exists ETM_DRIVER] } {
 
 proc csb337_clk_init { } {
 	# CPU is in Slow Clock Mode (32KiHz) ... needs slow JTAG clock
-	adapter_khz 8
+	adapter speed 8
 
 	# CKGR_MOR:  start main oscillator (3.6864 MHz)
 	mww 0xfffffc20 0xff01
@@ -37,7 +37,7 @@ proc csb337_clk_init { } {
 	sleep 20
 
 	# CPU is in Normal Mode ... allows faster JTAG clock speed
-	adapter_khz 40000
+	adapter speed 40000
 }
 
 proc csb337_nor_init { } {
diff --git a/tcl/board/csb732.cfg b/tcl/board/csb732.cfg
index 4d6f0e4..35e397f 100644
--- a/tcl/board/csb732.cfg
+++ b/tcl/board/csb732.cfg
@@ -3,7 +3,7 @@ source [find target/imx35.cfg]
 
 # Determined by trial and error
 reset_config trst_and_srst combined
-adapter_nsrst_delay 200
+adapter srst delay 200
 jtag_ntrst_delay 200
 
 $_TARGETNAME configure -event gdb-attach { reset init }
diff --git a/tcl/board/digi_connectcore_wi-9c.cfg b/tcl/board/digi_connectcore_wi-9c.cfg
index 8a8d4c3..43ad1c9 100644
--- a/tcl/board/digi_connectcore_wi-9c.cfg
+++ b/tcl/board/digi_connectcore_wi-9c.cfg
@@ -36,7 +36,7 @@ if { [info exists CPUTAPID] } {
 set _TARGETNAME $_CHIPNAME.cpu
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
-adapter_nsrst_delay 200
+adapter srst delay 200
 jtag_ntrst_delay 0
 
 
diff --git a/tcl/board/digilent_analog_discovery.cfg b/tcl/board/digilent_analog_discovery.cfg
index d356fc0..954e540 100644
--- a/tcl/board/digilent_analog_discovery.cfg
+++ b/tcl/board/digilent_analog_discovery.cfg
@@ -7,12 +7,12 @@
 # https://github.com/bvanheu/urjtag-ad/commit/8bd883ee01d134f94b79cbbd00df42cd03bafd71
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Digilent USB Device"
 ftdi_vid_pid 0x0403 0x6014
 
 ftdi_layout_init 0x8008 0x800b
 
-adapter_khz 25000
+adapter speed 25000
 
 source [find cpld/xilinx-xc6s.cfg]
diff --git a/tcl/board/dk-tm4c129.cfg b/tcl/board/dk-tm4c129.cfg
index f1171af..2c7de29 100755..100644
--- a/tcl/board/dk-tm4c129.cfg
+++ b/tcl/board/dk-tm4c129.cfg
@@ -1,14 +1,3 @@
-#
-# TI Tiva C DK-TM4C129X Connected Development Kit
-#
-# http://www.ti.com/tool/dk-tm4c129x
-#
+echo "WARNING: board/dk-tm4c129.cfg is deprecated, please switch to board/ti_dk-tm4c129.cfg"
 
-source [find interface/ti-icdi.cfg]
-
-transport select hla_jtag
-
-set WORKAREASIZE 0x8000
-set CHIPNAME tm4c129xnczad
-
-source [find target/stellaris.cfg]
+source [find board/ti_dk-tm4c129.cfg]
diff --git a/tcl/board/dm365evm.cfg b/tcl/board/dm365evm.cfg
index 8f268c4..3b29dd8 100644
--- a/tcl/board/dm365evm.cfg
+++ b/tcl/board/dm365evm.cfg
@@ -103,7 +103,7 @@ proc dm365evm_init {} {
 	echo "Initialize DM365 EVM board"
 
 	# CLKIN	= 24 MHz ... can't talk quickly to ARM yet
-	adapter_khz 1500
+	adapter speed 1500
 
 	# FIXME -- PLL init
 
@@ -143,5 +143,3 @@ proc dm365evm_init {} {
 
 	flashprobe
 }
-
-
diff --git a/tcl/board/dp_busblaster_v3.cfg b/tcl/board/dp_busblaster_v3.cfg
index f21197b..a9974d9 100644
--- a/tcl/board/dp_busblaster_v3.cfg
+++ b/tcl/board/dp_busblaster_v3.cfg
@@ -4,7 +4,7 @@
 # http://dangerousprototypes.com/docs/Bus_Blaster
 #
 # To reprogram the on-board CPLD do:
-# openocd -f board/dp_busblaster_v3.cfg -c "adapter_khz 1000; init; svf <path_to_svf>; shutdown"
+# openocd -f board/dp_busblaster_v3.cfg -c "adapter speed 1000; init; svf <path_to_svf>; shutdown"
 #
 
 source [find interface/ftdi/dp_busblaster.cfg]
diff --git a/tcl/board/efm32.cfg b/tcl/board/efm32.cfg
index d2bc9a6..adbdda7 100644
--- a/tcl/board/efm32.cfg
+++ b/tcl/board/efm32.cfg
@@ -5,7 +5,7 @@
 
 source [find interface/jlink.cfg]
 transport select swd
-adapter_khz 1000
+adapter speed 1000
 
 set CHIPNAME efm32
 source [find target/efm32.cfg]
diff --git a/tcl/board/eir.cfg b/tcl/board/eir.cfg
index a014e11..422db0d 100644
--- a/tcl/board/eir.cfg
+++ b/tcl/board/eir.cfg
@@ -91,4 +91,3 @@ $_TARGETNAME configure -event reset-init {
 	#
 	mww 0xfffffd08 0xa5000001
 }
-
diff --git a/tcl/board/ek-lm3s1968.cfg b/tcl/board/ek-lm3s1968.cfg
index 8d990b1..bbb04ba 100644
--- a/tcl/board/ek-lm3s1968.cfg
+++ b/tcl/board/ek-lm3s1968.cfg
@@ -5,7 +5,7 @@
 #
 
 # NOTE:  to use J-Link instead of the on-board interface,
-# you may also need to reduce adapter_khz to be about 1200.
+# you may also need to reduce adapter speed to be about 1200.
 # source [find interface/jlink.cfg]
 
 # include the FT2232 interface config for on-board JTAG interface
diff --git a/tcl/board/ek-tm4c123gxl.cfg b/tcl/board/ek-tm4c123gxl.cfg
index 4fc1050..3e497ba 100644
--- a/tcl/board/ek-tm4c123gxl.cfg
+++ b/tcl/board/ek-tm4c123gxl.cfg
@@ -1,13 +1,3 @@
-#
-# TI Tiva C Series ek-tm4c123gxl Launchpad Evaluation Kit
-#
-# http://www.ti.com/tool/ek-tm4c123gxl
-#
+echo "WARNING: board/ek-tm4c123gxl.cfg is deprecated, please switch to board/ti_ek-tm4c123gxl.cfg"
 
-source [find interface/ti-icdi.cfg]
-
-transport select hla_jtag
-
-set WORKAREASIZE 0x8000
-set CHIPNAME tm4c123gh6pm
-source [find target/stellaris.cfg]
+source [find board/ti_ek-tm4c123gxl.cfg]
diff --git a/tcl/board/ek-tm4c1294xl.cfg b/tcl/board/ek-tm4c1294xl.cfg
index b3f384c..6763866 100644
--- a/tcl/board/ek-tm4c1294xl.cfg
+++ b/tcl/board/ek-tm4c1294xl.cfg
@@ -1,14 +1,3 @@
-#
-# TI Tiva C Series ek-tm4c1294xl Launchpad Evaluation Kit
-#
-# http://www.ti.com/tool/ek-tm4c1294xl
-#
+echo "WARNING: board/ek-tm4c1294xl.cfg is deprecated, please switch to board/ti_ek-tm4c1294xl.cfg"
 
-source [find interface/ti-icdi.cfg]
-
-transport select hla_jtag
-
-set WORKAREASIZE 0x8000
-set CHIPNAME tm4c1294ncpdt
-
-source [find target/stellaris.cfg]
+source [find board/ti_ek-tm4c1294xl.cfg]
diff --git a/tcl/board/embedded-artists_lpc2478-32.cfg b/tcl/board/embedded-artists_lpc2478-32.cfg
index b036cd6..8ef9179 100644
--- a/tcl/board/embedded-artists_lpc2478-32.cfg
+++ b/tcl/board/embedded-artists_lpc2478-32.cfg
@@ -15,7 +15,7 @@ proc read_register {register} {
 
 proc init_board {} {
     # Delays on reset lines
-    adapter_nsrst_delay 500
+    adapter srst delay 500
     jtag_ntrst_delay 1
 
     # Adaptive JTAG clocking through RTCK.
@@ -151,4 +151,3 @@ proc enable_pll {} {
     mww 0xE01FC08C 0x000000AA       ;# PLLFEED
     mww 0xE01FC08C 0x00000055       ;# PLLFEED
 }
-
diff --git a/tcl/board/emcraft_imx8m-som-bsb.cfg b/tcl/board/emcraft_imx8m-som-bsb.cfg
index 5571d0e..248c0d4 100644
--- a/tcl/board/emcraft_imx8m-som-bsb.cfg
+++ b/tcl/board/emcraft_imx8m-som-bsb.cfg
@@ -6,13 +6,13 @@
 transport select jtag
 
 # set a safe JTAG clock speed, can be overridden
-adapter_khz 1000
+adapter speed 1000
 
 # SRST and TRST are wired up
 reset_config trst_and_srst
 
 # delay after SRST goes inactive
-adapter_nsrst_delay 70
+adapter srst delay 70
 
 # board has an i.MX8MQ with 4 Cortex-A53 cores
 set CHIPNAME imx8mq
diff --git a/tcl/board/ethernut3.cfg b/tcl/board/ethernut3.cfg
index ad45527..72fc5ad 100644
--- a/tcl/board/ethernut3.cfg
+++ b/tcl/board/ethernut3.cfg
@@ -20,13 +20,13 @@ flash bank $_FLASHNAME cfi 0x10000000 0x400000 2 2 $_TARGETNAME
 # Micrel MIC2775-29YM5 Supervisor
 # Reset output will remain active for 280ms (maximum)
 #
-adapter_nsrst_delay 300
+adapter srst delay 300
 jtag_ntrst_delay 300
 
 
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable
-adapter_khz 16000
+adapter speed 16000
 
 
 # Target events
diff --git a/tcl/board/fsl_imx6q_sabresd.cfg b/tcl/board/fsl_imx6q_sabresd.cfg
index e1f0892..cf34cd1 100644
--- a/tcl/board/fsl_imx6q_sabresd.cfg
+++ b/tcl/board/fsl_imx6q_sabresd.cfg
@@ -13,7 +13,7 @@ transport select jtag
 
 # iMX6Q POR gates JTAG and the chip is completely incommunicado
 # over JTAG for at least 10ms after nSRST is deasserted
-adapter_nsrst_delay 11
+adapter srst delay 11
 
 # Source generic iMX6Q target configuration
 set CHIPNAME imx6q
@@ -144,4 +144,4 @@ $_TARGETNAME.0 configure -event reset-assert { }
 # hook the init function into the reset-init event
 $_TARGETNAME.0 configure -event reset-init { imx6q_sabresd_init }
 # set a slow default JTAG clock, can be overridden later
-adapter_khz 1000
+adapter speed 1000
diff --git a/tcl/board/glyn_tonga2.cfg b/tcl/board/glyn_tonga2.cfg
index 17ed3cf..f48702c 100644
--- a/tcl/board/glyn_tonga2.cfg
+++ b/tcl/board/glyn_tonga2.cfg
@@ -19,12 +19,12 @@ source [find target/tmpa900.cfg]
 # Initial JTAG speed should not exceed 1/6 of the initial CPU clock
 # frequency (24MHz). Be conservative and use 1/8 of the frequency.
 # (24MHz / 8 = 3MHz)
-adapter_khz 3000
+adapter speed 3000
 
 $_TARGETNAME configure -event reset-start {
 	# Upon reset, set the JTAG frequency to 3MHz again, see above.
 	echo "Setting JTAG speed to 3MHz until clocks are initialized."
-	adapter_khz 3000
+	adapter speed 3000
 
 	# Halt the CPU.
 	halt
@@ -41,7 +41,7 @@ $_TARGETNAME configure -event reset-init {
 	# Tests showed that 15MHz works OK, higher speeds can cause problems,
 	# though. Not sure if this is a CPU issue or JTAG adapter issue.
 	echo "Increasing JTAG speed to 15MHz."
-	adapter_khz 15000
+	adapter speed 15000
 
 	# Enable faster memory access.
 	arm7_9 fast_memory_access enable
@@ -197,4 +197,3 @@ proc tonga2_init { } {
 #######################
 
 # TODO: Implement NAND support.
-
diff --git a/tcl/board/gumstix-aerocore.cfg b/tcl/board/gumstix-aerocore.cfg
index ba217c0..f0103ed 100644
--- a/tcl/board/gumstix-aerocore.cfg
+++ b/tcl/board/gumstix-aerocore.cfg
@@ -1,6 +1,6 @@
 # JTAG for the STM32F4x chip used on the Gumstix AeroCore is available on
 # the first interface of a Quad FTDI chip.  nTRST is bit 4.
-interface ftdi
+adapter driver ftdi
 ftdi_vid_pid 0x0403 0x6011
 
 ftdi_layout_init 0x0000 0x001b
diff --git a/tcl/board/hilscher_nxdb500sys.cfg b/tcl/board/hilscher_nxdb500sys.cfg
index 77073e7..20fa3ea 100644
--- a/tcl/board/hilscher_nxdb500sys.cfg
+++ b/tcl/board/hilscher_nxdb500sys.cfg
@@ -5,7 +5,7 @@
 source [find target/hilscher_netx500.cfg]
 
 reset_config trst_and_srst
-adapter_nsrst_delay 500
+adapter srst delay 500
 jtag_ntrst_delay 500
 
 $_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
@@ -17,7 +17,7 @@ $_TARGETNAME configure -event reset-init {
   arm7_9 dcc_downloads enable
 
   sdram_fix
-  
+
   puts "Configuring SDRAM controller for paired K4S561632C (64MB) "
   mww 0x00100140 0
   mww 0x00100144 0x03C13261
diff --git a/tcl/board/hilscher_nxeb500hmi.cfg b/tcl/board/hilscher_nxeb500hmi.cfg
index 6439156..a51fa03 100644
--- a/tcl/board/hilscher_nxeb500hmi.cfg
+++ b/tcl/board/hilscher_nxeb500hmi.cfg
@@ -5,7 +5,7 @@
 source [find target/hilscher_netx500.cfg]
 
 reset_config trst_and_srst
-adapter_nsrst_delay 500
+adapter srst delay 500
 jtag_ntrst_delay 500
 
 $_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
@@ -17,7 +17,7 @@ $_TARGETNAME configure -event reset-init {
   arm7_9 dcc_downloads disable
 
   sdram_fix
-  
+
   puts "Configuring SDRAM controller for MT48LC8M32 (32MB) "
   mww 0x00100140 0
   mww 0x00100144 0x03C23251
diff --git a/tcl/board/hilscher_nxhx10.cfg b/tcl/board/hilscher_nxhx10.cfg
index 4ef2f3b..add424d 100644
--- a/tcl/board/hilscher_nxhx10.cfg
+++ b/tcl/board/hilscher_nxhx10.cfg
@@ -9,7 +9,7 @@ source [find target/hilscher_netx10.cfg]
 # problems try to line below
 # reset_config trst_and_srst srst_pulls_trst
 reset_config trst_and_srst
-adapter_nsrst_delay 500
+adapter srst delay 500
 jtag_ntrst_delay 500
 
 $_TARGETNAME configure -work-area-virt 0x08000000 -work-area-phys 0x08000000 -work-area-size 0x4000 -work-area-backup 1
@@ -79,4 +79,4 @@ $_TARGETNAME configure -event reset-init {
 #flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME
 
 init
-reset init
-\ No newline at end of file
+reset init
diff --git a/tcl/board/hilscher_nxhx50.cfg b/tcl/board/hilscher_nxhx50.cfg
index eebb165..0867f2e 100644
--- a/tcl/board/hilscher_nxhx50.cfg
+++ b/tcl/board/hilscher_nxhx50.cfg
@@ -5,7 +5,7 @@
 source [find target/hilscher_netx50.cfg]
 
 reset_config trst_and_srst
-adapter_nsrst_delay 500
+adapter srst delay 500
 jtag_ntrst_delay 500
 
 $_TARGETNAME configure -work-area-virt 0x10000000 -work-area-phys 0x10000000 -work-area-size 0x4000 -work-area-backup 1
diff --git a/tcl/board/hilscher_nxhx500.cfg b/tcl/board/hilscher_nxhx500.cfg
index dd3a951..2ba030e 100644
--- a/tcl/board/hilscher_nxhx500.cfg
+++ b/tcl/board/hilscher_nxhx500.cfg
@@ -5,7 +5,7 @@
 source [find target/hilscher_netx500.cfg]
 
 reset_config trst_and_srst
-adapter_nsrst_delay 500
+adapter srst delay 500
 jtag_ntrst_delay 500
 
 $_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
diff --git a/tcl/board/hilscher_nxsb100.cfg b/tcl/board/hilscher_nxsb100.cfg
index efb091b..c332bee 100644
--- a/tcl/board/hilscher_nxsb100.cfg
+++ b/tcl/board/hilscher_nxsb100.cfg
@@ -5,7 +5,7 @@
 source [find target/hilscher_netx500.cfg]
 
 reset_config trst_and_srst
-adapter_nsrst_delay 500
+adapter srst delay 500
 jtag_ntrst_delay 500
 
 $_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
@@ -17,7 +17,7 @@ $_TARGETNAME configure -event reset-init {
   arm7_9 dcc_downloads enable
 
   sdram_fix
-  
+
   puts "Configuring SDRAM controller for MT48LC2M32 (8MB) "
   mww 0x00100140 0
   mww 0x00100144 0x03C23251
diff --git a/tcl/board/hitex_lpc1768stick.cfg b/tcl/board/hitex_lpc1768stick.cfg
index 161e965..ac176ca 100644
--- a/tcl/board/hitex_lpc1768stick.cfg
+++ b/tcl/board/hitex_lpc1768stick.cfg
@@ -11,5 +11,4 @@ source [find target/lpc17xx.cfg]
 
 
 # startup @ 500kHz
-adapter_khz 500
-
+adapter speed 500
diff --git a/tcl/board/hitex_lpc2929.cfg b/tcl/board/hitex_lpc2929.cfg
index d251537..2fe1f3c 100644
--- a/tcl/board/hitex_lpc2929.cfg
+++ b/tcl/board/hitex_lpc2929.cfg
@@ -2,12 +2,12 @@
 # http://www.hitex.com/
 
 # Delays on reset lines
-adapter_nsrst_delay 50
+adapter srst delay 50
 jtag_ntrst_delay 1
 
 # Maximum of 1/8 of clock frequency (XTAL = 16 MHz).
 # Adaptive clocking through RTCK is not supported.
-adapter_khz 2000
+adapter speed 2000
 
 # Target device: LPC29xx with ETB
 # The following variables are used by the LPC2900 script:
@@ -24,7 +24,7 @@ $_TARGETNAME configure -work-area-phys 0x58000000 -work-area-size 0x10000 -work-
 # Event handlers
 $_TARGETNAME configure -event reset-start {
   # Back to the slow JTAG clock
-  adapter_khz 2000
+  adapter speed 2000
 }
 
 # External 16-bit flash at chip select CS7 (SST39VF3201-70, 4 MiB)
@@ -46,7 +46,7 @@ $_TARGETNAME configure -event reset-init {
   mww 0xFFFF8070 0x02000000     ;# SYS_CLK_CONF: PLL
 
   # Increase JTAG speed
-  adapter_khz 6000
+  adapter speed 6000
 
   # Enable external memory bus (16-bit SRAM at CS6, 16-bit flash at CS7)
   mww 0xE0001138 0x0000001F     ;# P1.14 = D0
@@ -103,4 +103,3 @@ $_TARGETNAME configure -event reset-init {
   mww 0x600000CC 0x0000000C     ;# Bank7 WST2=8
   mww 0x600000C4 0x00000002     ;# Bank7 IDCY=2
 }
-
diff --git a/tcl/board/hitex_stm32-performancestick.cfg b/tcl/board/hitex_stm32-performancestick.cfg
index 82fb169..74dc583 100644
--- a/tcl/board/hitex_stm32-performancestick.cfg
+++ b/tcl/board/hitex_stm32-performancestick.cfg
@@ -12,5 +12,4 @@ source [find target/stm32f1x.cfg]
 jtag newtap str750 cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id 0x4f1f0041
 
 # for some reason this board like to startup @ 500kHz
-adapter_khz 500
-
+adapter speed 500
diff --git a/tcl/board/hitex_str9-comstick.cfg b/tcl/board/hitex_str9-comstick.cfg
index be15331..3b92252 100644
--- a/tcl/board/hitex_str9-comstick.cfg
+++ b/tcl/board/hitex_str9-comstick.cfg
@@ -5,9 +5,9 @@
 source [find interface/ftdi/hitex_str9-comstick.cfg]
 
 # set jtag speed
-adapter_khz 3000
+adapter speed 3000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 #use combined on interfaces or targets that can't set TRST/SRST separately
 reset_config trst_and_srst
diff --git a/tcl/board/iar_lpc1768.cfg b/tcl/board/iar_lpc1768.cfg
index d8c8c2d..38ffc35 100644
--- a/tcl/board/iar_lpc1768.cfg
+++ b/tcl/board/iar_lpc1768.cfg
@@ -14,4 +14,3 @@ $_TARGETNAME configure -event reset-init {
 
 	flash probe 0
 }
-
diff --git a/tcl/board/iar_str912_sk.cfg b/tcl/board/iar_str912_sk.cfg
index ba060a0..54f517b 100644
--- a/tcl/board/iar_str912_sk.cfg
+++ b/tcl/board/iar_str912_sk.cfg
@@ -1,3 +1,3 @@
 # The IAR str912-sk evaluation kick start board has an str912
 
-source [find target/str912.cfg]
-\ No newline at end of file
+source [find target/str912.cfg]
diff --git a/tcl/board/icnova_imx53_sodimm.cfg b/tcl/board/icnova_imx53_sodimm.cfg
index aa6a148..dce9c47 100644
--- a/tcl/board/icnova_imx53_sodimm.cfg
+++ b/tcl/board/icnova_imx53_sodimm.cfg
@@ -15,14 +15,14 @@ echo "i.MX53 SO-Dimm board lodaded."
 # Set reset type
 #reset_config srst_only
 
-adapter_khz 3000
+adapter speed 3000
 
 # Slow speed to be sure it will work
 jtag_rclk 1000
 $_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
 
 $_TARGETNAME configure -event "reset-assert" {
-	echo "Reseting ...."
+	echo "Resetting ...."
 	#cortex_a dbginit
 }
 
@@ -58,7 +58,7 @@ proc sodimm_init { } {
 	arm core_state arm
 
 	jtag_rclk 3000
-#	adapter_khz 3000
+#	adapter speed 3000
 }
 
 
diff --git a/tcl/board/icnova_sam9g45_sodimm.cfg b/tcl/board/icnova_sam9g45_sodimm.cfg
index 84dab38..30dc347 100644
--- a/tcl/board/icnova_sam9g45_sodimm.cfg
+++ b/tcl/board/icnova_sam9g45_sodimm.cfg
@@ -15,7 +15,7 @@ source [find target/at91sam9g45.cfg]
 # Set reset type.
 # reset_config trst_and_srst
 
-# adapter_nsrst_delay 200
+# adapter srst delay 200
 # jtag_ntrst_delay 200
 
 
@@ -58,7 +58,7 @@ proc at91sam9g45_start { } {
 
 	arm7_9 fast_memory_access disable
     # Slow-speed oscillator enabled at reset, so run jtag speed slow.
-	adapter_khz 4
+	adapter speed 4
     # Make sure processor is halted, or error will result in following steps.
 	halt
 	wait_halt 10000
@@ -117,7 +117,7 @@ proc at91sam9g45_init { } {
 
 	# Switch over to adaptive clocking.
 
-	adapter_khz 6000
+	adapter speed 6000
 
 	# Enable faster DCC downloads.
 
@@ -274,5 +274,3 @@ proc at91sam9g45_init { } {
 
 	arm7_9 fast_memory_access enable
 }
-
-
diff --git a/tcl/board/imx27lnst.cfg b/tcl/board/imx27lnst.cfg
index e0ed057..ac5a9f3 100644
--- a/tcl/board/imx27lnst.cfg
+++ b/tcl/board/imx27lnst.cfg
@@ -8,7 +8,7 @@ proc imx27lnst_init { } {
 	# This setup puts RAM at 0xA0000000
 
 	# reset the board correctly
-	adapter_khz 500
+	adapter speed 500
 	reset run
 	reset halt
 
diff --git a/tcl/board/imx31pdk.cfg b/tcl/board/imx31pdk.cfg
index 502d407..2dce157 100644
--- a/tcl/board/imx31pdk.cfg
+++ b/tcl/board/imx31pdk.cfg
@@ -28,36 +28,36 @@ proc imx31pdk_init { } {
 
 	mww 0x53FC0000 0x040
 	mww 0x53F80000 0x074B0B7D
-	
+
 	# 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
 	#mww 0x53F80004 0xFF871D50
 	#mww 0x53F80010 0x00271C1B
-	
+
 	# Start 16 bit NorFlash Initialization on CS0
 	mww 0xb8002000 0x0000CC03
 	mww 0xb8002004 0xa0330D01
 	mww 0xb8002008 0x00220800
-	
+
 	# Configure CPLD on CS4
 	mww 0xb8002040 0x0000DCF6
 	mww 0xb8002044 0x444A4541
 	mww 0xb8002048 0x44443302
-	
+
 	# SDCLK
 	mww 0x43FAC26C 0
-	
+
 	# CAS
 	mww 0x43FAC270 0
-	
+
 	# RAS
 	mww 0x43FAC274 0
-	
+
 	# CS2 (CSD0)
 	mww 0x43FAC27C 0x1000
-	
+
 	# DQM3
 	mww 0x43FAC284 0
-	
+
 	# DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
 	mww 0x43FAC288 0
 	mww 0x43FAC28C 0
@@ -81,7 +81,7 @@ proc imx31pdk_init { } {
 	mww 0x43FAC2D4 0
 	mww 0x43FAC2D8 0
 	mww 0x43FAC2DC 0
-	
+
 	# Initialization script for 32 bit DDR on MX31 ADS
 	mww 0xB8001010 0x00000004
 	mww 0xB8001004 0x006ac73a
diff --git a/tcl/board/imx35pdk.cfg b/tcl/board/imx35pdk.cfg
index b5aa752..2a7efab 100644
--- a/tcl/board/imx35pdk.cfg
+++ b/tcl/board/imx35pdk.cfg
@@ -8,9 +8,9 @@ $_TARGETNAME configure -event reset-init { imx35pdk_init }
 jtag_rclk 10
 
 proc imx35pdk_init { } {
-	
+
 	imx3x_reset
-	
+
 	mww 0x43f00040 0x00000000
 	mww 0x43f00044 0x00000000
 	mww 0x43f00048 0x00000000
@@ -25,11 +25,11 @@ proc imx35pdk_init { } {
 	mww 0x53f00050 0x00000000
 	mww 0x53f00000 0x77777777
 	mww 0x53f00004 0x77777777
-	
+
 	# clock setup
 	mww 0x53F80004 0x00821000 ;# first need to set IPU_HND_BYP
 	mww 0x53F80004 0x00821000 ;#arm clock is 399Mhz and ahb clock is 133Mhz.
-	
+
 	#=================================================
 	# WEIM config
 	#=================================================
@@ -45,14 +45,14 @@ proc imx35pdk_init { } {
 	mww 0xB8002054 0x444a4541
 	# CS5A
 	mww 0xB8002058 0x44443302
-	
+
 	# IO SW PAD Control registers - setting of 0x0002 is high drive, mDDR
 	mww 0x43FAC368 0x00000006
 	mww 0x43FAC36C 0x00000006
 	mww 0x43FAC370 0x00000006
 	mww 0x43FAC374 0x00000006
 	mww 0x43FAC378 0x00000006
-	mww 0x43FAC37C 0x00000006	
+	mww 0x43FAC37C 0x00000006
 	mww 0x43FAC380 0x00000006
 	mww 0x43FAC384 0x00000006
 	mww 0x43FAC388 0x00000006
@@ -76,7 +76,7 @@ proc imx35pdk_init { } {
 	mww 0x43FAC3D0 0x00000006
 	mww 0x43FAC3D4 0x00000006
 	mww 0x43FAC3D8 0x00000006
-	
+
 	# DDR data bus SD 0 through 31
 	mww 0x43FAC3DC 0x00000082
 	mww 0x43FAC3E0 0x00000082
@@ -110,13 +110,13 @@ proc imx35pdk_init { } {
 	mww 0x43FAC450 0x00000082
 	mww 0x43FAC454 0x00000082
 	mww 0x43FAC458 0x00000082
-	
+
 	# DQM setup
 	mww 0x43FAC45c 0x00000082
 	mww 0x43FAC460 0x00000082
 	mww 0x43FAC464 0x00000082
 	mww 0x43FAC468 0x00000082
-	
+
 	mww 0x43FAC46c 0x00000006
 	mww 0x43FAC470 0x00000006
 	mww 0x43FAC474 0x00000006
@@ -130,30 +130,30 @@ proc imx35pdk_init { } {
 	mww 0x43FAC494 0x00000006
 	mww 0x43FAC498 0x00000006
 	mww 0x43FAC49c 0x00000006
-	mww 0x43FAC4A0 0x00000006	
+	mww 0x43FAC4A0 0x00000006
 	mww 0x43FAC4A4 0x00000006	;# RAS
 	mww 0x43FAC4A8 0x00000006	;# CAS
 	mww 0x43FAC4Ac 0x00000006	;# SDWE
 	mww 0x43FAC4B0 0x00000006 	;# SDCKE0
 	mww 0x43FAC4B4 0x00000006  ;# SDCKE1
 	mww 0x43FAC4B8 0x00000002  ;# SDCLK
-	
+
 	# SDQS0 through SDQS3
 	mww 0x43FAC4Bc 0x00000082
 	mww 0x43FAC4C0 0x00000082
 	mww 0x43FAC4C4 0x00000082
 	mww 0x43FAC4C8 0x00000082
-	
-	
+
+
 	# *==================================================
 	#  Initialization script for 32 bit DDR2 on RINGO 3DS
 	# *==================================================
-	
+
 	#--------------------------------------------
 	# Init CCM
 	#--------------------------------------------
 	mww 0x53F80028 0x7D000028
-	
+
 	#--------------------------------------------
 	# Init IOMUX for JTAG
 	#--------------------------------------------
@@ -164,24 +164,24 @@ proc imx35pdk_init { } {
 	mww 0x43FAC5FC 0x000000F3
 	mww 0x43FAC600 0x000000F3
 	mww 0x43FAC604 0x000000F3
-	
-	
+
+
 	# ESD_MISC : enable DDR2
 	mww 0xB8001010 0x00000304
-	
+
 	#--------------------------------------------
-	# Init 32-bit DDR2 memeory on CSD0
+	# Init 32-bit DDR2 memory on CSD0
 	# COL=10-bit, ROW=13-bit, BA[1:0]=Addr[26:25]
 	#--------------------------------------------
-	
-	# ESD_ESDCFG0 : set timing paramters
-	mww 0xB8001004 0x007ffC2f	
-	
+
+	# ESD_ESDCFG0 : set timing parameters
+	mww 0xB8001004 0x007ffC2f
+
 	# ESD_ESDCTL0 : select Prechare-All mode
 	mww 0xB8001000 0x92220000
 	# DDR2 : Prechare-All
 	mww 0x80000400 0x12345678
-	
+
 	# ESD_ESDCTL0 : select Load-Mode-Register mode
 	mww 0xB8001000 0xB2220000
 	# DDR2 : Load reg EMR2
@@ -192,18 +192,18 @@ proc imx35pdk_init { } {
 	mwb 0x82000400 0xda
 	# DDR2 : Load reg MR -- reset DLL
 	mwb 0x80000333 0xda
-	
+
 	# ESD_ESDCTL0 : select Prechare-All mode
 	mww 0xB8001000 0x92220000
 	# DDR2 : Prechare-All
 	mwb 0x80000400 0x12345678
-	
+
 	# ESD_ESDCTL0 : select Manual-Refresh mode
 	mww 0xB8001000 0xA2220000
 	# DDR2 : Manual-Refresh 2 times
 	mww 0x80000000 0x87654321
 	mww 0x80000000 0x87654321
-	
+
 	# ESD_ESDCTL0 : select Load-Mode-Register mode
 	mww 0xB8001000 0xB2220000
 	# DDR2 : Load reg MR -- CL=3, BL=8, end DLL reset
@@ -212,19 +212,19 @@ proc imx35pdk_init { } {
 	mwb 0x82000780 0xda
 	# DDR2 : Load reg EMR1 -- OCD exit
 	mwb 0x82000400 0xda	;# ODT disabled
-	
+
 	# ESD_ESDCTL0 : select normal-operation mode
 	# DSIZ=32-bit, BL=8, COL=10-bit, ROW=13-bit
 	# disable PWT & PRCT
 	# disable Auto-Refresh
 	mww 0xB8001000 0x82220080
-	
+
 	## ESD_ESDCTL0 : enable Auto-Refresh
 	mww 0xB8001000 0x82228080
 	## ESD_ESDCTL1 : enable Auto-Refresh
 	mww 0xB8001008 0x00002000
-	
-	
+
+
 	#***********************************************
 	# Adjust the ESDCDLY5 register
 	#***********************************************
@@ -233,20 +233,20 @@ proc imx35pdk_init { } {
 	mww 0xB8001024 0x00F48000	;# this is the default value
 	mww 0xB8001028 0x00F48000	;# this is the default value
 	mww 0xB800102c 0x00F48000	;# this is the default value
-	
-	
+
+
 	#Then you can make force measure with the dedicated bit (Bit 7 at ESDMISC)
 	mww 0xB8001010 0x00000384
 	# wait a while
 	sleep 1000
 	# now clear the force measurement bit
 	mww 0xB8001010 0x00000304
-	
+
 	# dummy write to DDR memory to set DQS low
 	mww 0x80000000 0x00000000
-	
+
 	mww 0x30000100 0x0
 	mww 0x30000104 0x31024
-	
-	
+
+
 }
diff --git a/tcl/board/imx53-m53evk.cfg b/tcl/board/imx53-m53evk.cfg
index eada27a..baeb3cd 100644
--- a/tcl/board/imx53-m53evk.cfg
+++ b/tcl/board/imx53-m53evk.cfg
@@ -18,10 +18,10 @@ echo "iMX53 M53EVK board lodaded."
 reset_config trst_and_srst separate trst_open_drain srst_open_drain
 
 # Run at 6 MHz
-adapter_khz 6000
+adapter speed 6000
 
 $_TARGETNAME configure -event "reset-assert" {
-	echo "Reseting ...."
+	echo "Resetting ...."
 	#cortex_a dbginit
 }
 
diff --git a/tcl/board/imx53loco.cfg b/tcl/board/imx53loco.cfg
index 06c3993..18caca5 100644
--- a/tcl/board/imx53loco.cfg
+++ b/tcl/board/imx53loco.cfg
@@ -13,7 +13,7 @@ echo "iMX53 Loco board lodaded."
 # Set reset type
 #reset_config srst_only
 
-adapter_khz 3000
+adapter speed 3000
 
 # Slow speed to be sure it will work
 jtag_rclk 1000
@@ -23,7 +23,7 @@ $_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
 #jtag_ntrst_delay 200
 
 $_TARGETNAME configure -event "reset-assert" {
-	echo "Reseting ...."
+	echo "Resetting ...."
 	#cortex_a dbginit
 }
 
@@ -59,7 +59,7 @@ proc loco_init { } {
 	arm core_state arm
 
 	jtag_rclk 3000
-#	adapter_khz 3000
+#	adapter speed 3000
 }
 
 
diff --git a/tcl/board/imx8mp-evk.cfg b/tcl/board/imx8mp-evk.cfg
new file mode 100644
index 0000000..97a303a
--- /dev/null
+++ b/tcl/board/imx8mp-evk.cfg
@@ -0,0 +1,15 @@
+#
+# configuration file for NXP MC-IMX8MP-EVK
+#
+# Board includes FTDI-based JTAG adapter: interface/ftdi/imx8mp-evk.cfg
+#
+
+transport select jtag
+adapter speed 1000
+reset_config srst_only
+adapter srst delay 100
+
+set CHIPNAME imx8mp
+set CHIPCORES 4
+
+source [find target/imx8m.cfg]
diff --git a/tcl/board/insignal_arndale.cfg b/tcl/board/insignal_arndale.cfg
index 25c123e..09a7223 100644
--- a/tcl/board/insignal_arndale.cfg
+++ b/tcl/board/insignal_arndale.cfg
@@ -5,4 +5,4 @@
 source [find target/exynos5250.cfg]
 
 # Experimentally determined highest working speed
-adapter_khz 200
+adapter speed 200
diff --git a/tcl/board/kasli.cfg b/tcl/board/kasli.cfg
index 2c5e268..06cc1e6 100644
--- a/tcl/board/kasli.cfg
+++ b/tcl/board/kasli.cfg
@@ -1,4 +1,4 @@
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Quad RS232-HS"
 ftdi_vid_pid 0x0403 0x6011
 ftdi_channel 0
@@ -7,7 +7,7 @@ ftdi_layout_init 0x0008 0x000b
 
 reset_config none
 transport select jtag
-adapter_khz 25000
+adapter speed 25000
 
 source [find cpld/xilinx-xc7.cfg]
 source [find cpld/jtagspi.cfg]
diff --git a/tcl/board/kc100.cfg b/tcl/board/kc100.cfg
new file mode 100644
index 0000000..1d383be
--- /dev/null
+++ b/tcl/board/kc100.cfg
@@ -0,0 +1,31 @@
+# Knovative KC-100 cable modem
+
+# TNETC4401PYP, 208-QFP U3
+source [find target/tnetc4401.cfg]
+
+# 14-pin EJTAG on JP1. Standard pinout, 1-3-5-7-9-11 = nTRST-TDI-TDO-TMS-TCK-nSRST. Use 2 for GND.
+# Was initially disabled in hardware; had to add a solder bridge reenabling R124, R125 on back.
+reset_config trst_and_srst separate
+
+# 16Mb Intel CFI flash. Note this CPU has an internal ROM at 0x1FC0000 (phys) for cold boot.
+# All that really does is some minimal checks before jumping to external flash at 0x00000000 phys.
+# That is remapped to 0xB0000000 uncached, 0x90000000 cached.
+flash bank intel cfi 0xB0000000 0x200000 2 2 $_TARGETNAME
+
+# Perform this after a clean reboot, halt, and reset init (which should also leave it halted).
+proc kc100_dump_flash {} {
+	echo "Probing 48 TSOP Intel CFI flash chip (2MB)..."
+	flash probe intel
+	echo "Dumping 2MB flash chip to flashdump.bin.
+	flash read_bank 0 flashdump.bin 0 0x200000
+}
+
+#TODO figure out memory init sequence to be able to dump from cached segment instead
+
+# There is also a serial console on JP2, 3-5-6 = TX-RX-GND. 9600/8/N/1.
+
+# Possibly of note, this modem's ancient ethernet port does not support Auto-MDIX.
+
+# This modem in many ways appears to be essentially a clone of the SB5120. See usbjtag.com.
+# The firmware/OS is also susceptible to many of the same procedures in "Hacking the Cable Modem"
+# by DerEngel (Ryan Harris), available from No Starch Press.
diff --git a/tcl/board/kc705.cfg b/tcl/board/kc705.cfg
index e032e9b..51ea14d 100644
--- a/tcl/board/kc705.cfg
+++ b/tcl/board/kc705.cfg
@@ -5,7 +5,7 @@ source [find cpld/xilinx-xc7.cfg]
 source [find cpld/jtagspi.cfg]
 source [find fpga/xilinx-xadc.cfg]
 source [find fpga/xilinx-dna.cfg]
-adapter_khz 25000
+adapter speed 25000
 
 # example command to write bitstream, soft-cpu bios and runtime:
 # openocd -f board/kc705.cfg -c "init;\
diff --git a/tcl/board/kcu105.cfg b/tcl/board/kcu105.cfg
index c8daea6..e2b68ca 100644
--- a/tcl/board/kcu105.cfg
+++ b/tcl/board/kcu105.cfg
@@ -8,4 +8,4 @@ source [find cpld/xilinx-xcu.cfg]
 
 source [find cpld/jtagspi.cfg]
 
-adapter_khz 25000
+adapter speed 25000
diff --git a/tcl/board/keil_mcb1700.cfg b/tcl/board/keil_mcb1700.cfg
index d63d3ed..05f12df 100644
--- a/tcl/board/keil_mcb1700.cfg
+++ b/tcl/board/keil_mcb1700.cfg
@@ -5,4 +5,3 @@
 #
 
 source [find target/lpc17xx.cfg]
-
diff --git a/tcl/board/keil_mcb2140.cfg b/tcl/board/keil_mcb2140.cfg
index db81efa..bb41a2a 100644
--- a/tcl/board/keil_mcb2140.cfg
+++ b/tcl/board/keil_mcb2140.cfg
@@ -5,4 +5,3 @@
 #
 
 source [find target/lpc2148.cfg]
-
diff --git a/tcl/board/kindle2.cfg b/tcl/board/kindle2.cfg
index f32b2a3..a39f15c 100644
--- a/tcl/board/kindle2.cfg
+++ b/tcl/board/kindle2.cfg
@@ -18,7 +18,7 @@ source [find target/imx31.cfg]
 source [find target/imx.cfg]
 
 $_TARGETNAME configure -event reset-init { kindle2_init }
-$_TARGETNAME configure -event reset-start { adapter_khz 1000 }
+$_TARGETNAME configure -event reset-start { adapter speed 1000 }
 
 # 8MiB NOR Flash
 set _FLASHNAME $_CHIPNAME.flash
@@ -36,7 +36,7 @@ jtag_ntrst_delay 30
 # this is broken but enabled by default
 arm11 memwrite burst disable
 
-adapter_khz 1000
+adapter speed 1000
 ftdi_tdo_sample_edge falling
 
 proc kindle2_init {} {
@@ -162,7 +162,7 @@ proc kindle2_sdram_init {} {
 	# LPDDR1 Initialization script
 	mww 0xb8001010 0x00000002
 	mww 0xb8001010 0x00000004
-	# ESDCFG0: set timing paramters
+	# ESDCFG0: set timing parameters
 	mww 0xb8001004 0x007fff7f
 	# ESDCTL0: select Prechare-All mode
 	mww 0xb8001000 0x92100000
diff --git a/tcl/board/linksys_nslu2.cfg b/tcl/board/linksys_nslu2.cfg
index e605fc1..0b0f58b 100644
--- a/tcl/board/linksys_nslu2.cfg
+++ b/tcl/board/linksys_nslu2.cfg
@@ -5,4 +5,3 @@ source [find target/ixp42x.cfg]
 # The _TARGETNAME is set by the above.
 
 $_TARGETNAME configure -work-area-phys 0x00020000 -work-area-size 0x10000 -work-area-backup 0
-
diff --git a/tcl/board/lubbock.cfg b/tcl/board/lubbock.cfg
index 298954c..d803e6f 100644
--- a/tcl/board/lubbock.cfg
+++ b/tcl/board/lubbock.cfg
@@ -4,7 +4,7 @@
 
 source [find target/pxa255.cfg]
 
-adapter_nsrst_delay 250
+adapter srst delay 250
 jtag_ntrst_delay 250
 
 # NOTE: until after pinmux and such are set up, only CS0 is
diff --git a/tcl/board/marsohod.cfg b/tcl/board/marsohod.cfg
index 681f575..b1393a9 100644
--- a/tcl/board/marsohod.cfg
+++ b/tcl/board/marsohod.cfg
@@ -6,7 +6,7 @@
 
 # Recommended MBFTDI programmer
 source [find interface/ftdi/mbftdi.cfg]
-adapter_khz 2000
+adapter speed 2000
 transport select jtag
 
 # Altera MAXII EPM240T100C CPLD
diff --git a/tcl/board/marsohod2.cfg b/tcl/board/marsohod2.cfg
index d4897c3..31819a2 100644
--- a/tcl/board/marsohod2.cfg
+++ b/tcl/board/marsohod2.cfg
@@ -6,7 +6,7 @@
 
 # Built-in MBFTDI programmer
 source [find interface/ftdi/mbftdi.cfg]
-adapter_khz 2000
+adapter speed 2000
 transport select jtag
 
 # Cyclone III EP3C10E144 FPGA
diff --git a/tcl/board/marsohod3.cfg b/tcl/board/marsohod3.cfg
index bb3c74f..fa00706 100644
--- a/tcl/board/marsohod3.cfg
+++ b/tcl/board/marsohod3.cfg
@@ -6,7 +6,7 @@
 
 # Built-in MBFTDI programmer
 source [find interface/ftdi/mbftdi.cfg]
-adapter_khz 2000
+adapter speed 2000
 transport select jtag
 
 # MAX10 10M50SAE144C8GES FPGA
diff --git a/tcl/board/mcb1700.cfg b/tcl/board/mcb1700.cfg
index 068a19b..01080a0 100644
--- a/tcl/board/mcb1700.cfg
+++ b/tcl/board/mcb1700.cfg
@@ -1,5 +1,5 @@
 # Keil MCB1700 PCB with 1768
-# 
+#
 # Reset init script sets it to 100MHz
 set CCLK 100000
 
@@ -11,7 +11,7 @@ set MCB1700_CCLK $CCLK
 $_TARGETNAME configure -event reset-start {
 	# Start *real slow* as we do not know the
     # state the boot rom left the clock in
-	adapter_khz 10
+	adapter speed 10
 }
 
 # Set up 100MHz clock to CPU
@@ -53,9 +53,9 @@ $_TARGETNAME configure -event reset-init {
 
 	# Dividing CPU clock by 8 should be pretty conservative
 	#
-	# 
+	#
 	global MCB1700_CCLK
-	adapter_khz [expr $MCB1700_CCLK / 8]
+	adapter speed [expr $MCB1700_CCLK / 8]
 
 	# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
 	# "User Flash Mode" where interrupt vectors are _not_ remapped,
diff --git a/tcl/board/microchip_same54_xplained_pro.cfg b/tcl/board/microchip_same54_xplained_pro.cfg
index db8a856..7482de4 100644
--- a/tcl/board/microchip_same54_xplained_pro.cfg
+++ b/tcl/board/microchip_same54_xplained_pro.cfg
@@ -10,4 +10,3 @@ set CHIPNAME same54
 source [find target/atsame5x.cfg]
 
 reset_config srst_only
-
diff --git a/tcl/board/microchip_saml11_xplained_pro.cfg b/tcl/board/microchip_saml11_xplained_pro.cfg
index 3558a8e..2ab6111 100644
--- a/tcl/board/microchip_saml11_xplained_pro.cfg
+++ b/tcl/board/microchip_saml11_xplained_pro.cfg
@@ -4,7 +4,7 @@
 #
 
 source [find interface/cmsis-dap.cfg]
-adapter_khz 1000
+adapter speed 1000
 
 set CHIPNAME saml11
 source [find target/atsaml1x.cfg]
diff --git a/tcl/board/mini2440.cfg b/tcl/board/mini2440.cfg
index 874f829..9dca5a3 100644
--- a/tcl/board/mini2440.cfg
+++ b/tcl/board/mini2440.cfg
@@ -111,7 +111,7 @@ target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
 $_TARGETNAME configure -work-area-phys 0x40000000  -work-area-size 0x4000 -work-area-backup 1
 
 #reset configuration
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 reset_config trst_and_srst
 
@@ -120,7 +120,7 @@ reset_config trst_and_srst
 # IMPORTANT! See README at top of this file.
 #-------------------------------------------------------------------------
 
-    adapter_khz 12000
+    adapter speed 12000
     jtag interface
 
 #-------------------------------------------------------------------------
@@ -140,7 +140,7 @@ reset_config trst_and_srst
 
     nand device s3c2440 0
 
-    adapter_nsrst_delay 100
+    adapter srst delay 100
     jtag_ntrst_delay 100
     reset_config trst_and_srst
     init
diff --git a/tcl/board/mini6410.cfg b/tcl/board/mini6410.cfg
index d00ce1f..2cee939 100644
--- a/tcl/board/mini6410.cfg
+++ b/tcl/board/mini6410.cfg
@@ -88,8 +88,8 @@ proc init_6410_flash {} {
 }
 
 
-adapter_khz 1000
-adapter_nsrst_delay 100
+adapter speed 1000
+adapter srst delay 100
 jtag_ntrst_delay 100
 reset_config trst_and_srst
 
diff --git a/tcl/board/novena-internal-fpga.cfg b/tcl/board/novena-internal-fpga.cfg
index 87495e3..0e9ff5b 100644
--- a/tcl/board/novena-internal-fpga.cfg
+++ b/tcl/board/novena-internal-fpga.cfg
@@ -14,7 +14,7 @@
 # | DISP0_DAT17 | FPGA_TMS     | 5-11 |  139  | TMS     |
 # +-------------+--------------+------+-------+---------+
 
-interface sysfsgpio
+adapter driver sysfsgpio
 
 transport select jtag
 
@@ -22,4 +22,3 @@ transport select jtag
 sysfsgpio_jtag_nums 136 139 137 138
 
 source [find cpld/xilinx-xc6s.cfg]
-
diff --git a/tcl/board/numato_mimas_a7.cfg b/tcl/board/numato_mimas_a7.cfg
index 1261fea..d4012ba 100644
--- a/tcl/board/numato_mimas_a7.cfg
+++ b/tcl/board/numato_mimas_a7.cfg
@@ -7,7 +7,7 @@
 #       Programming while powering via USB may lead to programming failure.
 #       Therefore, prefer external power supply.
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Mimas Artix 7 FPGA Module"
 ftdi_vid_pid 0x2a19 0x1009
 
@@ -30,7 +30,7 @@ ftdi_tdo_sample_edge falling
 #
 ftdi_layout_init 0x0008 0x004b
 reset_config none
-adapter_khz 30000
+adapter speed 30000
 
 source [find cpld/xilinx-xc7.cfg]
 source [find cpld/jtagspi.cfg]
diff --git a/tcl/board/nxp_imx7sabre.cfg b/tcl/board/nxp_imx7sabre.cfg
index 25b7b87..c595e3a 100644
--- a/tcl/board/nxp_imx7sabre.cfg
+++ b/tcl/board/nxp_imx7sabre.cfg
@@ -3,12 +3,12 @@
 transport select jtag
 
 # set a safe speed, can be overridden
-adapter_khz 1000
+adapter speed 1000
 
 # reset configuration has TRST and SRST support
 reset_config trst_and_srst srst_push_pull
 # need at least 100ms delay after SRST release for JTAG
-adapter_nsrst_delay 100
+adapter srst delay 100
 
 # source the target file
 source [find target/imx7.cfg]
diff --git a/tcl/board/nxp_mcimx8m-evk.cfg b/tcl/board/nxp_mcimx8m-evk.cfg
index e2d63ce..dd9bd53 100644
--- a/tcl/board/nxp_mcimx8m-evk.cfg
+++ b/tcl/board/nxp_mcimx8m-evk.cfg
@@ -6,13 +6,13 @@
 transport select jtag
 
 # set a safe JTAG clock speed, can be overridden
-adapter_khz 1000
+adapter speed 1000
 
 # default JTAG configuration has only SRST and no TRST
 reset_config srst_only srst_push_pull
 
 # delay after SRST goes inactive
-adapter_nsrst_delay 70
+adapter srst delay 70
 
 # board has an i.MX8MQ with 4 Cortex-A53 cores
 set CHIPNAME imx8mq
diff --git a/tcl/board/olimex_LPC2378STK.cfg b/tcl/board/olimex_LPC2378STK.cfg
index a4b422d..7e9e58e 100644
--- a/tcl/board/olimex_LPC2378STK.cfg
+++ b/tcl/board/olimex_LPC2378STK.cfg
@@ -8,4 +8,3 @@
 #
 
 source [find target/lpc2378.cfg]
-
diff --git a/tcl/board/olimex_lpc_h2148.cfg b/tcl/board/olimex_lpc_h2148.cfg
index 7833fde..d8fb5be 100644
--- a/tcl/board/olimex_lpc_h2148.cfg
+++ b/tcl/board/olimex_lpc_h2148.cfg
@@ -5,4 +5,3 @@
 #
 
 source [find target/lpc2148.cfg]
-
diff --git a/tcl/board/olimex_sam7_ex256.cfg b/tcl/board/olimex_sam7_ex256.cfg
index 5f83629..426ead6 100644
--- a/tcl/board/olimex_sam7_ex256.cfg
+++ b/tcl/board/olimex_sam7_ex256.cfg
@@ -1,4 +1,3 @@
 # Olimex SAM7-EX256 has a single Atmel at91sam7ex256 on it.
 
 source [find target/sam7x256.cfg]
-
diff --git a/tcl/board/olimex_sam7_la2.cfg b/tcl/board/olimex_sam7_la2.cfg
index 89d2b5a..038fe67 100644
--- a/tcl/board/olimex_sam7_la2.cfg
+++ b/tcl/board/olimex_sam7_la2.cfg
@@ -2,7 +2,7 @@ source [find target/at91sam7a2.cfg]
 
 # delays needed to get stable reads of cpu state
 jtag_ntrst_delay 10
-adapter_nsrst_delay 200
+adapter srst delay 200
 
 # board uses pullup and connects only srst
 reset_config srst_open_drain
@@ -10,9 +10,9 @@ reset_config srst_open_drain
 # srst is connected to NRESET of CPU and fully resets everything...
 reset_config srst_only srst_pulls_trst
 
-adapter_khz 1
+adapter speed 1
 $_TARGETNAME configure -event reset-start {
-	adapter_khz 1
+	adapter speed 1
 }
 
 $_TARGETNAME configure -event reset-init {
@@ -61,7 +61,7 @@ $_TARGETNAME configure -event reset-init {
 	echo "set up pll"
 
 	sleep 100
-	adapter_khz 5000
+	adapter speed 5000
 }
 
 $_TARGETNAME arm7_9 dcc_downloads enable
diff --git a/tcl/board/olimex_sam9_l9260.cfg b/tcl/board/olimex_sam9_l9260.cfg
index ad2f850..72dce87 100644
--- a/tcl/board/olimex_sam9_l9260.cfg
+++ b/tcl/board/olimex_sam9_l9260.cfg
@@ -23,15 +23,15 @@ $_TARGETNAME configure -event reset-start {
 	# RCLK is not supported.
 	jtag_rclk 5
 	halt
-	
-	# RSTC_MR : enable user reset, reset length is 64 slow clock cycles.  MMU may 
+
+	# RSTC_MR : enable user reset, reset length is 64 slow clock cycles.  MMU may
 	# be enabled... use physical address.
 	mww phys 0xfffffd08 0xa5000501
 }
 
 $_TARGETNAME configure -event reset-init {
 	mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
-	
+
 	##
 	# Clock configuration for 99.328 MHz main clock.
 	##
@@ -45,23 +45,23 @@ $_TARGETNAME configure -event reset-init {
 	mww 0xfffffc30 0x00000101 ;# PMC_MCKR : no scale on proc clock, master is proc / 2
 	sleep 10                  ;# wait 10 ms
 	mww 0xfffffc30 0x00000102 ;# PMC_MCKR : switch to PLLA (99.328 MHz)
-	
+
 	# Increase JTAG speed to 6 MHz if RCLK is not supported.
 	jtag_rclk 6000
-	
+
 	arm7_9 dcc_downloads enable ;# Enable faster DCC downloads.
-	
+
 	##
 	# SDRAM configuration for 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks.
 	##
     echo "Configuring SDRAM"
 	mww 0xfffff870 0xffff0000 ;# PIOC_ASR : select peripheral function for D15..D31
 	mww 0xfffff804 0xffff0000 ;# PIOC_PDR : disable PIO function for D15..D31
-	
+
 	mww 0xffffef1c 0x00010002 ;# EBI_CSA : assign EBI CS1 to SDRAM, VDDIOMSEL set for +3V3 memory
-	
+
 	mww 0xffffea08 0x85237259 ;# SDRAMC_CR : configure SDRAM for Samsung chips
-	
+
 	mww 0xffffea00 0x1        ;# SDRAMC_MR : issue NOP command
 	mww 0x20000000 0
 	mww 0xffffea00 0x2        ;# SDRAMC_MR : issue an 'All Banks Precharge' command
@@ -86,7 +86,7 @@ $_TARGETNAME configure -event reset-init {
 	mww 0x20000000 0
 	mww 0xffffea00 0x0        ;# SDRAMC_MR : normal mode
 	mww 0x20000000 0
-	
+
 	mww 0xffffea04 0x2b6      ;# SDRAMC_TR : set refresh timer count to 7 us
 
     ##
@@ -99,37 +99,37 @@ $_TARGETNAME configure -event reset-init {
     mww 0xfffff814 0x00002000 ;# PIOC_ODR : disable output on 13
     mww 0xfffff830 0x00004000 ;# PIOC_SODR : set 14 to disable NAND
     mww 0xfffff864 0x00002000 ;# PIOC_PUER : enable pull-up on 13
-    
+
     mww 0xffffef1c 0x0001000A ;# EBI_CSA : assign EBI CS3 to NAND, same settings as before
-    
+
     mww 0xffffec30 0x00010001 ;# SMC_SETUP3 : 1 clock cycle setup for NRD and NWE
     mww 0xffffec34 0x03030303 ;# SMC_PULSE3 : 3 clock cycle pulse for all signals
     mww 0xffffec38 0x00050005 ;# SMC_CYCLE3 : 5 clock cycle NRD and NWE cycle
-    mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW, 
+    mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
                                #             3 TDF cycles, no optimization
-    
+
     mww 0xffffe800 0x00000001 ;# ECC_CR : reset the ECC parity registers
     mww 0xffffe804 0x00000002 ;# ECC_MR : page size is 2112 words (word is 8 bits)
-    
+
     nand probe at91sam9260.flash
-    
+
     ##
     # Dataflash configuration for 1 x Atmel AT45DB161D, 16Mbit
     ##
     echo "Setting up dataflash"
-    mww 0xfffff404 0x00000807 ;# PIOA_PDR : disable PIO function for 0(SPI0_MISO), 1(SPI0_MOSI), 
+    mww 0xfffff404 0x00000807 ;# PIOA_PDR : disable PIO function for 0(SPI0_MISO), 1(SPI0_MOSI),
                                #            2(SPI0_SPCK), and 11(SPI0_NPCS1)
     mww 0xfffff470 0x00000007 ;# PIOA_ASR : select peripheral A function for 0, 1, and 2
     mww 0xfffff474 0x00000800 ;# PIOA_BSR : select peripheral B function for 11
     mww 0xfffffc10 0x00001000 ;# PMC_PCER : enable SPI0 clock
-    
+
     mww 0xfffc8000 0x00000080 ;# SPI0_CR : software reset SPI0
     mww 0xfffc8000 0x00000080 ;# SPI0_CR : again to be sure
     mww 0xfffc8004 0x000F0011 ;# SPI0_MR : master mode with nothing selected
-    
-    mww 0xfffc8034 0x011a0302 ;# SPI0_CSR1 : capture on leading edge, 8-bits/tx. 33MHz baud, 
+
+    mww 0xfffc8034 0x011a0302 ;# SPI0_CSR1 : capture on leading edge, 8-bits/tx. 33MHz baud,
                                #             250ns delay before SPCK, 250ns b/n tx
-    
+
     mww 0xfffc8004 0x000D0011 ;# SPI0_MR : same config, select NPCS1
     mww 0xfffc8000 0x00000001 ;# SPI0_CR : enable SPI0
 }
diff --git a/tcl/board/openrd.cfg b/tcl/board/openrd.cfg
index db3cb03..fda01d1 100644
--- a/tcl/board/openrd.cfg
+++ b/tcl/board/openrd.cfg
@@ -3,7 +3,7 @@
 source [find interface/ftdi/openrd.cfg]
 source [find target/feroceon.cfg]
 
-adapter_khz 2000
+adapter speed 2000
 
 $_TARGETNAME configure \
 	-work-area-phys 0x10000000 \
@@ -25,10 +25,10 @@ proc openrd_init { } {
 	# possible that initial tap examination failed.  So let's
 	# re-examine the target again here when nSRST is asserted which
 	# should then succeed.
-	jtag_reset 0 1
+	adapter assert srst
 	feroceon.cpu arp_examine
 	halt 0
-	jtag_reset 0 0
+	adapter deassert srst
 	wait_halt
 
 	arm mcr 15 0 0 1 0 0x00052078
@@ -122,4 +122,3 @@ proc openrd_load_uboot { } {
 	resume 0x00600000
 
 }
-
diff --git a/tcl/board/or1k_generic.cfg b/tcl/board/or1k_generic.cfg
index c543ebe..7c19565 100644
--- a/tcl/board/or1k_generic.cfg
+++ b/tcl/board/or1k_generic.cfg
@@ -17,7 +17,7 @@ source [find target/or1k.cfg]
 poll_period 1
 
 # Set the adapter speed
-adapter_khz 3000
+adapter speed 3000
 
 # Enable the target description feature
 gdb_target_description enable
diff --git a/tcl/board/phone_se_j100i.cfg b/tcl/board/phone_se_j100i.cfg
index 6326590..ec61425 100644
--- a/tcl/board/phone_se_j100i.cfg
+++ b/tcl/board/phone_se_j100i.cfg
@@ -1,7 +1,7 @@
 #
 # Sony Ericsson J100I Phone
 #
-# more informations can be found on
+# more information can be found on
 # http://bb.osmocom.org/trac/wiki/SonyEricssonJ100i
 #
 source [find target/ti_calypso.cfg]
diff --git a/tcl/board/phytec_lpc3250.cfg b/tcl/board/phytec_lpc3250.cfg
index 6a7e8e9..cee28cd 100644
--- a/tcl/board/phytec_lpc3250.cfg
+++ b/tcl/board/phytec_lpc3250.cfg
@@ -1,8 +1,8 @@
 source [find target/lpc3250.cfg]
 
-adapter_nsrst_delay 200
+adapter srst delay 200
 jtag_ntrst_delay 1
-adapter_khz 200
+adapter speed 200
 reset_config trst_and_srst separate
 
 arm7_9 dcc_downloads enable
@@ -11,11 +11,11 @@ $_TARGETNAME configure -event gdb-attach { reset init }
 
 $_TARGETNAME configure -event reset-start {
              arm7_9 fast_memory_access disable
-             adapter_khz 200
+             adapter speed 200
 }
 
 $_TARGETNAME configure -event reset-end {
-             adapter_khz 6000
+             adapter speed 6000
              arm7_9 fast_memory_access enable
 }
 
@@ -23,12 +23,12 @@ $_TARGETNAME configure -event reset-init { phytec_lpc3250_init }
 
 # Bare-bones initialization of core clocks and SDRAM
 proc phytec_lpc3250_init { } {
-        # Set clock dividers 
+        # Set clock dividers
         #   ARMCLK = 266.5 MHz
         #   HCLK   = 133.25 MHz
         #   PERIPHCLK = 13.325 MHz
         mww 0x400040BC 0
-        mww 0x40004050 0x140        
+        mww 0x40004050 0x140
         mww 0x40004040 0x4D
         mww 0x40004058 0x16250
 
@@ -37,7 +37,7 @@ proc phytec_lpc3250_init { } {
         sleep 1 busy
         mww 0x40004044 0x106
         sleep 1 busy
-        mww 0x40004044 0x006        
+        mww 0x40004044 0x006
         sleep 1 busy
         mww 0x40004048 0x2
 
@@ -49,7 +49,7 @@ proc phytec_lpc3250_init { } {
         mww 0x31080008 0
         mww 0x40004068 0x1C000
         mww 0x31080028 0x11
-        
+
         mww 0x31080400 0
         mww 0x31080440 0
         mww 0x31080460 0
@@ -66,7 +66,7 @@ proc phytec_lpc3250_init { } {
         mww 0x31080054 1
         mww 0x31080058 1
         mww 0x3108005C 0
-        
+
         mww 0x31080100 0x5680
         mww 0x31080104 0x302
 
diff --git a/tcl/board/pxa255_sst.cfg b/tcl/board/pxa255_sst.cfg
index 49cad5d..2b44a05 100644
--- a/tcl/board/pxa255_sst.cfg
+++ b/tcl/board/pxa255_sst.cfg
@@ -93,7 +93,7 @@ $_TARGETNAME configure -event reset-init {pxa255_sst_init}
 
 reset_config trst_and_srst
 
-adapter_nsrst_delay 200
+adapter srst delay 200
 jtag_ntrst_delay 200
 
 #xscale debug_handler 0  0xFFFF0800      ;# debug handler base address
diff --git a/tcl/board/quark_d2000_refboard.cfg b/tcl/board/quark_d2000_refboard.cfg
index d1388bb..8b8314a 100644
--- a/tcl/board/quark_d2000_refboard.cfg
+++ b/tcl/board/quark_d2000_refboard.cfg
@@ -1,7 +1,7 @@
 # Intel Quark microcontroller D2000 Reference Board (web search for doc num 333582)
 
 # the board has an onboard FTDI FT232H chip
-interface ftdi
+adapter driver ftdi
 ftdi_vid_pid 0x0403 0x6014
 ftdi_channel 0
 
@@ -10,6 +10,6 @@ ftdi_layout_signal nTRST -data 0x0100 -noe 0x0100
 
 source [find target/quark_d20xx.cfg]
 
-adapter_khz 1000
+adapter speed 1000
 
 reset_config trst_only
diff --git a/tcl/board/quark_x10xx_board.cfg b/tcl/board/quark_x10xx_board.cfg
index 8dc600b..4ecf30e 100644
--- a/tcl/board/quark_x10xx_board.cfg
+++ b/tcl/board/quark_x10xx_board.cfg
@@ -4,6 +4,6 @@
 source [find target/quark_x10xx.cfg]
 
 #default frequency but this can be adjusted at runtime
-adapter_khz 4000
+adapter speed 4000
 
 reset_config trst_only
diff --git a/tcl/board/renesas_porter.cfg b/tcl/board/renesas_porter.cfg
index c8032f5..7f23fb6 100644
--- a/tcl/board/renesas_porter.cfg
+++ b/tcl/board/renesas_porter.cfg
@@ -1,4 +1,4 @@
 # Renesas R-Car M2 Evaluation Board
 
-source [find target/renesas_r8a7791.cfg]
-source [find board/renesas_gen2_common.cfg]
+set SOC M2
+source [find target/renesas_rcar_gen2.cfg]
diff --git a/tcl/board/renesas_salvator-xs.cfg b/tcl/board/renesas_salvator-xs.cfg
index 1558a52..6d3096e 100644
--- a/tcl/board/renesas_salvator-xs.cfg
+++ b/tcl/board/renesas_salvator-xs.cfg
@@ -7,17 +7,3 @@ if { ![info exists SOC] } {
 	set SOC H3
 }
 source [find target/renesas_rcar_gen3.cfg]
-
-reset_config trst_and_srst srst_nogate
-
-proc init_reset {mode} {
-	# Assert both resets: equivalent to a power-on reset
-	jtag_reset 1 1
-
-	# Deassert TRST to begin TAP communication
-	jtag_reset 0 1
-
-	# TAP should now be responsive, validate the scan-chain
-	jtag arp_init
-}
-
diff --git a/tcl/board/renesas_silk.cfg b/tcl/board/renesas_silk.cfg
index a026537..08bcb66 100644
--- a/tcl/board/renesas_silk.cfg
+++ b/tcl/board/renesas_silk.cfg
@@ -1,4 +1,4 @@
 # Renesas R-Car E2 Evaluation Board
 
-source [find target/renesas_r8a7794.cfg]
-source [find board/renesas_gen2_common.cfg]
+set SOC E2
+source [find target/renesas_rcar_gen2.cfg]
diff --git a/tcl/board/renesas_stout.cfg b/tcl/board/renesas_stout.cfg
index d35f874..51b53e1 100644
--- a/tcl/board/renesas_stout.cfg
+++ b/tcl/board/renesas_stout.cfg
@@ -1,4 +1,4 @@
 # Renesas R-Car H2 Evaluation Board
 
-source [find target/renesas_r8a7790.cfg]
-source [find board/renesas_gen2_common.cfg]
+set SOC H2
+source [find target/renesas_rcar_gen2.cfg]
diff --git a/tcl/board/rigado_bmd300_ek.cfg b/tcl/board/rigado_bmd300_ek.cfg
index 04e5e1f..8e1e65e 100644
--- a/tcl/board/rigado_bmd300_ek.cfg
+++ b/tcl/board/rigado_bmd300_ek.cfg
@@ -6,6 +6,6 @@
 
 source [find interface/jlink.cfg]
 transport select swd
-adapter_khz 1000
+adapter speed 1000
 
 source [find target/nrf52.cfg]
diff --git a/tcl/board/rsc-w910.cfg b/tcl/board/rsc-w910.cfg
index 636a053..574de0c 100644
--- a/tcl/board/rsc-w910.cfg
+++ b/tcl/board/rsc-w910.cfg
@@ -12,8 +12,8 @@ source [find target/nuc910.cfg]
 #
 reset_config trst_and_srst srst_pulls_trst
 
-adapter_khz 1000
-adapter_nsrst_delay 100
+adapter speed 1000
+adapter srst delay 100
 jtag_ntrst_delay 100
 
 $_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x04000000 -work-area-backup 0
@@ -28,12 +28,12 @@ nand device $_NANDNAME nuc910 $_TARGETNAME
 # Target events
 #
 
-$_TARGETNAME configure -event reset-start {adapter_khz 1000}
+$_TARGETNAME configure -event reset-start {adapter speed 1000}
 
 $_TARGETNAME configure -event reset-init {
 	# switch on PLL for 200MHz operation
 	# running from 15MHz input clock
-	
+
 	mww 0xB0000200 0x00000030 ;# CLKEN
 	mww 0xB0000204 0x00000f3c ;# CLKSEL
 	mww 0xB0000208 0x05007000 ;# CLKDIV
@@ -41,17 +41,17 @@ $_TARGETNAME configure -event reset-init {
 	mww 0xB0000210 0x00002b63 ;# PLLCON1
 	mww 0xB000000C 0x08817fa6 ;# MFSEL
 	sleep 10
-	
+
 	# we are now running @ 200MHz
 	# enable all openocd speed tweaks
-	
+
 	arm7_9 dcc_downloads enable
 	arm7_9 fast_memory_access enable
-	adapter_khz 15000
-	
+	adapter speed 15000
+
 	# map nor flash to 0x20000000
 	# map sdram to 0x00000000
-	
+
 	mww 0xb0001000 0x000530c1 ;# EBICON
 	mww 0xb0001004 0x40030084 ;# ROMCON
 	mww 0xb0001008 0x000010ee ;# SDCONF0
diff --git a/tcl/board/sayma_amc.cfg b/tcl/board/sayma_amc.cfg
index 5d338ed..009eb78 100644
--- a/tcl/board/sayma_amc.cfg
+++ b/tcl/board/sayma_amc.cfg
@@ -10,7 +10,7 @@
 # Sayma AMC is usually combined with Sayma RTM (rear transition module)
 # which features an Artix 7 FPGA.
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Quad RS232-HS"
 ftdi_vid_pid 0x0403 0x6011
 ftdi_channel 0
@@ -26,7 +26,7 @@ ftdi_layout_init 0x0098 0x008b
 #ftdi_layout_signal nTRST -data 0x0010
 reset_config none
 
-adapter_khz 5000
+adapter speed 5000
 
 transport select jtag
 
diff --git a/tcl/board/sheevaplug.cfg b/tcl/board/sheevaplug.cfg
index ff333ca..4551637 100644
--- a/tcl/board/sheevaplug.cfg
+++ b/tcl/board/sheevaplug.cfg
@@ -3,7 +3,7 @@
 source [find interface/ftdi/sheevaplug.cfg]
 source [find target/feroceon.cfg]
 
-adapter_khz 2000
+adapter speed 2000
 
 $_TARGETNAME configure \
 	-work-area-phys 0x10000000 \
@@ -25,10 +25,10 @@ proc sheevaplug_init { } {
 	# possible that initial tap examination failed.  So let's
 	# re-examine the target again here when nSRST is asserted which
 	# should then succeed.
-	jtag_reset 0 1
+	adapter assert srst
 	feroceon.cpu arp_examine
 	halt 0
-	jtag_reset 0 0
+	adapter deassert srst
 	wait_halt
 
 	arm mcr 15 0 0 1 0 0x00052078
@@ -133,4 +133,3 @@ proc sheevaplug_load_uboot { } {
 	resume 0x00600000
 
 }
-
diff --git a/tcl/board/sifive-e31arty.cfg b/tcl/board/sifive-e31arty.cfg
index ec10b27..b7a255e 100644
--- a/tcl/board/sifive-e31arty.cfg
+++ b/tcl/board/sifive-e31arty.cfg
@@ -1,7 +1,7 @@
 #
 # Be sure you include the speed and interface before this file
 # Example:
-# -c "adapter_khz 5000" -f "interface/ftdi/olimex-arm-usb-tiny-h.cfg" -f "board/sifive-e31arty.cfg"
+# -c "adapter speed 5000" -f "interface/ftdi/olimex-arm-usb-tiny-h.cfg" -f "board/sifive-e31arty.cfg"
 
 set _CHIPNAME riscv
 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
diff --git a/tcl/board/sifive-e51arty.cfg b/tcl/board/sifive-e51arty.cfg
index ffd83a0..20ad575 100644
--- a/tcl/board/sifive-e51arty.cfg
+++ b/tcl/board/sifive-e51arty.cfg
@@ -1,7 +1,7 @@
 #
 # Be sure you include the speed and interface before this file
 # Example:
-# -c "adapter_khz 5000" -f "interface/ftdi/olimex-arm-usb-tiny-h.cfg" -f "board/sifive-e51arty.cfg"
+# -c "adapter speed 5000" -f "interface/ftdi/olimex-arm-usb-tiny-h.cfg" -f "board/sifive-e51arty.cfg"
 
 set _CHIPNAME riscv
 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
diff --git a/tcl/board/sifive-hifive1-revb.cfg b/tcl/board/sifive-hifive1-revb.cfg
index 662811f..7f2a212 100644
--- a/tcl/board/sifive-hifive1-revb.cfg
+++ b/tcl/board/sifive-hifive1-revb.cfg
@@ -1,6 +1,6 @@
-adapter_khz 4000
+adapter speed 4000
 
-interface jlink
+adapter driver jlink
 transport select jtag
 
 set _CHIPNAME riscv
diff --git a/tcl/board/sifive-hifive1.cfg b/tcl/board/sifive-hifive1.cfg
index 9bc6670..196f540 100644
--- a/tcl/board/sifive-hifive1.cfg
+++ b/tcl/board/sifive-hifive1.cfg
@@ -1,6 +1,6 @@
-adapter_khz     10000
+adapter speed     10000
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Dual RS232-HS"
 ftdi_vid_pid 0x0403 0x6010
 
@@ -10,7 +10,7 @@ ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
 #Reset Stretcher logic on FE310 is ~1 second long
 #This doesn't apply if you use
 # ftdi_set_signal, but still good to document
-#adapter_nsrst_delay 1500
+#adapter srst delay 1500
 
 set _CHIPNAME riscv
 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
diff --git a/tcl/board/snps_em_sk.cfg b/tcl/board/snps_em_sk.cfg
new file mode 100644
index 0000000..3d93407
--- /dev/null
+++ b/tcl/board/snps_em_sk.cfg
@@ -0,0 +1,22 @@
+#  Copyright (C) 2014-2016,2020 Synopsys, Inc.
+#  Anton Kolesov <anton.kolesov@synopsys.com>
+#  Didin Evgeniy <didin@synopsys.com>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Synopsys DesignWare ARC EM Starter Kit v2.x
+#
+
+# Configure JTAG cable
+# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.
+source [find interface/ftdi/digilent-hs1.cfg]
+
+# 5MHz seems to work good with all cores that might happen in 2.x
+adapter speed 5000
+
+# ARCs support only JTAG.
+transport select jtag
+
+# Configure FPGA. This script supports both LX45 and LX150.
+source [find target/snps_em_sk_fpga.cfg]
diff --git a/tcl/board/snps_em_sk_v1.cfg b/tcl/board/snps_em_sk_v1.cfg
new file mode 100644
index 0000000..0c1539e
--- /dev/null
+++ b/tcl/board/snps_em_sk_v1.cfg
@@ -0,0 +1,20 @@
+#  Copyright (C) 2014-2016,2020 Synopsys, Inc.
+#  Anton Kolesov <anton.kolesov@synopsys.com>
+#  Didin Evgeniy <didin@synopsys.com>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Synopsys DesignWare ARC EM Starter Kit v1.0 and v1.1
+#
+
+# Configure JTAG cable
+# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.
+source [find interface/ftdi/digilent-hs1.cfg]
+adapter speed 10000
+
+# ARCs support only JTAG.
+transport select jtag
+
+# Configure FPGA. This script supports both LX45 and LX150.
+source [find target/snps_em_sk_fpga.cfg]
diff --git a/tcl/board/snps_em_sk_v2.1.cfg b/tcl/board/snps_em_sk_v2.1.cfg
new file mode 100644
index 0000000..c1fb232
--- /dev/null
+++ b/tcl/board/snps_em_sk_v2.1.cfg
@@ -0,0 +1,23 @@
+#  Copyright (C) 2014-2016,2020 Synopsys, Inc.
+#  Anton Kolesov <anton.kolesov@synopsys.com>
+#  Didin Evgeniy <didin@synopsys.com>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Synopsys DesignWare ARC EM Starter Kit v2.1
+#
+
+# Configure JTAG cable
+# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.
+source [find interface/ftdi/digilent-hs1.cfg]
+
+# JTAG 10MHz is too fast for EM7D FPU in EM SK 2.1 which has core frequency
+# 20MHz. 7.5 MHz seems to work fine.
+adapter speed 7500
+
+# ARCs support only JTAG.
+transport select jtag
+
+# Configure FPGA. This script supports both LX45 and LX150.
+source [find target/snps_em_sk_fpga.cfg]
diff --git a/tcl/board/snps_em_sk_v2.2.cfg b/tcl/board/snps_em_sk_v2.2.cfg
new file mode 100644
index 0000000..674d9f6
--- /dev/null
+++ b/tcl/board/snps_em_sk_v2.2.cfg
@@ -0,0 +1,22 @@
+#  Copyright (C) 2016,2020 Synopsys, Inc.
+#  Anton Kolesov <anton.kolesov@synopsys.com>
+#  Didin Evgeniy <didin@synopsys.com>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Synopsys DesignWare ARC EM Starter Kit v2.2
+#
+
+# Configure JTAG cable
+# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.
+source [find interface/ftdi/digilent-hs1.cfg]
+
+# EM11D reportedly requires 5 MHz. Other cores and board can work faster.
+adapter speed 5000
+
+# ARCs support only JTAG.
+transport select jtag
+
+# Configure FPGA. This script supports both LX45 and LX150.
+source [find target/snps_em_sk_fpga.cfg]
diff --git a/tcl/board/st_nucleo_8l152r8.cfg b/tcl/board/st_nucleo_8l152r8.cfg
new file mode 100644
index 0000000..d337269
--- /dev/null
+++ b/tcl/board/st_nucleo_8l152r8.cfg
@@ -0,0 +1,10 @@
+# This is a ST NUCLEO 8L152R8 board with a single STM8L152R8T6 chip.
+# http://www.st.com/en/evaluation-tools/nucleo-8l152r8.html
+
+source [find interface/stlink-dap.cfg]
+
+transport select swim
+
+source [find target/stm8l152.cfg]
+
+reset_config srst_only
diff --git a/tcl/board/st_nucleo_h745zi.cfg b/tcl/board/st_nucleo_h745zi.cfg
new file mode 100644
index 0000000..22d36f6
--- /dev/null
+++ b/tcl/board/st_nucleo_h745zi.cfg
@@ -0,0 +1,14 @@
+# This is an ST NUCLEO-H745ZI-Q board with single STM32H745ZITx chip.
+
+source [find interface/stlink-dap.cfg]
+transport select dapdirect_swd
+
+# STM32H745xx devices are dual core (Cortex-M7 and Cortex-M4)
+set DUAL_CORE 1
+
+# enable CTI for cross halting both cores
+set USE_CTI 1
+
+source [find target/stm32h7x_dual_bank.cfg]
+
+reset_config srst_only
diff --git a/tcl/board/st_nucleo_wb55.cfg b/tcl/board/st_nucleo_wb55.cfg
new file mode 100644
index 0000000..5b5b8f7
--- /dev/null
+++ b/tcl/board/st_nucleo_wb55.cfg
@@ -0,0 +1,11 @@
+#
+# Configuration for STM32WB55 Nucleo board (STM32WB55RGV6)
+#
+
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+source [find target/stm32wbx.cfg]
+
+reset_config srst_only
diff --git a/tcl/board/steval-idb011v1.cfg b/tcl/board/steval-idb011v1.cfg
new file mode 100644
index 0000000..5988c63
--- /dev/null
+++ b/tcl/board/steval-idb011v1.cfg
@@ -0,0 +1,3 @@
+# This is an evaluation board with a single BlueNRG-LP chip.
+set CHIPNAME bluenrg-lp
+source [find target/bluenrg-x.cfg]
diff --git a/tcl/board/steval_pcc010.cfg b/tcl/board/steval_pcc010.cfg
index ddfdbb3..94108d1 100644
--- a/tcl/board/steval_pcc010.cfg
+++ b/tcl/board/steval_pcc010.cfg
@@ -1,5 +1,5 @@
 # Use for the STM207VG plug-in board (1 MiB Flash and 112+16 KiB Ram
-# comming with the STEVAL-PCC010 board
+# coming with the STEVAL-PCC010 board
 # http://www.st.com/internet/evalboard/product/251530.jsp
 # or any other board with only a STM32F2x in the JTAG chain
 
diff --git a/tcl/board/stm3210e_eval.cfg b/tcl/board/stm3210e_eval.cfg
index 91807ce..f30253c 100644
--- a/tcl/board/stm3210e_eval.cfg
+++ b/tcl/board/stm3210e_eval.cfg
@@ -17,11 +17,11 @@ flash bank $_FLASHNAME cfi 0x64000000 0x01000000 2 2 $_TARGETNAME
 proc stm32_enable_fsmc {} {
 
 	echo "Enabling FSMC Bank 1 (NOR/PSRAM Bank 2)"
-	
+
 	# enable gpio (defg) clocks for fsmc
 	# RCC_APB2ENR
 	mww 0x40021018 0x000001E0
-	
+
 	# enable fsmc clock
 	# RCC_AHBENR
 	mww 0x40021014 0x00000114
@@ -31,29 +31,29 @@ proc stm32_enable_fsmc {} {
 	mww 0x40011400 0x44BB44BB
 	# GPIOD_CRH
 	mww 0x40011404 0xBBBBBBBB
-	
+
 	# GPIOE_CRL
 	mww 0x40011800 0xBBBBB444
 	# GPIOE_CRH
 	mww 0x40011804 0xBBBBBBBB
-	
+
 	# GPIOF_CRL
 	mww 0x40011C00 0x44BBBBBB
 	# GPIOF_CRH
 	mww 0x40011C04 0xBBBB4444
-	
+
 	# GPIOG_CRL
 	mww 0x40012000 0x44BBBBBB
 	# GPIOG_CRH
 	mww 0x40012004 0x444444B4
-	
+
 	# setup fsmc timings
 	# FSMC_BCR1
 	mww 0xA0000008 0x00001058
-	
+
 	# FSMC_BTR1
 	mww 0xA000000C 0x10000502
-	
+
 	# FSMC_BCR1 - enable fsmc
 	mww 0xA0000008 0x00001059
 }
diff --git a/tcl/board/stm32f7discovery.cfg b/tcl/board/stm32f7discovery.cfg
index 7d1bc96..7d1bc96 100755..100644
--- a/tcl/board/stm32f7discovery.cfg
+++ b/tcl/board/stm32f7discovery.cfg
diff --git a/tcl/board/stm32mp15x_dk2.cfg b/tcl/board/stm32mp15x_dk2.cfg
new file mode 100644
index 0000000..0233c6d
--- /dev/null
+++ b/tcl/board/stm32mp15x_dk2.cfg
@@ -0,0 +1,11 @@
+# board MB1272B
+# http://www.st.com/en/evaluation-tools/stm32mp157a-dk1.html
+# http://www.st.com/en/evaluation-tools/stm32mp157c-dk2.html
+
+source [find interface/stlink-dap.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32mp15x.cfg]
+
+reset_config srst_only
diff --git a/tcl/board/telo.cfg b/tcl/board/telo.cfg
index 1d3afdf..2c98ca3 100644
--- a/tcl/board/telo.cfg
+++ b/tcl/board/telo.cfg
@@ -1,5 +1,5 @@
 source [find target/c100.cfg]
-# basic register defintion for C100
+# basic register definition for C100
 source [find target/c100regs.tcl]
 # board-config info
 source [find target/c100config.tcl]
@@ -10,10 +10,10 @@ source [find target/c100helper.tcl]
 # Telo board & C100 support trst and srst
 # make the reset asserted to
 # allow RC circuit to discharge for: [ms]
-adapter_nsrst_assert_width 100
+adapter srst pulse_width 100
 jtag_ntrst_assert_width 100
 # don't talk to JTAG after reset for: [ms]
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 reset_config trst_and_srst separate
 
@@ -23,11 +23,11 @@ reset_config trst_and_srst separate
 # issue telnet: reset init
 # issue gdb: monitor reset init
 $_TARGETNAME configure -event reset-init {
-	adapter_khz 100
+	adapter speed 100
 	# this will setup Telo board
 	setupTelo
 	#turn up the JTAG speed
-	adapter_khz 3000
+	adapter speed 3000
 	echo "JTAG speek now 3MHz"
 	echo "type helpC100 to get help on C100"
 }
diff --git a/tcl/board/ti_am437x_idk.cfg b/tcl/board/ti_am437x_idk.cfg
index 65e2094..fc2b81b 100644
--- a/tcl/board/ti_am437x_idk.cfg
+++ b/tcl/board/ti_am437x_idk.cfg
@@ -4,7 +4,7 @@
 source [find interface/ftdi/xds100v2.cfg]
 
 transport select jtag
-adapter_khz 30000
+adapter speed 30000
 
 source [find target/am437x.cfg]
 $_TARGETNAME configure -event reset-init { init_platform 0x61a11b32 }
diff --git a/tcl/board/ti_am43xx_evm.cfg b/tcl/board/ti_am43xx_evm.cfg
index d536314..dbc37ae 100644
--- a/tcl/board/ti_am43xx_evm.cfg
+++ b/tcl/board/ti_am43xx_evm.cfg
@@ -1,6 +1,6 @@
 # Works on both AM437x GP EVM and AM438x ePOS EVM
 transport select jtag
-adapter_khz 16000
+adapter speed 16000
 
 source [find target/am437x.cfg]
 
diff --git a/tcl/board/ti_beagleboard_xm.cfg b/tcl/board/ti_beagleboard_xm.cfg
index e4e93e3..683f583 100644
--- a/tcl/board/ti_beagleboard_xm.cfg
+++ b/tcl/board/ti_beagleboard_xm.cfg
@@ -9,4 +9,3 @@ source [find target/amdm37x.cfg]
 reset_config trst_only
 
 # "amdm37x_dbginit dm37x.cpu" needs to be run after init.
-
diff --git a/tcl/board/ti_beaglebone.cfg b/tcl/board/ti_beaglebone.cfg
index a54ad62..7ba8c50 100644
--- a/tcl/board/ti_beaglebone.cfg
+++ b/tcl/board/ti_beaglebone.cfg
@@ -4,10 +4,8 @@
 # The JTAG interface is built directly on the board.
 source [find interface/ftdi/xds100v2.cfg]
 
-adapter_khz 16000
+adapter speed 16000
 
 reset_config trst_and_srst
 
 source [find board/ti_beaglebone-base.cfg]
-
-
diff --git a/tcl/board/ti_beaglebone_black.cfg b/tcl/board/ti_beaglebone_black.cfg
index 79fc1e8..c730814 100644
--- a/tcl/board/ti_beaglebone_black.cfg
+++ b/tcl/board/ti_beaglebone_black.cfg
@@ -1,7 +1,7 @@
 # AM335x Beaglebone Black
 #  http://beagleboard.org/bone
 
-adapter_khz 1000
+adapter speed 1000
 
 reset_config trst_and_srst
 
diff --git a/tcl/board/ti_blaze.cfg b/tcl/board/ti_blaze.cfg
index c9bbe25..4881389 100644
--- a/tcl/board/ti_blaze.cfg
+++ b/tcl/board/ti_blaze.cfg
@@ -3,4 +3,3 @@ jtag_rclk 6000
 source [find target/omap4430.cfg]
 
 reset_config trst_and_srst
-
diff --git a/tcl/board/ti_cc13x0_launchpad.cfg b/tcl/board/ti_cc13x0_launchpad.cfg
index 9e1c1ea..4fbce41 100644
--- a/tcl/board/ti_cc13x0_launchpad.cfg
+++ b/tcl/board/ti_cc13x0_launchpad.cfg
@@ -3,5 +3,5 @@
 #
 source [find interface/xds110.cfg]
 transport select jtag
-adapter_khz 2500
+adapter speed 5500
 source [find target/ti_cc13x0.cfg]
diff --git a/tcl/board/ti_cc13x2_launchpad.cfg b/tcl/board/ti_cc13x2_launchpad.cfg
index 18c5ce5..dc0c182 100644
--- a/tcl/board/ti_cc13x2_launchpad.cfg
+++ b/tcl/board/ti_cc13x2_launchpad.cfg
@@ -2,6 +2,6 @@
 # TI CC13x2 LaunchPad Evaluation Kit
 #
 source [find interface/xds110.cfg]
-adapter_khz 2500
+adapter speed 5500
 transport select jtag
 source [find target/ti_cc13x2.cfg]
diff --git a/tcl/board/ti_cc26x0_launchpad.cfg b/tcl/board/ti_cc26x0_launchpad.cfg
index 3613a47..372e57c 100644
--- a/tcl/board/ti_cc26x0_launchpad.cfg
+++ b/tcl/board/ti_cc26x0_launchpad.cfg
@@ -2,6 +2,6 @@
 # TI CC26x0 LaunchPad Evaluation Kit
 #
 source [find interface/xds110.cfg]
-adapter_khz 2500
+adapter speed 5500
 transport select jtag
 source [find target/ti_cc26x0.cfg]
diff --git a/tcl/board/ti_cc26x2_launchpad.cfg b/tcl/board/ti_cc26x2_launchpad.cfg
index 2f2b34b..c8057ad 100644
--- a/tcl/board/ti_cc26x2_launchpad.cfg
+++ b/tcl/board/ti_cc26x2_launchpad.cfg
@@ -2,6 +2,6 @@
 # TI CC26x2 LaunchPad Evaluation Kit
 #
 source [find interface/xds110.cfg]
-adapter_khz 2500
+adapter speed 5500
 transport select jtag
 source [find target/ti_cc26x2.cfg]
diff --git a/tcl/board/ti_cc3200_launchxl.cfg b/tcl/board/ti_cc3200_launchxl.cfg
index b78b09b..b37b406 100644
--- a/tcl/board/ti_cc3200_launchxl.cfg
+++ b/tcl/board/ti_cc3200_launchxl.cfg
@@ -12,9 +12,10 @@ if { [info exists TRANSPORT] } {
    transport select jtag
 }
 
-adapter_khz 2500
+adapter speed 2500
 
 set WORKAREASIZE 0x40000
 source [find target/ti_cc32xx.cfg]
 
 reset_config srst_only
+adapter srst delay 1100
diff --git a/tcl/board/ti_cc3220sf_launchpad.cfg b/tcl/board/ti_cc3220sf_launchpad.cfg
index a3dac62..7c8310a 100644
--- a/tcl/board/ti_cc3220sf_launchpad.cfg
+++ b/tcl/board/ti_cc3220sf_launchpad.cfg
@@ -2,6 +2,6 @@
 # TI CC3220SF-LaunchXL LaunchPad Evaluation Kit
 #
 source [find interface/xds110.cfg]
-adapter_khz 2500
+adapter speed 8500
 transport select swd
 source [find target/ti_cc3220sf.cfg]
diff --git a/tcl/board/ti_cc32xx_launchpad.cfg b/tcl/board/ti_cc32xx_launchpad.cfg
index f657bdf..d0f2a83 100644
--- a/tcl/board/ti_cc32xx_launchpad.cfg
+++ b/tcl/board/ti_cc32xx_launchpad.cfg
@@ -2,6 +2,9 @@
 # TI CC32xx-LaunchXL LaunchPad Evaluation Kit
 #
 source [find interface/xds110.cfg]
-adapter_khz 2500
+adapter speed 8500
 transport select swd
 source [find target/ti_cc32xx.cfg]
+
+reset_config srst_only
+adapter srst delay 1100
diff --git a/tcl/board/ti_dk-tm4c129.cfg b/tcl/board/ti_dk-tm4c129.cfg
new file mode 100644
index 0000000..f1171af
--- /dev/null
+++ b/tcl/board/ti_dk-tm4c129.cfg
@@ -0,0 +1,14 @@
+#
+# TI Tiva C DK-TM4C129X Connected Development Kit
+#
+# http://www.ti.com/tool/dk-tm4c129x
+#
+
+source [find interface/ti-icdi.cfg]
+
+transport select hla_jtag
+
+set WORKAREASIZE 0x8000
+set CHIPNAME tm4c129xnczad
+
+source [find target/stellaris.cfg]
diff --git a/tcl/board/ti_ek-tm4c123gxl.cfg b/tcl/board/ti_ek-tm4c123gxl.cfg
new file mode 100644
index 0000000..4fc1050
--- /dev/null
+++ b/tcl/board/ti_ek-tm4c123gxl.cfg
@@ -0,0 +1,13 @@
+#
+# TI Tiva C Series ek-tm4c123gxl Launchpad Evaluation Kit
+#
+# http://www.ti.com/tool/ek-tm4c123gxl
+#
+
+source [find interface/ti-icdi.cfg]
+
+transport select hla_jtag
+
+set WORKAREASIZE 0x8000
+set CHIPNAME tm4c123gh6pm
+source [find target/stellaris.cfg]
diff --git a/tcl/board/ti_ek-tm4c1294xl.cfg b/tcl/board/ti_ek-tm4c1294xl.cfg
new file mode 100644
index 0000000..b3f384c
--- /dev/null
+++ b/tcl/board/ti_ek-tm4c1294xl.cfg
@@ -0,0 +1,14 @@
+#
+# TI Tiva C Series ek-tm4c1294xl Launchpad Evaluation Kit
+#
+# http://www.ti.com/tool/ek-tm4c1294xl
+#
+
+source [find interface/ti-icdi.cfg]
+
+transport select hla_jtag
+
+set WORKAREASIZE 0x8000
+set CHIPNAME tm4c1294ncpdt
+
+source [find target/stellaris.cfg]
diff --git a/tcl/board/ti_msp432_launchpad.cfg b/tcl/board/ti_msp432_launchpad.cfg
index bfad322..6d2b15d 100644
--- a/tcl/board/ti_msp432_launchpad.cfg
+++ b/tcl/board/ti_msp432_launchpad.cfg
@@ -2,6 +2,6 @@
 # TI MSP432 LaunchPad Evaluation Kit
 #
 source [find interface/xds110.cfg]
-adapter_khz 2500
+adapter speed 10000
 transport select swd
 source [find target/ti_msp432.cfg]
diff --git a/tcl/board/ti_pandaboard.cfg b/tcl/board/ti_pandaboard.cfg
index bd2cd37..bc92596 100644
--- a/tcl/board/ti_pandaboard.cfg
+++ b/tcl/board/ti_pandaboard.cfg
@@ -3,4 +3,3 @@ jtag_rclk 6000
 source [find target/omap4430.cfg]
 
 reset_config trst_only
-
diff --git a/tcl/board/ti_pandaboard_es.cfg b/tcl/board/ti_pandaboard_es.cfg
index 2abd7e9..756fa33 100644
--- a/tcl/board/ti_pandaboard_es.cfg
+++ b/tcl/board/ti_pandaboard_es.cfg
@@ -3,4 +3,3 @@ jtag_rclk 6000
 source [find target/omap4460.cfg]
 
 reset_config trst_only
-
diff --git a/tcl/board/ti_tmdx570ls31usb.cfg b/tcl/board/ti_tmdx570ls31usb.cfg
index 5502444..6d73502 100644
--- a/tcl/board/ti_tmdx570ls31usb.cfg
+++ b/tcl/board/ti_tmdx570ls31usb.cfg
@@ -1,4 +1,4 @@
-adapter_khz 1500
+adapter speed 1500
 
 source [find interface/ftdi/xds100v2.cfg]
 source [find target/ti_tms570.cfg]
diff --git a/tcl/board/tocoding_poplar.cfg b/tcl/board/tocoding_poplar.cfg
index d8b8330..d0951ce 100644
--- a/tcl/board/tocoding_poplar.cfg
+++ b/tcl/board/tocoding_poplar.cfg
@@ -5,7 +5,7 @@
 # board does not feature anything but JTAG
 transport select jtag
 
-adapter_khz 10000
+adapter speed 10000
 
 # SRST-only reset configuration
 reset_config srst_only srst_push_pull
diff --git a/tcl/board/topas910.cfg b/tcl/board/topas910.cfg
index 90c18c4..9f994c8 100644
--- a/tcl/board/topas910.cfg
+++ b/tcl/board/topas910.cfg
@@ -30,7 +30,7 @@ proc topas910_init { } {
 # Init SDRAM
 #  _PMCDRV          = 0x00000071;
 #  //
-#  // Initialize SDRAM timing paramater
+#  // Initialize SDRAM timing parameter
 #  //
 #  _DMC_CAS_LATENCY = 0x00000006;
 #  _DMC_T_DQSS      = 0x00000000;
@@ -99,7 +99,7 @@ proc topas910_init { } {
 	mww 0xf4300004 0x00000000
 
 	sleep 10
-#	adapter_khz NNNN
+#	adapter speed NNNN
 
 # remap off in case of IROM boot
 	mww 0xf0000004 0x00000001
diff --git a/tcl/board/topasa900.cfg b/tcl/board/topasa900.cfg
index 2a388d5..4fa6383 100644
--- a/tcl/board/topasa900.cfg
+++ b/tcl/board/topasa900.cfg
@@ -37,7 +37,7 @@ proc topasa900_init { } {
 # Init SDRAM
 #  _PMCDRV          = 0x00000071;
 #  //
-#  // Initialize SDRAM timing paramater
+#  // Initialize SDRAM timing parameter
 #  //
 #  _DMC_CAS_LATENCY = 0x00000006;
 #  _DMC_T_DQSS      = 0x00000000;
@@ -105,7 +105,7 @@ proc topasa900_init { } {
 	mww 0xf4300004 0x00000000
 
 	sleep 10
-#	adapter_khz NNNN
+#	adapter speed NNNN
 
 # remap off in case of IROM boot
 	mww 0xf0000004 0x00000001
@@ -123,4 +123,3 @@ arm7_9 dcc_downloads enable       ;# Enable faster DCC downloads
 #flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME cfi 0x20000000 0x1000000 2 2 $_TARGETNAME
-
diff --git a/tcl/board/twr-k60f120m.cfg b/tcl/board/twr-k60f120m.cfg
index e96d045..c4d87db 100644
--- a/tcl/board/twr-k60f120m.cfg
+++ b/tcl/board/twr-k60f120m.cfg
@@ -5,7 +5,7 @@
 source [find target/k60.cfg]
 
 $_TARGETNAME configure -event reset-init {
-	puts "-event reset-init occured"
+	puts "-event reset-init occurred"
 }
 
 #
diff --git a/tcl/board/twr-k60n512.cfg b/tcl/board/twr-k60n512.cfg
index d2312cf..5babeb8 100644
--- a/tcl/board/twr-k60n512.cfg
+++ b/tcl/board/twr-k60n512.cfg
@@ -5,7 +5,7 @@
 source [find target/k60.cfg]
 
 $_TARGETNAME configure -event reset-init {
-	puts "-event reset-init occured"
+	puts "-event reset-init occurred"
 }
 
 #
diff --git a/tcl/board/twr-vf65gs10.cfg b/tcl/board/twr-vf65gs10.cfg
index a80407f..0d6d332 100644
--- a/tcl/board/twr-vf65gs10.cfg
+++ b/tcl/board/twr-vf65gs10.cfg
@@ -198,4 +198,4 @@ proc board_init { } {
 # hook the init function into the reset-init event
 ${_TARGETNAME}0 configure -event reset-init { board_init }
 # set a slow default JTAG clock, can be overridden later
-adapter_khz 1000
+adapter speed 1000
diff --git a/tcl/board/twr-vf65gs10_cmsisdap.cfg b/tcl/board/twr-vf65gs10_cmsisdap.cfg
index e8db754..ab4548f 100644
--- a/tcl/board/twr-vf65gs10_cmsisdap.cfg
+++ b/tcl/board/twr-vf65gs10_cmsisdap.cfg
@@ -12,4 +12,4 @@ transport select swd
 source [find board/twr-vf65gs10.cfg]
 
 # override reset configuration
-reset_config srst_only
-\ No newline at end of file
+reset_config srst_only
diff --git a/tcl/board/unknown_at91sam9260.cfg b/tcl/board/unknown_at91sam9260.cfg
index de49a69..5570ef0 100644
--- a/tcl/board/unknown_at91sam9260.cfg
+++ b/tcl/board/unknown_at91sam9260.cfg
@@ -93,5 +93,3 @@ $_TARGETNAME configure -event reset-init {
 #flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
-
-
diff --git a/tcl/board/uptech_2410.cfg b/tcl/board/uptech_2410.cfg
index 950f2a7..227cf42 100644
--- a/tcl/board/uptech_2410.cfg
+++ b/tcl/board/uptech_2410.cfg
@@ -11,28 +11,28 @@ proc init_pll_sdram { } {
 	#echo "---------- Initializing PLL and SDRAM ---------"
 	#watchdog timer disable
 	mww phys 0x53000000 0x00000000
-	
+
 	#disable all interrupts
 	mww phys 0x4a000008 0xffffffff
-	
+
 	#disable all sub-interrupts
 	mww phys 0x4a00001c 0x000007ff
-	
+
 	#clear all source pending bits
 	mww phys 0x4a000000 0xffffffff
-	
+
 	#clear all sub-source pending bits
 	mww phys 0x4a000018 0x000007ff
-	
+
 	#clear interrupt pending bit
 	mww phys 0x4a000010 0xffffffff
-	
+
 	#PLL locktime counter
 	mww phys 0x4c000000 0x00ffffff
-	
+
 	#Fin=12MHz Fout=202.8MHz
 	#mww phys 0x4c000004 0x000a1031
-	
+
 	#FCLK:HCLK:PCLK = 1:2:4
 	mww phys 0x4c000014 0x00000003
 
@@ -61,5 +61,3 @@ proc uptech2410_init { } {
 
 set _NANDNAME $_CHIPNAME.nand
 nand device $_NANDNAME s3c2410 $_TARGETNAME
-
-
diff --git a/tcl/board/verdex.cfg b/tcl/board/verdex.cfg
index 6da9875..dd267fc 100644
--- a/tcl/board/verdex.cfg
+++ b/tcl/board/verdex.cfg
@@ -8,7 +8,7 @@ source [find target/pxa270.cfg]
 reset_config trst_and_srst separate
 
 # XM4 = 400MHz, XL6P = 600MHz...let's run at 0.1*400MHz=40MHz
-adapter_khz 40000
+adapter speed 40000
 
 # flash bank <driver> <base> <size> <chip_width> <bus_width>
 # XL6P has 32 MB flash
diff --git a/tcl/board/voltcraft_dso-3062c.cfg b/tcl/board/voltcraft_dso-3062c.cfg
index 01e37e9..f300cf2 100644
--- a/tcl/board/voltcraft_dso-3062c.cfg
+++ b/tcl/board/voltcraft_dso-3062c.cfg
@@ -13,7 +13,7 @@
 
 source [find target/samsung_s3c2440.cfg]
 
-adapter_khz 16000
+adapter speed 16000
 
 # Samsung K9F1208U0C NAND flash chip (64MiB, 3.3V, 8-bit)
 nand device $_CHIPNAME.nand s3c2440 $_TARGETNAME
@@ -28,4 +28,3 @@ scan_chain
 targets
 nand probe 0
 nand list
-
diff --git a/tcl/board/zy1000.cfg b/tcl/board/zy1000.cfg
index 57deaa8..e0d1ccf 100644
--- a/tcl/board/zy1000.cfg
+++ b/tcl/board/zy1000.cfg
@@ -72,7 +72,7 @@ $_TARGETNAME configure -event gdb-attach {
 # other things than flash programming.
 $_TARGETNAME configure -work-area-phys 0x00020000 -work-area-size 0x20000 -work-area-backup 0
 
-adapter_khz 16000
+adapter speed 16000
 
 
 proc production_info {} {
diff --git a/tcl/chip/atmel/at91/aic.tcl b/tcl/chip/atmel/at91/aic.tcl
index 6dae36a..ba0f2a9 100644
--- a/tcl/chip/atmel/at91/aic.tcl
+++ b/tcl/chip/atmel/at91/aic.tcl
@@ -98,4 +98,3 @@ proc show_AIC { } {
 	}
     }
 }
-
diff --git a/tcl/chip/atmel/at91/at91sam9263_matrix.cfg b/tcl/chip/atmel/at91/at91sam9263_matrix.cfg
index ad3d9a2..f287cd9 100644
--- a/tcl/chip/atmel/at91/at91sam9263_matrix.cfg
+++ b/tcl/chip/atmel/at91/at91sam9263_matrix.cfg
@@ -108,5 +108,3 @@ set		AT91_MATRIX_EBI1_DBPUC		[expr (1 << 8)]	;# Data Bus Pull-up Configuration
 set		AT91_MATRIX_EBI1_VDDIOMSEL	[expr (1 << 16)]	;# Memory voltage selection
 set			AT91_MATRIX_EBI1_VDDIOMSEL_1_8V		[expr (0 << 16)]
 set			AT91_MATRIX_EBI1_VDDIOMSEL_3_3V		[expr (1 << 16)]
-
-
diff --git a/tcl/chip/atmel/at91/pmc.tcl b/tcl/chip/atmel/at91/pmc.tcl
index 584acb8..7cb1d09 100644
--- a/tcl/chip/atmel/at91/pmc.tcl
+++ b/tcl/chip/atmel/at91/pmc.tcl
@@ -14,4 +14,3 @@ if [info exists AT91C_SLOWOSC_FREQ] {
     set AT91C_SLOWOSC_FREQ 32768
 }
 global AT91C_SLOWOSC_FREQ
-
diff --git a/tcl/chip/atmel/at91/rtt.tcl b/tcl/chip/atmel/at91/rtt.tcl
index 8be6a56..2dd74fa 100644
--- a/tcl/chip/atmel/at91/rtt.tcl
+++ b/tcl/chip/atmel/at91/rtt.tcl
@@ -53,4 +53,3 @@ proc show_RTTC { } {
     show_mmr32_reg RTTC_RTVR
     show_mmr32_reg RTTC_RTSR
 }
-
diff --git a/tcl/chip/atmel/at91/usarts.tcl b/tcl/chip/atmel/at91/usarts.tcl
index 6842029..ecc4f60 100644
--- a/tcl/chip/atmel/at91/usarts.tcl
+++ b/tcl/chip/atmel/at91/usarts.tcl
@@ -130,6 +130,3 @@ proc show_DBGU { } $str
 unset str
 
 proc show_DBGU_MR_helper { NAME ADDR VAL } { show_mmr_USx_MR_helper $NAME $ADDR $VAL }
-
-
-
diff --git a/tcl/cpu/arc/common.tcl b/tcl/cpu/arc/common.tcl
new file mode 100644
index 0000000..e9a9157
--- /dev/null
+++ b/tcl/cpu/arc/common.tcl
@@ -0,0 +1,40 @@
+#  Copyright (C) 2015, 2020 Synopsys, Inc.
+#  Anton Kolesov <anton.kolesov@synopsys.com>
+#  Didin Evgeniy <didin@synopsys.com>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Things common to all ARCs
+
+# It is assumed that target is already halted.
+proc arc_common_reset { {target ""} } {
+        if { $target != "" } {
+                targets $target
+        }
+
+        halt
+
+        # 1. Interrupts are disabled (STATUS32.IE)
+        # 2. The status register flags are cleared.
+        # All fields, except the H bit, are set to 0 when the processor is Reset.
+
+        arc jtag set-aux-reg 0xA 0x1
+
+        # 3. The loop count, loop start, and loop end registers are cleared.
+        arc jtag set-core-reg 60 0
+        arc jtag set-aux-reg 0x2 0
+        arc jtag set-aux-reg 0x3 0
+
+        # Program execution begins at the address referenced by the four byte reset
+        # vector located at the interrupt vector base address, which is the first
+        # entry (offset 0x00) in the vector table.
+        set int_vector_base [arc jtag get-aux-reg 0x25]
+        set start_pc ""
+        mem2array start_pc 32 $int_vector_base 1
+        arc jtag set-aux-reg 0x6 $start_pc(0)
+
+        # It is OK to do uncached writes - register cache will be invalidated by
+        # the reset_assert() function.
+}
+
+# vim:expandtab:
diff --git a/tcl/cpu/arc/em.tcl b/tcl/cpu/arc/em.tcl
new file mode 100644
index 0000000..f0455bb
--- /dev/null
+++ b/tcl/cpu/arc/em.tcl
@@ -0,0 +1,32 @@
+#  Copyright (C) 2015, 2020 Synopsys, Inc.
+#  Anton Kolesov <anton.kolesov@synopsys.com>
+#  Didin Evgeniy <didin@synopsys.com>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find cpu/arc/v2.tcl]
+
+proc arc_em_examine_target { {target ""} } {
+	# Will set current target
+	arc_v2_examine_target $target
+}
+
+proc arc_em_init_regs { } {
+	arc_v2_init_regs
+
+	[target current] configure \
+		-event examine-end "arc_em_examine_target [target current]"
+}
+
+# Scripts in "target" folder should call this function instead of direct
+# invocation of arc_common_reset.
+proc arc_em_reset { {target ""} } {
+	arc_v2_reset $target
+
+	# Set DEBUG.ED bit to enable clock in actionpoint module.
+	# This is specific to ARC EM.
+	set debug [arc jtag get-aux-reg 5]
+	if { !($debug & (1 << 20)) } {
+		arc jtag set-aux-reg 5 [expr $debug | (1 << 20)]
+	}
+}
diff --git a/tcl/cpu/arc/v2.tcl b/tcl/cpu/arc/v2.tcl
new file mode 100644
index 0000000..ad55361
--- /dev/null
+++ b/tcl/cpu/arc/v2.tcl
@@ -0,0 +1,288 @@
+#  Copyright (C) 2015, 2020 Synopsys, Inc.
+#  Anton Kolesov <anton.kolesov@synopsys.com>
+#  Didin Evgeniy <didin@synopsys.com>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find cpu/arc/common.tcl]
+
+# Currently 'examine_target' can only read JTAG registers and set properties -
+# but it shouldn't write any of registers - writes will be cached, but cache
+# will be invalidated before flushing after examine_target, and changes will be
+# lost.  Perhaps that would be fixed later - perhaps writes shouldn't be cached
+# after all.  But if write to register is really needed from TCL - then it
+# should be done via "arc jtag" for now.
+proc arc_v2_examine_target { {target ""} } {
+	# Set current target, because OpenOCD event handlers don't do this for us.
+	if { $target != "" } {
+		targets $target
+	}
+
+	# Those registers always exist. DEBUG and DEBUGI are formally optional,
+	# however they come with JTAG interface, and so far there is no way
+	# OpenOCD can communicate with target without JTAG interface.
+	arc set-reg-exists identity pc status32 bta debug lp_start lp_end \
+		eret erbta erstatus ecr efa
+
+	# 32 core registers
+	arc set-reg-exists \
+		r0  r1  r2  r3  r4  r5  r6  r7  r8  r9  r10 r11 r12 \
+		r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 \
+		gp fp sp ilink r30 blink lp_count pcl
+
+	# DCCM
+	set dccm_version [arc get-reg-field dccm_build version]
+	if { $dccm_version == 3 || $dccm_version == 4 } {
+		arc set-reg-exists aux_dccm
+	}
+
+	# ICCM
+	if { [arc get-reg-field iccm_build version] == 4 } {
+		arc set-reg-exists aux_iccm
+	}
+
+	# MPU
+	if { [arc get-reg-field mpu_build version] >= 2 &&
+		 [arc get-reg-field mpu_build version] <= 4 } {
+		arc set-reg-exists mpu_en mpu_ecr
+		set mpu_regions [arc get-reg-field mpu_build regions]
+		for {set i 0} {$i < $mpu_regions} {incr i} {
+			arc set-reg-exists mpu_rdp$i mpu_rdb$i
+		}
+
+		# Secure MPU
+		if { [arc get-reg-field mpu_build version] == 4 } {
+			arc set-reg-exists mpu_index mpu_rstart mpu_rend mpu_rper
+		}
+	}
+}
+
+proc arc_v2_init_regs { } {
+	# XML features
+	set core_feature "org.gnu.gdb.arc.core.v2"
+	set aux_min_feature "org.gnu.gdb.arc.aux-minimal"
+	set aux_other_feature "org.gnu.gdb.arc.aux-other"
+
+	# Describe types
+	# Types are sorted alphabetically according to their name.
+	arc add-reg-type-struct -name ap_build_t -bitfield version 0 7 \
+		-bitfield type 8 11
+	arc add-reg-type-struct -name ap_control_t -bitfield at 0 3 -bitfield tt 4 5 \
+		-bitfield m 6 6 -bitfield p 7 7 -bitfield aa 8 8 -bitfield q 9 9
+	# Cycles field added in version 4.
+	arc add-reg-type-struct -name dccm_build_t -bitfield version 0 7 \
+		-bitfield size0 8 11 -bitfield size1 12 15 -bitfield cycles 17 19
+
+	arc add-reg-type-struct -name debug_t \
+		-bitfield fh 1 1   -bitfield ah 2 2   -bitfield asr 3 10 \
+		-bitfield is 11 11 -bitfield ep 19 19 -bitfield ed 20 20 \
+		-bitfield eh 21 21 -bitfield ra 22 22 -bitfield zz 23 23 \
+		-bitfield sm 24 26 -bitfield ub 28 28 -bitfield bh 29 29 \
+		-bitfield sh 30 30 -bitfield ld 31 31
+
+	arc add-reg-type-struct -name ecr_t \
+		-bitfield parameter 0 7 \
+		-bitfield cause 8 15 \
+		-bitfield vector 16 23 \
+		-bitfield U 30 30 \
+		-bitfield P 31 31
+	arc add-reg-type-struct -name iccm_build_t -bitfield version 0 7 \
+		-bitfield iccm0_size0  8 11 -bitfield iccm1_size0 12 15 \
+		-bitfield iccm0_size1 16 19 -bitfield iccm1_size1 20 23
+	arc add-reg-type-struct -name identity_t \
+		-bitfield arcver 0 7 -bitfield arcnum 8 15 -bitfield chipid 16 31
+	arc add-reg-type-struct -name isa_config_t -bitfield version 0 7 \
+		-bitfield pc_size 8 11 -bitfield lpc_size 12 15 -bitfield addr_size 16 19 \
+		-bitfield b 20 20 -bitfield a 21 21 -bitfield n 22 22 -bitfield l 23 23 \
+		-bitfield c 24 27 -bitfield d 28 31
+	arc add-reg-type-struct -name mpu_build_t -bitfield version 0 7 \
+		-bitfield regions 8 15 \
+		-bitfield s 16 16 \
+		-bitfield i 17 17
+	arc add-reg-type-struct -name mpu_ecr_t \
+		-bitfield MR 0 7 \
+		-bitfield VT 8 9 \
+		-bitfield EC_CODE 16 31
+	arc add-reg-type-struct -name mpu_en_t \
+		-bitfield UE  3  3 -bitfield UW   4  4 -bitfield UR 5 5 \
+		-bitfield KE  6  6 -bitfield KW   7  7 -bitfield KR 8 8 \
+		-bitfield S  15 15 -bitfield SID 16 23 \
+		-bitfield EN 30 30
+	arc add-reg-type-struct -name mpu_index_t \
+		-bitfield I 0 3 -bitfield M 30 30 -bitfield D 31 31
+	arc add-reg-type-struct -name mpu_rper_t \
+		-bitfield V 0 0 \
+		-bitfield UE 3 3 -bitfield UW 4 4 -bitfield UR 5 5 \
+		-bitfield KE 6 6 -bitfield KW 7 7 -bitfield KR 8 8 \
+		-bitfield S 15 15 -bitfield SID 16 23
+	arc add-reg-type-flags -name status32_t \
+		-flag   H  0 -flag E0   1 -flag E1   2 -flag E2  3 \
+		-flag  E3  4 -flag AE   5 -flag DE   6 -flag  U  7 \
+		-flag   V  8 -flag  C   9 -flag  N  10 -flag  Z 11 \
+		-flag   L 12 -flag DZ  13 -flag SC  14 -flag ES 15 \
+		-flag RB0 16 -flag RB1 17 -flag RB2 18 \
+		-flag  AD 19 -flag US  20 -flag IE  31
+
+	# Core registers
+	set core_regs {
+		r0       0  uint32
+		r1       1  uint32
+		r2       2  uint32
+		r3       3  uint32
+		r4       4  uint32
+		r5       5  uint32
+		r6       6  uint32
+		r7       7  uint32
+		r8       8  uint32
+		r9       9  uint32
+		r10      10 uint32
+		r11      11 uint32
+		r12      12 uint32
+		r13      13 uint32
+		r14      14 uint32
+		r15      15 uint32
+		r16      16 uint32
+		r17      17 uint32
+		r18      18 uint32
+		r19      19 uint32
+		r20      20 uint32
+		r21      21 uint32
+		r22      23 uint32
+		r23      24 uint32
+		r24      24 uint32
+		r25      25 uint32
+		gp       26 data_ptr
+		fp       27 data_ptr
+		sp       28 data_ptr
+		ilink    29 code_ptr
+		r30      30 uint32
+		blink    31 code_ptr
+		r32      32 uint32
+		r33      33 uint32
+		r34      34 uint32
+		r35      35 uint32
+		r36      36 uint32
+		r37      37 uint32
+		r38      38 uint32
+		r39      39 uint32
+		r40      40 uint32
+		r41      41 uint32
+		r42      42 uint32
+		r43      43 uint32
+		r44      44 uint32
+		r45      45 uint32
+		r46      46 uint32
+		r47      47 uint32
+		r48      48 uint32
+		r49      49 uint32
+		r50      50 uint32
+		r51      51 uint32
+		r52      52 uint32
+		r53      53 uint32
+		r54      54 uint32
+		r55      55 uint32
+		r56      56 uint32
+		r57      57 uint32
+		accl     58 uint32
+		acch     59 uint32
+		lp_count 60 uint32
+		limm     61 uint32
+		reserved 62 uint32
+		pcl      63 code_ptr
+	}
+	foreach {reg count type} $core_regs {
+		arc add-reg -name $reg -num $count -core -type $type -g \
+			-feature $core_feature
+	}
+
+	# AUX min
+	set aux_min {
+		0x6 pc       code_ptr
+		0x2 lp_start code_ptr
+		0x3 lp_end   code_ptr
+		0xA status32 status32_t
+	}
+	foreach {num name type} $aux_min {
+		arc add-reg -name $name -num $num -type $type -feature $aux_min_feature -g
+	}
+
+	# AUX other
+	set aux_other {
+		0x004 identity	identity_t
+		0x005 debug		debug_t
+		0x018 aux_dccm	int
+		0x208 aux_iccm	int
+
+
+		0x400 eret		code_ptr
+		0x401 erbta		code_ptr
+		0x402 erstatus	status32_t
+		0x403 ecr		ecr_t
+		0x404 efa		data_ptr
+
+		0x409 mpu_en	mpu_en_t
+
+		0x412 bta		code_ptr
+
+		0x420 mpu_ecr	mpu_ecr_t
+		0x422 mpu_rdb0	int
+		0x423 mpu_rdp0	int
+		0x424 mpu_rdb1	int
+		0x425 mpu_rdp1	int
+		0x426 mpu_rdb2	int
+		0x427 mpu_rdp2	int
+		0x428 mpu_rdb3	int
+		0x429 mpu_rdp3	int
+		0x42A mpu_rdb4	int
+		0x42B mpu_rdp4	int
+		0x42C mpu_rdb5	int
+		0x42D mpu_rdp5	int
+		0x42E mpu_rdb6	int
+		0x42F mpu_rdp6	int
+		0x430 mpu_rdb7	int
+		0x431 mpu_rdp7	int
+		0x432 mpu_rdb8	int
+		0x433 mpu_rdp8	int
+		0x434 mpu_rdb9	int
+		0x435 mpu_rdp9	int
+		0x436 mpu_rdb10	int
+		0x437 mpu_rdp10	int
+		0x438 mpu_rdb11	int
+		0x439 mpu_rdp11	int
+		0x43A mpu_rdb12	int
+		0x43B mpu_rdp12	int
+		0x43C mpu_rdb13	int
+		0x43D mpu_rdp13	int
+		0x43E mpu_rdb14	int
+		0x43F mpu_rdp14	int
+		0x440 mpu_rdb15	int
+		0x441 mpu_rdp15	int
+		0x448 mpu_index	mpu_index_t
+		0x449 mpu_rstart uint32
+		0x44A mpu_rend	uint32
+		0x44B mpu_rper	mpu_rper_t
+		0x44C mpu_probe uint32
+	}
+	foreach {num name type} $aux_other {
+		arc add-reg -name $name -num $num -type $type -feature $aux_other_feature
+	}
+
+	# AUX BCR
+	set bcr {
+		0x6D mpu_build
+		0x74 dccm_build
+		0x76 ap_build
+		0x78 iccm_build
+		0xC1 isa_config
+	}
+	foreach {num reg} $bcr {
+		arc add-reg -name $reg -num $num -type ${reg}_t -bcr -feature $aux_other_feature
+	}
+
+	[target current] configure \
+		-event examine-end "arc_v2_examine_target [target current]"
+}
+
+proc arc_v2_reset { {target ""} } {
+	arc_common_reset $target
+}
diff --git a/tcl/cpu/arm/arm7tdmi.tcl b/tcl/cpu/arm/arm7tdmi.tcl
index 37db266..a1d4a1f 100644
--- a/tcl/cpu/arm/arm7tdmi.tcl
+++ b/tcl/cpu/arm/arm7tdmi.tcl
@@ -3,4 +3,3 @@ set CPU_NAME   arm7tdmi
 set CPU_ARCH   armv4t
 set CPU_MAX_ADDRESS 0xFFFFFFFF
 set CPU_NBITS  32
-
diff --git a/tcl/cpu/arm/arm920.tcl b/tcl/cpu/arm/arm920.tcl
index f19b20b..c01f602 100644
--- a/tcl/cpu/arm/arm920.tcl
+++ b/tcl/cpu/arm/arm920.tcl
@@ -3,4 +3,3 @@ set CPU_NAME   arm920
 set CPU_ARCH   armv4t
 set CPU_MAX_ADDRESS 0xFFFFFFFF
 set CPU_NBITS  32
-
diff --git a/tcl/cpu/arm/arm946.tcl b/tcl/cpu/arm/arm946.tcl
index 5204101..a6110a5 100644
--- a/tcl/cpu/arm/arm946.tcl
+++ b/tcl/cpu/arm/arm946.tcl
@@ -3,4 +3,3 @@ set CPU_NAME   arm946
 set CPU_ARCH   armv5te
 set CPU_MAX_ADDRESS 0xFFFFFFFF
 set CPU_NBITS  32
-
diff --git a/tcl/cpu/arm/arm966.tcl b/tcl/cpu/arm/arm966.tcl
index 83ce0f6..1fffbc0 100644
--- a/tcl/cpu/arm/arm966.tcl
+++ b/tcl/cpu/arm/arm966.tcl
@@ -3,4 +3,3 @@ set CPU_NAME   arm966
 set CPU_ARCH   armv5te
 set CPU_MAX_ADDRESS 0xFFFFFFFF
 set CPU_NBITS  32
-
diff --git a/tcl/cpu/arm/cortex_m3.tcl b/tcl/cpu/arm/cortex_m3.tcl
index 166af84..c995026 100644
--- a/tcl/cpu/arm/cortex_m3.tcl
+++ b/tcl/cpu/arm/cortex_m3.tcl
@@ -3,4 +3,3 @@ set CPU_NAME   cortex_m3
 set CPU_ARCH   armv7
 set CPU_MAX_ADDRESS 0xFFFFFFFF
 set CPU_NBITS  32
-
diff --git a/tcl/fpga/xilinx-xadc.cfg b/tcl/fpga/xilinx-xadc.cfg
index 3869104..d4be4f5 100644
--- a/tcl/fpga/xilinx-xadc.cfg
+++ b/tcl/fpga/xilinx-xadc.cfg
@@ -5,7 +5,7 @@
 # voltages. The XADC is available both from fabric as well as through the
 # JTAG TAP.
 #
-# This code implements access throught the JTAG TAP.
+# This code implements access through the JTAG TAP.
 #
 # https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf
 
diff --git a/tcl/interface/altera-usb-blaster.cfg b/tcl/interface/altera-usb-blaster.cfg
index 1bfef9d..84e77b1 100644
--- a/tcl/interface/altera-usb-blaster.cfg
+++ b/tcl/interface/altera-usb-blaster.cfg
@@ -4,7 +4,7 @@
 # http://www.altera.com/literature/ug/ug_usb_blstr.pdf
 #
 
-interface usb_blaster
+adapter driver usb_blaster
 usb_blaster_lowlevel_driver ftdi
 # These are already the defaults.
 # usb_blaster_vid_pid 0x09FB 0x6001
diff --git a/tcl/interface/altera-usb-blaster2.cfg b/tcl/interface/altera-usb-blaster2.cfg
index c35be19..4642b1d 100644
--- a/tcl/interface/altera-usb-blaster2.cfg
+++ b/tcl/interface/altera-usb-blaster2.cfg
@@ -2,7 +2,7 @@
 # Altera USB-Blaster II
 #
 
-interface usb_blaster
+adapter driver usb_blaster
 usb_blaster_vid_pid 0x09fb 0x6010 0x09fb 0x6810
 usb_blaster_lowlevel_driver ublast2
 usb_blaster_firmware /path/to/quartus/blaster_6810.hex
diff --git a/tcl/interface/arm-jtag-ew.cfg b/tcl/interface/arm-jtag-ew.cfg
index 2e8b57e..797bb71 100644
--- a/tcl/interface/arm-jtag-ew.cfg
+++ b/tcl/interface/arm-jtag-ew.cfg
@@ -4,5 +4,4 @@
 # http://www.olimex.com/dev/arm-jtag-ew.html
 #
 
-interface arm-jtag-ew
-
+adapter driver arm-jtag-ew
diff --git a/tcl/interface/at91rm9200.cfg b/tcl/interface/at91rm9200.cfg
index 2082647..b66e060 100644
--- a/tcl/interface/at91rm9200.cfg
+++ b/tcl/interface/at91rm9200.cfg
@@ -4,6 +4,5 @@
 # TODO: URL?
 #
 
-interface at91rm9200
+adapter driver at91rm9200
 at91rm9200_device rea_ecr
-
diff --git a/tcl/interface/buspirate.cfg b/tcl/interface/buspirate.cfg
index c2f3a83..265e37e 100644
--- a/tcl/interface/buspirate.cfg
+++ b/tcl/interface/buspirate.cfg
@@ -4,7 +4,7 @@
 # http://dangerousprototypes.com/bus-pirate-manual/
 #
 
-interface buspirate
+adapter driver buspirate
 
 # you need to specify port on which BP lives
 #buspirate_port /dev/ttyUSB0
@@ -23,4 +23,3 @@ buspirate_speed normal ;# or fast
 
 # this depends on the cable, you are safe with this option
 reset_config srst_only
-
diff --git a/tcl/interface/calao-usb-a9260.cfg b/tcl/interface/calao-usb-a9260.cfg
index 5fae2f3..01b426b 100644
--- a/tcl/interface/calao-usb-a9260.cfg
+++ b/tcl/interface/calao-usb-a9260.cfg
@@ -6,6 +6,5 @@
 # See calao-usb-a9260-c01.cfg and calao-usb-a9260-c02.cfg.
 #
 
-adapter_nsrst_delay 200
+adapter srst delay 200
 jtag_ntrst_delay 200
-
diff --git a/tcl/interface/chameleon.cfg b/tcl/interface/chameleon.cfg
index 2fb7468..1cb1d61 100644
--- a/tcl/interface/chameleon.cfg
+++ b/tcl/interface/chameleon.cfg
@@ -4,6 +4,5 @@
 # http://www.amontec.com/chameleon.shtml
 #
 
-interface parport
+adapter driver parport
 parport_cable chameleon
-
diff --git a/tcl/interface/cmsis-dap.cfg b/tcl/interface/cmsis-dap.cfg
index ab5c187..887d2d7 100644
--- a/tcl/interface/cmsis-dap.cfg
+++ b/tcl/interface/cmsis-dap.cfg
@@ -4,7 +4,7 @@
 # http://www.keil.com/support/man/docs/dapdebug/
 #
 
-interface cmsis-dap
+adapter driver cmsis-dap
 
 # Optionally specify the serial number of CMSIS-DAP usb device.
 #cmsis_dap_serial 02200201E6661E601B98E3B9
diff --git a/tcl/interface/dummy.cfg b/tcl/interface/dummy.cfg
index 1c148c0..154c872 100644
--- a/tcl/interface/dummy.cfg
+++ b/tcl/interface/dummy.cfg
@@ -2,5 +2,4 @@
 # Dummy interface (for testing purposes)
 #
 
-interface dummy
-
+adapter driver dummy
diff --git a/tcl/interface/estick.cfg b/tcl/interface/estick.cfg
index adefcb7..75e6ea8 100644
--- a/tcl/interface/estick.cfg
+++ b/tcl/interface/estick.cfg
@@ -4,4 +4,4 @@
 # http://code.google.com/p/estick-jtag/
 #
 
-interface opendous
+adapter driver opendous
diff --git a/tcl/interface/flashlink.cfg b/tcl/interface/flashlink.cfg
index 56dc35e..e0a4b97 100644
--- a/tcl/interface/flashlink.cfg
+++ b/tcl/interface/flashlink.cfg
@@ -11,6 +11,6 @@ if { [info exists PARPORTADDR] } {
    set _PARPORTADDR 0
 }
 
-interface parport
+adapter driver parport
 parport_port $_PARPORTADDR
 parport_cable flashlink
diff --git a/tcl/interface/ft232r.cfg b/tcl/interface/ft232r.cfg
index b4f71c8..2c705c3 100644
--- a/tcl/interface/ft232r.cfg
+++ b/tcl/interface/ft232r.cfg
@@ -1,2 +1,2 @@
-interface ft232r
-adapter_khz 1000
+adapter driver ft232r
+adapter speed 1000
diff --git a/tcl/interface/ftdi/100ask-openjtag.cfg b/tcl/interface/ftdi/100ask-openjtag.cfg
index 01ae2f7..3cbd37e 100644
--- a/tcl/interface/ftdi/100ask-openjtag.cfg
+++ b/tcl/interface/ftdi/100ask-openjtag.cfg
@@ -7,7 +7,7 @@
 # https://blog.matthiasbock.net/wp-content/uploads/2015/04/100ask-JTAGv3.pdf
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "USB<=>JTAG&RS232"
 ftdi_vid_pid 0x1457 0x5118
 
diff --git a/tcl/interface/ftdi/axm0432.cfg b/tcl/interface/ftdi/axm0432.cfg
index 0c24a33..6cc1752 100644
--- a/tcl/interface/ftdi/axm0432.cfg
+++ b/tcl/interface/ftdi/axm0432.cfg
@@ -9,7 +9,7 @@ echo "This file was not tested with real interface, it is based on code in ft223
 echo "Please report your experience with this file to openocd-devel mailing list,"
 echo "so it could be marked as working or fixed."
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Symphony SoundBite"
 ftdi_vid_pid 0x0403 0x6010
 
diff --git a/tcl/interface/ftdi/c232hm.cfg b/tcl/interface/ftdi/c232hm.cfg
index 387abbb..27cf766 100644
--- a/tcl/interface/ftdi/c232hm.cfg
+++ b/tcl/interface/ftdi/c232hm.cfg
@@ -1,4 +1,3 @@
-#
 # FTDI USB Hi-Speed to MPSSE Cable
 #
 # http://www.ftdichip.com/Products/Cables/USBMPSSE.htm
@@ -6,10 +5,52 @@
 # C232HM-DDHSL-0 and C232HM-EDSL-0 provide 3.3V and 5V on pin 1 (Red),
 # respectively.
 #
+# Adapter: http://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_C232HM_MPSSE_CABLE.PDF
+# Chip: http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232H.pdf
+# See pinout/colors at end of this file.
+#
+# Tech notes:
+# http://www.ftdichip.com/Support/Documents/AppNotes/AN_135_MPSSE_Basics.pdf
+# http://www.ftdichip.com/Support/Documents/AppNotes/AN_129_FTDI_Hi_Speed_USB_To_JTAG_Example.pdf
 
-interface ftdi
+adapter driver ftdi
 #ftdi_device_desc "C232HM-DDHSL-0"
 #ftdi_device_desc "C232HM-EDHSL-0"
+
+# Common PID for FT232H
 ftdi_vid_pid 0x0403 0x6014
 
-ftdi_layout_init 0x0008 0x000b
+# Layout
+# High data byte 0x40 configures red LED on ACBUS6 initially high (unlit, since active-low)
+# Low data byte 0x08 configures TMS on ACBUS3 initially high (asserted); TCK, TDI low
+# High direction byte 0x40 configures red LED on ACBUS6 as high (output)
+# Low direction byte 0x0b configures TDO on ACBUS2 as low (input)
+ftdi_layout_init 0x4008 0x400b
+
+# ---A*BUS-------CCCCCCCC|DDDDDDDD
+# --------\______76543210|76543210
+# LED	0x4000 = 01000000|00000000 = ACBUS6
+#GPIOL0	0x0010 = 00000000|00010000 = ADBUS4
+#GPIOL1	0x0020 = 00000000|00100000 = ADBUS5
+#GPIOL2	0x0040 = 00000000|01000000 = ADBUS6
+#GPIOL3	0x0080 = 00000000|10000000 = ADBUS7
+# -ndata treats the LED as active-low for expected behavior (toggle when transferring)
+ftdi_layout_signal LED -ndata 0x4000
+# Available for aliasing as desired
+ftdi_layout_signal GPIOL0 -data 0x0010 -oe 0x0010
+ftdi_layout_signal GPIOL1 -data 0x0020 -oe 0x0020
+ftdi_layout_signal GPIOL2 -data 0x0040 -oe 0x0040
+ftdi_layout_signal GPIOL3 -data 0x0080 -oe 0x0080
+
+# C232HM		FT232H	JTAG/Other
+# Num	Color	Name	Func
+# 1		Red		VCC		Optionally, can power the board if it is not using its own power supply.
+# 2		Orange	ADBUS0	TCK
+# 3		Yellow  ADBUS1	TDI
+# 4		Green	ADBUS2	TDO
+# 5		Brown   ADBUS3	TMS
+# 6		Grey	ADBUS4	GPIOL0
+# 7		Purple	ADBUS5	GPIOL1
+# 8		White	ADBUS6	GPIOL2
+# 9		Blue	ADBUS7	GPIOL3
+# 10	Black	GND		Connect to ground
diff --git a/tcl/interface/ftdi/calao-usb-a9260-c01.cfg b/tcl/interface/ftdi/calao-usb-a9260-c01.cfg
index d3da6b7..a23ddbf 100644
--- a/tcl/interface/ftdi/calao-usb-a9260-c01.cfg
+++ b/tcl/interface/ftdi/calao-usb-a9260-c01.cfg
@@ -10,7 +10,7 @@ echo "interface uses the same layout as configs that were verified. Please repor
 echo "experience with this file to openocd-devel mailing list, so it could be marked"
 echo "as working or fixed."
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "USB-A9260"
 ftdi_vid_pid 0x0403 0x6010
 
diff --git a/tcl/interface/ftdi/calao-usb-a9260-c02.cfg b/tcl/interface/ftdi/calao-usb-a9260-c02.cfg
index dc4dca8..67427c5 100644
--- a/tcl/interface/ftdi/calao-usb-a9260-c02.cfg
+++ b/tcl/interface/ftdi/calao-usb-a9260-c02.cfg
@@ -10,7 +10,7 @@ echo "interface uses the same layout as configs that were verified. Please repor
 echo "experience with this file to openocd-devel mailing list, so it could be marked"
 echo "as working or fixed."
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "USB-A9260"
 ftdi_vid_pid 0x0403 0x6001
 
diff --git a/tcl/interface/ftdi/cortino.cfg b/tcl/interface/ftdi/cortino.cfg
index 16ede61..2bc516c 100644
--- a/tcl/interface/ftdi/cortino.cfg
+++ b/tcl/interface/ftdi/cortino.cfg
@@ -4,7 +4,7 @@
 # http://www.hitex.com/index.php?id=cortino
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Cortino"
 ftdi_vid_pid 0x0640 0x0032
 
diff --git a/tcl/interface/ftdi/digilent-hs1.cfg b/tcl/interface/ftdi/digilent-hs1.cfg
index e27249b..dfba339 100644
--- a/tcl/interface/ftdi/digilent-hs1.cfg
+++ b/tcl/interface/ftdi/digilent-hs1.cfg
@@ -1,7 +1,7 @@
 # this supports JTAG-HS1 and JTAG-SMT1
 # (the later being the OEM on-board version)
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Digilent Adept USB Device"
 ftdi_vid_pid 0x0403 0x6010
 # channel 1 does not have any functionality
diff --git a/tcl/interface/ftdi/digilent-hs2.cfg b/tcl/interface/ftdi/digilent-hs2.cfg
index 2005b66..ae6ba01 100644
--- a/tcl/interface/ftdi/digilent-hs2.cfg
+++ b/tcl/interface/ftdi/digilent-hs2.cfg
@@ -1,6 +1,6 @@
 # this supports JTAG-HS2 (and apparently Nexys4 as well)
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Digilent Adept USB Device"
 ftdi_vid_pid 0x0403 0x6014
 
diff --git a/tcl/interface/ftdi/digilent_jtag_hs3.cfg b/tcl/interface/ftdi/digilent_jtag_hs3.cfg
index f7b8e57..7160bed 100644
--- a/tcl/interface/ftdi/digilent_jtag_hs3.cfg
+++ b/tcl/interface/ftdi/digilent_jtag_hs3.cfg
@@ -2,7 +2,7 @@
 # Digilent JTAG-HS3
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_vid_pid 0x0403 0x6014
 ftdi_device_desc "Digilent USB Device"
 
diff --git a/tcl/interface/ftdi/digilent_jtag_smt2.cfg b/tcl/interface/ftdi/digilent_jtag_smt2.cfg
index 014fe14..493ed6a 100644
--- a/tcl/interface/ftdi/digilent_jtag_smt2.cfg
+++ b/tcl/interface/ftdi/digilent_jtag_smt2.cfg
@@ -7,7 +7,7 @@
 # http://electronix.ru/forum/index.php?showtopic=114633&view=findpost&p=1215497 and ZedBoard schematics
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_vid_pid 0x0403 0x6014
 
 ftdi_layout_init 0x2088 0x3f8b
diff --git a/tcl/interface/ftdi/digilent_jtag_smt2_nc.cfg b/tcl/interface/ftdi/digilent_jtag_smt2_nc.cfg
index a83a008..bc783a4 100644
--- a/tcl/interface/ftdi/digilent_jtag_smt2_nc.cfg
+++ b/tcl/interface/ftdi/digilent_jtag_smt2_nc.cfg
@@ -10,7 +10,7 @@
 # Note that the digilent_jtag_smt2 layout does not work and hangs while
 # the ftdi_device_desc from digilent_hs2 is wrong.
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Digilent USB Device"
 ftdi_vid_pid 0x0403 0x6014
 ftdi_channel 0
diff --git a/tcl/interface/ftdi/dlp-usb1232h.cfg b/tcl/interface/ftdi/dlp-usb1232h.cfg
index f447771..9ddc2c8 100644
--- a/tcl/interface/ftdi/dlp-usb1232h.cfg
+++ b/tcl/interface/ftdi/dlp-usb1232h.cfg
@@ -12,7 +12,7 @@ echo "This file was not tested with real interface, it is based on schematics an
 echo "in ft2232.c. Please report your experience with this file to openocd-devel"
 echo "mailing list, so it could be marked as working or fixed."
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Dual RS232-HS"
 ftdi_vid_pid 0x0403 0x6010
 
diff --git a/tcl/interface/ftdi/dp_busblaster.cfg b/tcl/interface/ftdi/dp_busblaster.cfg
index 73827cf..86ab4d8 100644
--- a/tcl/interface/ftdi/dp_busblaster.cfg
+++ b/tcl/interface/ftdi/dp_busblaster.cfg
@@ -11,7 +11,7 @@
 echo "Info : If you need SWD support, flash KT-Link buffer from https://github.com/bharrisau/busblaster
 and use dp_busblaster_kt-link.cfg instead"
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Dual RS232-HS"
 ftdi_vid_pid 0x0403 0x6010
 
diff --git a/tcl/interface/ftdi/dp_busblaster_kt-link.cfg b/tcl/interface/ftdi/dp_busblaster_kt-link.cfg
index 2d27519..d49a4c9 100644
--- a/tcl/interface/ftdi/dp_busblaster_kt-link.cfg
+++ b/tcl/interface/ftdi/dp_busblaster_kt-link.cfg
@@ -9,7 +9,7 @@
 # http://dangerousprototypes.com/docs/Bus_Blaster
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Dual RS232-HS"
 ftdi_vid_pid 0x0403 0x6010
 
diff --git a/tcl/interface/ftdi/flossjtag-noeeprom.cfg b/tcl/interface/ftdi/flossjtag-noeeprom.cfg
index 18046e7..42ed18e 100644
--- a/tcl/interface/ftdi/flossjtag-noeeprom.cfg
+++ b/tcl/interface/ftdi/flossjtag-noeeprom.cfg
@@ -17,7 +17,7 @@ echo "This file was not tested with real interface, it is based on code in ft223
 echo "Please report your experience with this file to openocd-devel mailing list,"
 echo "so it could be marked as working or fixed."
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Dual RS232-HS"
 ftdi_vid_pid 0x0403 0x6010
 
diff --git a/tcl/interface/ftdi/flossjtag.cfg b/tcl/interface/ftdi/flossjtag.cfg
index 13e1f0b..c4ad81d 100644
--- a/tcl/interface/ftdi/flossjtag.cfg
+++ b/tcl/interface/ftdi/flossjtag.cfg
@@ -17,7 +17,7 @@ echo "This file was not tested with real interface, it is based on code in ft223
 echo "Please report your experience with this file to openocd-devel mailing list,"
 echo "so it could be marked as working or fixed."
 
-interface ftdi
+adapter driver ftdi
 ftdi_vid_pid 0x0403 0x6010
 ftdi_device_desc "FLOSS-JTAG"
 #ftdi_serial "FJ000001"
diff --git a/tcl/interface/ftdi/flyswatter.cfg b/tcl/interface/ftdi/flyswatter.cfg
index 56dab1f..5e9d481 100644
--- a/tcl/interface/ftdi/flyswatter.cfg
+++ b/tcl/interface/ftdi/flyswatter.cfg
@@ -4,7 +4,7 @@
 # http://www.tincantools.com/product.php?productid=16134
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Flyswatter"
 ftdi_vid_pid 0x0403 0x6010
 
diff --git a/tcl/interface/ftdi/flyswatter2.cfg b/tcl/interface/ftdi/flyswatter2.cfg
index 8bd4db4..45dd0ba 100644
--- a/tcl/interface/ftdi/flyswatter2.cfg
+++ b/tcl/interface/ftdi/flyswatter2.cfg
@@ -4,7 +4,7 @@
 # http://www.tincantools.com/product.php?productid=16153
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Flyswatter2"
 ftdi_vid_pid 0x0403 0x6010
 
diff --git a/tcl/interface/ftdi/ft232h-module-swd.cfg b/tcl/interface/ftdi/ft232h-module-swd.cfg
index d2bd1da..98a8c84 100644
--- a/tcl/interface/ftdi/ft232h-module-swd.cfg
+++ b/tcl/interface/ftdi/ft232h-module-swd.cfg
@@ -6,7 +6,7 @@
 #
 #
 
-interface ftdi
+adapter driver ftdi
 
 ftdi_vid_pid 0x0403 0x6014
 
@@ -15,7 +15,7 @@ ftdi_vid_pid 0x0403 0x6014
 ftdi_layout_init 0x0030 0x003b
 # 0xfff8 0xfffb
 # Those signal are only required on some platforms or may required to be
-# enabled explicitely (e.g. nrf5x chips).
+# enabled explicitly (e.g. nrf5x chips).
 ftdi_layout_signal nSRST -data 0x0010 -oe 0x0010
 ftdi_layout_signal nTRST -data 0x0020 -oe 0x0020
 
diff --git a/tcl/interface/ftdi/gw16042.cfg b/tcl/interface/ftdi/gw16042.cfg
index 90c6f7c..1288f77 100644
--- a/tcl/interface/ftdi/gw16042.cfg
+++ b/tcl/interface/ftdi/gw16042.cfg
@@ -17,7 +17,7 @@
 #   BDBUS1 TXD (input)
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "USB-JTAG"
 ftdi_vid_pid 0x0403 0x6010
 
diff --git a/tcl/interface/ftdi/hilscher_nxhx10_etm.cfg b/tcl/interface/ftdi/hilscher_nxhx10_etm.cfg
index b682333..3802f6d 100644
--- a/tcl/interface/ftdi/hilscher_nxhx10_etm.cfg
+++ b/tcl/interface/ftdi/hilscher_nxhx10_etm.cfg
@@ -9,7 +9,7 @@ echo "This file was not tested with real interface, it is based on code in ft223
 echo "Please report your experience with this file to openocd-devel mailing list,"
 echo "so it could be marked as working or fixed."
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "NXHX 10-ETM"
 ftdi_vid_pid 0x0640 0x0028
 
diff --git a/tcl/interface/ftdi/hilscher_nxhx500_etm.cfg b/tcl/interface/ftdi/hilscher_nxhx500_etm.cfg
index 3483030..f2e64b4 100644
--- a/tcl/interface/ftdi/hilscher_nxhx500_etm.cfg
+++ b/tcl/interface/ftdi/hilscher_nxhx500_etm.cfg
@@ -9,7 +9,7 @@ echo "This file was not tested with real interface, it is based on code in ft223
 echo "Please report your experience with this file to openocd-devel mailing list,"
 echo "so it could be marked as working or fixed."
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "NXHX 500-ETM"
 ftdi_vid_pid 0x0640 0x0028
 
diff --git a/tcl/interface/ftdi/hilscher_nxhx500_re.cfg b/tcl/interface/ftdi/hilscher_nxhx500_re.cfg
index b4cada0..38f3c69 100644
--- a/tcl/interface/ftdi/hilscher_nxhx500_re.cfg
+++ b/tcl/interface/ftdi/hilscher_nxhx500_re.cfg
@@ -9,7 +9,7 @@ echo "This file was not tested with real interface, it is based on code in ft223
 echo "Please report your experience with this file to openocd-devel mailing list,"
 echo "so it could be marked as working or fixed."
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "NXHX 500-RE"
 ftdi_vid_pid 0x0640 0x0028
 
diff --git a/tcl/interface/ftdi/hilscher_nxhx50_etm.cfg b/tcl/interface/ftdi/hilscher_nxhx50_etm.cfg
index 67074a2..bff081f 100644
--- a/tcl/interface/ftdi/hilscher_nxhx50_etm.cfg
+++ b/tcl/interface/ftdi/hilscher_nxhx50_etm.cfg
@@ -9,7 +9,7 @@ echo "This file was not tested with real interface, it is based on code in ft223
 echo "Please report your experience with this file to openocd-devel mailing list,"
 echo "so it could be marked as working or fixed."
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "NXHX 50-ETM"
 ftdi_vid_pid 0x0640 0x0028
 
diff --git a/tcl/interface/ftdi/hilscher_nxhx50_re.cfg b/tcl/interface/ftdi/hilscher_nxhx50_re.cfg
index 966dcd8..f9fbd01 100644
--- a/tcl/interface/ftdi/hilscher_nxhx50_re.cfg
+++ b/tcl/interface/ftdi/hilscher_nxhx50_re.cfg
@@ -9,7 +9,7 @@ echo "This file was not tested with real interface, it is based on code in ft223
 echo "Please report your experience with this file to openocd-devel mailing list,"
 echo "so it could be marked as working or fixed."
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "NXHX50-RE"
 ftdi_vid_pid 0x0640 0x0028
 
diff --git a/tcl/interface/ftdi/hitex_lpc1768stick.cfg b/tcl/interface/ftdi/hitex_lpc1768stick.cfg
index f22d4f7..9fe80f1 100644
--- a/tcl/interface/ftdi/hitex_lpc1768stick.cfg
+++ b/tcl/interface/ftdi/hitex_lpc1768stick.cfg
@@ -5,11 +5,10 @@
 #
 
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "LPC1768-Stick"
 ftdi_vid_pid 0x0640 0x0026
 
 ftdi_layout_init 0x0388 0x038b
 ftdi_layout_signal nTRST -data 0x0100
 ftdi_layout_signal nSRST -data 0x0080 -noe 0x200
-
diff --git a/tcl/interface/ftdi/hitex_str9-comstick.cfg b/tcl/interface/ftdi/hitex_str9-comstick.cfg
index c46f032..2b3dc36 100644
--- a/tcl/interface/ftdi/hitex_str9-comstick.cfg
+++ b/tcl/interface/ftdi/hitex_str9-comstick.cfg
@@ -4,7 +4,7 @@
 # http://www.hitex.com/index.php?id=383
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "STR9-comStick"
 ftdi_vid_pid 0x0640 0x002c
 
diff --git a/tcl/interface/ftdi/icebear.cfg b/tcl/interface/ftdi/icebear.cfg
index 2c03d41..04c2731 100644
--- a/tcl/interface/ftdi/icebear.cfg
+++ b/tcl/interface/ftdi/icebear.cfg
@@ -9,7 +9,7 @@ echo "This file was not tested with real interface, it is based on code in ft223
 echo "Please report your experience with this file to openocd-devel mailing list,"
 echo "so it could be marked as working or fixed."
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "ICEbear JTAG adapter"
 ftdi_vid_pid 0x0403 0xc140
 
diff --git a/tcl/interface/ftdi/imx8mp-evk.cfg b/tcl/interface/ftdi/imx8mp-evk.cfg
new file mode 100644
index 0000000..4e04e8c
--- /dev/null
+++ b/tcl/interface/ftdi/imx8mp-evk.cfg
@@ -0,0 +1,28 @@
+#
+# Configuration file for NXP MC-IMX8MP-EVK on-board internal JTAG
+#
+# Using this interface requires enabling "remote mode" for the board using the
+# NXP bcu tool (see https://github.com/NXPmicro/bcu)
+#
+#	bcu set_gpio remote_en 1 -board=imx8mpevk
+#
+# The REMOTE_EN gpio is accessible through the same FTDI adapter but it's
+# behind an I2C GPIO expander.
+#
+
+adapter driver ftdi
+ftdi_vid_pid 0x0403 0x6011
+ftdi_channel 0
+
+ftdi_layout_init 0x00f8 0x000b
+
+ftdi_layout_signal RESET_B	-data 0x0010 -oe 0x0010
+# Called SYS_nRST in schematics
+ftdi_layout_signal nSRST	-data 0x0020 -oe 0x0020
+ftdi_layout_signal IO_nRST	-data 0x0040 -oe 0x0040
+ftdi_layout_signal ONOFF_B	-data 0x0080 -oe 0x0080
+
+ftdi_layout_signal GPIO1	-data 0x0100 -oe 0x0100
+ftdi_layout_signal GPIO2	-data 0x0200 -oe 0x0200
+ftdi_layout_signal GPIO3	-data 0x0400 -oe 0x0400
+ftdi_layout_signal GPIO4	-data 0x0800 -oe 0x0800
diff --git a/tcl/interface/ftdi/incircuit-icprog.cfg b/tcl/interface/ftdi/incircuit-icprog.cfg
index 5e90a70..e0bd5ef 100644
--- a/tcl/interface/ftdi/incircuit-icprog.cfg
+++ b/tcl/interface/ftdi/incircuit-icprog.cfg
@@ -6,7 +6,7 @@
 # http://wiki.in-circuit.de/images/0/06/610000158A_openocd.pdf
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_vid_pid 0x0403 0x6010
 
 ftdi_layout_init 0x0508 0x0f1b
diff --git a/tcl/interface/ftdi/iotlab-usb.cfg b/tcl/interface/ftdi/iotlab-usb.cfg
index fbbad0c..caa0596 100644
--- a/tcl/interface/ftdi/iotlab-usb.cfg
+++ b/tcl/interface/ftdi/iotlab-usb.cfg
@@ -3,7 +3,7 @@
 # https://github.com/iot-lab/iot-lab/wiki
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_vid_pid 0x0403 0x6010
 
 ftdi_layout_init 0x0008 0x000b
diff --git a/tcl/interface/ftdi/isodebug.cfg b/tcl/interface/ftdi/isodebug.cfg
new file mode 100644
index 0000000..ead2864
--- /dev/null
+++ b/tcl/interface/ftdi/isodebug.cfg
@@ -0,0 +1,27 @@
+# isodebug v1
+# 5 kV isolated JTAG/SWD + UART adapter by Unjo AB
+
+adapter driver ftdi
+ftdi_vid_pid 0x22b7 0x150d
+
+ftdi_layout_init 0x0ff8 0xfffb
+
+ftdi_layout_signal LED -ndata 0x0100
+ftdi_layout_signal nTRST -data 0x0200
+ftdi_layout_signal nSRST -noe 0x0400
+ftdi_layout_signal SWDIO_OE -data 0x0008
+
+# Mode signals, either of these needs to be high to drive the JTAG/SWD pins.
+# The power-on state is low for both signals but the init setting above sets
+# JTAG_EN high.
+ftdi_layout_signal SWD_EN -data 0x1000
+ftdi_layout_signal JTAG_EN -data 0x0800
+
+# In SWD mode, the JTAG_EN signal doubles as SWO_EN_N which switches the
+# second FTDI channel UART RxD to the SWO pin instead of the separate RxD
+# pin. Note that the default init state has this pin high so when OpenOCD
+# starts in SWD mode, SWO is by default disabled. To enable SWO tracing,
+# issue the command 'ftdi_set_signal SWO_EN 1' where tracing is configured.
+# To switch back to using the separate UART, SWO_EN needs to be disabled
+# before exiting OpenOCD, or the adapter replugged.
+ftdi_layout_signal SWO_EN -nalias JTAG_EN
diff --git a/tcl/interface/ftdi/jtag-lock-pick_tiny_2.cfg b/tcl/interface/ftdi/jtag-lock-pick_tiny_2.cfg
index c5e5db4..82eeaa7 100644
--- a/tcl/interface/ftdi/jtag-lock-pick_tiny_2.cfg
+++ b/tcl/interface/ftdi/jtag-lock-pick_tiny_2.cfg
@@ -4,7 +4,7 @@
 # http://www.distortec.com
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "JTAG-lock-pick Tiny 2"
 ftdi_vid_pid 0x0403 0x8220
 
diff --git a/tcl/interface/ftdi/jtagkey.cfg b/tcl/interface/ftdi/jtagkey.cfg
index 7b87e6d..06463ab 100644
--- a/tcl/interface/ftdi/jtagkey.cfg
+++ b/tcl/interface/ftdi/jtagkey.cfg
@@ -4,7 +4,7 @@
 # http://www.amontec.com/jtagkey.shtml
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Amontec JTAGkey"
 ftdi_vid_pid 0x0403 0xcff8
 
diff --git a/tcl/interface/ftdi/jtagkey2.cfg b/tcl/interface/ftdi/jtagkey2.cfg
index c6c2b32..ba151d3 100644
--- a/tcl/interface/ftdi/jtagkey2.cfg
+++ b/tcl/interface/ftdi/jtagkey2.cfg
@@ -4,7 +4,7 @@
 # http://www.amontec.com/jtagkey2.shtml
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Amontec JTAGkey-2"
 ftdi_vid_pid 0x0403 0xcff8
 
diff --git a/tcl/interface/ftdi/jtagkey2p.cfg b/tcl/interface/ftdi/jtagkey2p.cfg
index dc9c456..acb5047 100644
--- a/tcl/interface/ftdi/jtagkey2p.cfg
+++ b/tcl/interface/ftdi/jtagkey2p.cfg
@@ -4,7 +4,7 @@
 # http://www.amontec.com/jtagkey2p.shtml
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Amontec JTAGkey-2P"
 ftdi_vid_pid 0x0403 0xcff8
 
diff --git a/tcl/interface/ftdi/kt-link.cfg b/tcl/interface/ftdi/kt-link.cfg
index 1f28d3a..5fc5db9 100644
--- a/tcl/interface/ftdi/kt-link.cfg
+++ b/tcl/interface/ftdi/kt-link.cfg
@@ -4,7 +4,7 @@
 # http://www.kristech.eu
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "KT-LINK"
 ftdi_vid_pid 0x0403 0xbbe2
 
diff --git a/tcl/interface/ftdi/lisa-l.cfg b/tcl/interface/ftdi/lisa-l.cfg
index 67002bb..4e52f7b 100644
--- a/tcl/interface/ftdi/lisa-l.cfg
+++ b/tcl/interface/ftdi/lisa-l.cfg
@@ -9,7 +9,7 @@ echo "This file was not tested with real interface, it is based on schematics an
 echo "in ft2232.c. Please report your experience with this file to openocd-devel"
 echo "mailing list, so it could be marked as working or fixed."
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Lisa/L"
 ftdi_vid_pid 0x0403 0x6010
 ftdi_channel 1
diff --git a/tcl/interface/ftdi/luminary-icdi.cfg b/tcl/interface/ftdi/luminary-icdi.cfg
index 2eea806..8bc783e 100644
--- a/tcl/interface/ftdi/luminary-icdi.cfg
+++ b/tcl/interface/ftdi/luminary-icdi.cfg
@@ -15,7 +15,7 @@
 # http://www.luminarymicro.com/products/ek-lm3s9b92.html
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Luminary Micro ICDI Board"
 ftdi_vid_pid 0x0403 0xbcda
 
diff --git a/tcl/interface/ftdi/luminary-lm3s811.cfg b/tcl/interface/ftdi/luminary-lm3s811.cfg
index 543b1e0..aac915e 100644
--- a/tcl/interface/ftdi/luminary-lm3s811.cfg
+++ b/tcl/interface/ftdi/luminary-lm3s811.cfg
@@ -11,7 +11,7 @@
 # need to use the "luminary_icdi" layout to work correctly.
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "LM3S811 Evaluation Board"
 ftdi_vid_pid 0x0403 0xbcd9
 
diff --git a/tcl/interface/ftdi/luminary.cfg b/tcl/interface/ftdi/luminary.cfg
index 20b5422..5e34f8c 100644
--- a/tcl/interface/ftdi/luminary.cfg
+++ b/tcl/interface/ftdi/luminary.cfg
@@ -24,7 +24,7 @@
 # firmware via the ITM module as well as profile data.
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Stellaris Evaluation Board"
 ftdi_vid_pid 0x0403 0xbcd9
 
diff --git a/tcl/interface/ftdi/m53evk.cfg b/tcl/interface/ftdi/m53evk.cfg
index 2b97270..6597f2d 100644
--- a/tcl/interface/ftdi/m53evk.cfg
+++ b/tcl/interface/ftdi/m53evk.cfg
@@ -4,7 +4,7 @@
 # http://www.denx-cs.de/?q=M53EVK
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Dual RS232-HS"
 ftdi_vid_pid 0x0403 0x6010
 
diff --git a/tcl/interface/ftdi/mbftdi.cfg b/tcl/interface/ftdi/mbftdi.cfg
index d051ccc..c0ff865 100644
--- a/tcl/interface/ftdi/mbftdi.cfg
+++ b/tcl/interface/ftdi/mbftdi.cfg
@@ -9,7 +9,7 @@
 # and http://www.marsohod.org/plata-marsokhod3 for details.
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Dual RS232-HS"
 ftdi_vid_pid 0x0403 0x6010
 
diff --git a/tcl/interface/ftdi/minimodule-swd.cfg b/tcl/interface/ftdi/minimodule-swd.cfg
index 5f0b212..7ab4650 100644
--- a/tcl/interface/ftdi/minimodule-swd.cfg
+++ b/tcl/interface/ftdi/minimodule-swd.cfg
@@ -34,7 +34,7 @@ Supports SWD using the FT2232H or FT4232H minimodule.
 # CN2-22  -  nRESET
 #
 
-interface ftdi
+adapter driver ftdi
 
 #Select your module type and channel
 
diff --git a/tcl/interface/ftdi/minimodule.cfg b/tcl/interface/ftdi/minimodule.cfg
index 7df096d..5dcce1f 100644
--- a/tcl/interface/ftdi/minimodule.cfg
+++ b/tcl/interface/ftdi/minimodule.cfg
@@ -4,7 +4,7 @@
 # http://www.ftdichip.com/Support/Documents/DataSheets/Modules/DS_FT2232H_Mini_Module.pdf
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "FT2232H MiniModule"
 ftdi_vid_pid 0x0403 0x6010
 
diff --git a/tcl/interface/ftdi/minispartan6.cfg b/tcl/interface/ftdi/minispartan6.cfg
index 8f16011..97a6abe 100644
--- a/tcl/interface/ftdi/minispartan6.cfg
+++ b/tcl/interface/ftdi/minispartan6.cfg
@@ -1,6 +1,6 @@
 # https://www.scarabhardware.com/minispartan6/
 # https://github.com/scarabhardware/miniSpartan6-plus/raw/master/miniSpartan6%2B_Rev_B.pdf
-interface ftdi
+adapter driver ftdi
 # The miniSpartan6+ sadly doesn't have a custom device description, so we just
 # have to hope you got it right.
 #ftdi_device_desc "Dual RS232-HS"
@@ -12,4 +12,4 @@ ftdi_layout_init 0x0008 0x000b
 reset_config none
 # this generally works fast: the fpga can handle 30MHz, the spi flash can handle
 # 54MHz with simple read, no dummy cycles, and wait-for-write-completion
-adapter_khz 30000
+adapter speed 30000
diff --git a/tcl/interface/ftdi/neodb.cfg b/tcl/interface/ftdi/neodb.cfg
index 6cc8ccf..1cfb352 100644
--- a/tcl/interface/ftdi/neodb.cfg
+++ b/tcl/interface/ftdi/neodb.cfg
@@ -4,7 +4,7 @@
 # http://wiki.openmoko.org/wiki/Debug_Board_v3
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Debug Board for Neo1973"
 ftdi_vid_pid 0x1457 0x5118
 
diff --git a/tcl/interface/ftdi/ngxtech.cfg b/tcl/interface/ftdi/ngxtech.cfg
index 9eaa3c5..3aa79ab 100644
--- a/tcl/interface/ftdi/ngxtech.cfg
+++ b/tcl/interface/ftdi/ngxtech.cfg
@@ -10,7 +10,7 @@ echo "interface uses the same layout as configs that were verified. Please repor
 echo "experience with this file to openocd-devel mailing list, so it could be marked"
 echo "as working or fixed."
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "NGX JTAG"
 ftdi_vid_pid 0x0403 0x6010
 
diff --git a/tcl/interface/ftdi/olimex-arm-usb-ocd-h.cfg b/tcl/interface/ftdi/olimex-arm-usb-ocd-h.cfg
index 5b27d38..c8e3bef 100644
--- a/tcl/interface/ftdi/olimex-arm-usb-ocd-h.cfg
+++ b/tcl/interface/ftdi/olimex-arm-usb-ocd-h.cfg
@@ -4,7 +4,7 @@
 # http://www.olimex.com/dev/arm-usb-ocd-h.html
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-OCD-H"
 ftdi_vid_pid 0x15ba 0x002b
 
diff --git a/tcl/interface/ftdi/olimex-arm-usb-ocd.cfg b/tcl/interface/ftdi/olimex-arm-usb-ocd.cfg
index e1aeeea..f9126d4 100644
--- a/tcl/interface/ftdi/olimex-arm-usb-ocd.cfg
+++ b/tcl/interface/ftdi/olimex-arm-usb-ocd.cfg
@@ -4,7 +4,7 @@
 # http://www.olimex.com/dev/arm-usb-ocd.html
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Olimex OpenOCD JTAG"
 ftdi_vid_pid 0x15ba 0x0003
 
diff --git a/tcl/interface/ftdi/olimex-arm-usb-tiny-h.cfg b/tcl/interface/ftdi/olimex-arm-usb-tiny-h.cfg
index f77c24b..eac25b6 100644
--- a/tcl/interface/ftdi/olimex-arm-usb-tiny-h.cfg
+++ b/tcl/interface/ftdi/olimex-arm-usb-tiny-h.cfg
@@ -4,7 +4,7 @@
 # http://www.olimex.com/dev/arm-usb-tiny-h.html
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
 ftdi_vid_pid 0x15ba 0x002a
 
diff --git a/tcl/interface/ftdi/olimex-jtag-tiny.cfg b/tcl/interface/ftdi/olimex-jtag-tiny.cfg
index b3c6a71..4811f4d 100644
--- a/tcl/interface/ftdi/olimex-jtag-tiny.cfg
+++ b/tcl/interface/ftdi/olimex-jtag-tiny.cfg
@@ -4,7 +4,7 @@
 # http://www.olimex.com/dev/arm-usb-tiny.html
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Olimex OpenOCD JTAG TINY"
 ftdi_vid_pid 0x15ba 0x0004
 
diff --git a/tcl/interface/ftdi/oocdlink.cfg b/tcl/interface/ftdi/oocdlink.cfg
index fc09a16..deba4a5 100644
--- a/tcl/interface/ftdi/oocdlink.cfg
+++ b/tcl/interface/ftdi/oocdlink.cfg
@@ -10,7 +10,7 @@ echo "interface uses the same layout as configs that were verified. Please repor
 echo "experience with this file to openocd-devel mailing list, so it could be marked"
 echo "as working or fixed."
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "OOCDLink"
 ftdi_vid_pid 0x0403 0xbaf8
 
diff --git a/tcl/interface/ftdi/opendous_ftdi.cfg b/tcl/interface/ftdi/opendous_ftdi.cfg
index 6a12d72..50f32fb 100644
--- a/tcl/interface/ftdi/opendous_ftdi.cfg
+++ b/tcl/interface/ftdi/opendous_ftdi.cfg
@@ -7,7 +7,7 @@
 # (and it has a different pid number).
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Dual RS232-HS"
 ftdi_vid_pid 0x0403 0x6010
 ftdi_channel 1
diff --git a/tcl/interface/ftdi/openocd-usb-hs.cfg b/tcl/interface/ftdi/openocd-usb-hs.cfg
index 37a717d..6f67689 100644
--- a/tcl/interface/ftdi/openocd-usb-hs.cfg
+++ b/tcl/interface/ftdi/openocd-usb-hs.cfg
@@ -4,7 +4,7 @@
 # http://shop.embedded-projects.net/index.php?module=artikel&action=artikel&id=14
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Dual RS232-HS"
 ftdi_vid_pid 0x0403 0x6010
 
diff --git a/tcl/interface/ftdi/openocd-usb.cfg b/tcl/interface/ftdi/openocd-usb.cfg
index ff537c7..ed80a05 100644
--- a/tcl/interface/ftdi/openocd-usb.cfg
+++ b/tcl/interface/ftdi/openocd-usb.cfg
@@ -4,7 +4,7 @@
 # http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Dual RS232"
 ftdi_vid_pid 0x0403 0x6010
 
diff --git a/tcl/interface/ftdi/openrd.cfg b/tcl/interface/ftdi/openrd.cfg
index 9ec5b5f..535c5e8 100644
--- a/tcl/interface/ftdi/openrd.cfg
+++ b/tcl/interface/ftdi/openrd.cfg
@@ -4,7 +4,7 @@
 # http://www.marvell.com/products/embedded_processors/developer/kirkwood/openrd.jsp
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "OpenRD JTAGKey FT2232D B"
 ftdi_vid_pid 0x0403 0x9e90
 ftdi_channel 0
diff --git a/tcl/interface/ftdi/pipistrello.cfg b/tcl/interface/ftdi/pipistrello.cfg
index 5ee5be5..2074924 100644
--- a/tcl/interface/ftdi/pipistrello.cfg
+++ b/tcl/interface/ftdi/pipistrello.cfg
@@ -1,6 +1,6 @@
 # http://pipistrello.saanlima.com/
 # http://www.saanlima.com/download/pipistrello-v2.0/pipistrello_v2_schematic.pdf
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Pipistrello LX45"
 ftdi_vid_pid 0x0403 0x6010
 # interface 1 is the uart
@@ -10,4 +10,4 @@ ftdi_layout_init 0x0008 0x000b
 reset_config none
 # this generally works fast: the fpga can handle 30MHz, the spi flash can handle
 # 54MHz with simple read, no dummy cycles, and wait-for-write-completion
-adapter_khz 10000
+adapter speed 10000
diff --git a/tcl/interface/ftdi/redbee-econotag.cfg b/tcl/interface/ftdi/redbee-econotag.cfg
index 70c30d6..b6f6d23 100644
--- a/tcl/interface/ftdi/redbee-econotag.cfg
+++ b/tcl/interface/ftdi/redbee-econotag.cfg
@@ -13,7 +13,7 @@ echo "This file was not tested with real interface, it is based on code in ft223
 echo "Please report your experience with this file to openocd-devel mailing list,"
 echo "so it could be marked as working or fixed."
 
-interface ftdi
+adapter driver ftdi
 ftdi_vid_pid 0x0403 0x6010
 
 ftdi_layout_init 0x0c08 0x0c2b
diff --git a/tcl/interface/ftdi/redbee-usb.cfg b/tcl/interface/ftdi/redbee-usb.cfg
index b79300d..52ab93e 100644
--- a/tcl/interface/ftdi/redbee-usb.cfg
+++ b/tcl/interface/ftdi/redbee-usb.cfg
@@ -13,7 +13,7 @@ echo "This file was not tested with real interface, it is based on code in ft223
 echo "Please report your experience with this file to openocd-devel mailing list,"
 echo "so it could be marked as working or fixed."
 
-interface ftdi
+adapter driver ftdi
 ftdi_vid_pid 0x0403 0x6010
 ftdi_channel 1
 
diff --git a/tcl/interface/ftdi/sheevaplug.cfg b/tcl/interface/ftdi/sheevaplug.cfg
index 625aad3..d4ec72e 100644
--- a/tcl/interface/ftdi/sheevaplug.cfg
+++ b/tcl/interface/ftdi/sheevaplug.cfg
@@ -4,7 +4,7 @@
 # http://www.marvell.com/products/embedded_processors/developer/kirkwood/sheevaplug.jsp
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "SheevaPlug JTAGKey FT2232D B"
 ftdi_vid_pid 0x9e88 0x9e8f
 ftdi_channel 0
diff --git a/tcl/interface/ftdi/signalyzer-lite.cfg b/tcl/interface/ftdi/signalyzer-lite.cfg
index 4988a3b..4778420 100644
--- a/tcl/interface/ftdi/signalyzer-lite.cfg
+++ b/tcl/interface/ftdi/signalyzer-lite.cfg
@@ -9,7 +9,7 @@ echo "This file was not tested with real interface, it is based on code in ft223
 echo "Please report your experience with this file to openocd-devel mailing list,"
 echo "so it could be marked as working or fixed."
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Signalyzer LITE"
 ftdi_vid_pid 0x0403 0xbca1
 
diff --git a/tcl/interface/ftdi/signalyzer.cfg b/tcl/interface/ftdi/signalyzer.cfg
index e2629be..2439298 100644
--- a/tcl/interface/ftdi/signalyzer.cfg
+++ b/tcl/interface/ftdi/signalyzer.cfg
@@ -9,7 +9,7 @@ echo "This file was not tested with real interface, it is based on code in ft223
 echo "Please report your experience with this file to openocd-devel mailing list,"
 echo "so it could be marked as working or fixed."
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Signalyzer"
 ftdi_vid_pid 0x0403 0xbca0
 
diff --git a/tcl/interface/ftdi/stm32-stick.cfg b/tcl/interface/ftdi/stm32-stick.cfg
index 2aff1fe..7ae02bd 100644
--- a/tcl/interface/ftdi/stm32-stick.cfg
+++ b/tcl/interface/ftdi/stm32-stick.cfg
@@ -4,7 +4,7 @@
 # http://www.hitex.com/index.php?id=340
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "STM32-PerformanceStick"
 ftdi_vid_pid 0x0640 0x002d
 
diff --git a/tcl/interface/ftdi/ti-icdi.cfg b/tcl/interface/ftdi/ti-icdi.cfg
index 6af809c..55085ea 100644
--- a/tcl/interface/ftdi/ti-icdi.cfg
+++ b/tcl/interface/ftdi/ti-icdi.cfg
@@ -6,7 +6,7 @@
 # support) but the USB IDs are different.
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_vid_pid 0x0451 0xc32a
 
 ftdi_layout_init 0x00a8 0x00eb
diff --git a/tcl/interface/ftdi/tumpa-lite.cfg b/tcl/interface/ftdi/tumpa-lite.cfg
index 657515a..7f576e9 100644
--- a/tcl/interface/ftdi/tumpa-lite.cfg
+++ b/tcl/interface/ftdi/tumpa-lite.cfg
@@ -4,7 +4,7 @@
 # http://www.diygadget.com/tiao-usb-multi-protocol-adapter-lite-jtag-spi-i2c-serial.html
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_vid_pid 0x0403 0x8a99
 
 ftdi_layout_init 0x0038 0x087b
diff --git a/tcl/interface/ftdi/tumpa.cfg b/tcl/interface/ftdi/tumpa.cfg
index e4b59b1..1a4e3cd 100644
--- a/tcl/interface/ftdi/tumpa.cfg
+++ b/tcl/interface/ftdi/tumpa.cfg
@@ -4,7 +4,7 @@
 # http://www.diygadget.com/tiao-usb-multi-protocol-adapter-jtag-spi-i2c-serial.html
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_vid_pid 0x0403 0x8a98 0x0403 0x6010
 
 ftdi_layout_init 0x0038 0x087b
diff --git a/tcl/interface/ftdi/turtelizer2-revB.cfg b/tcl/interface/ftdi/turtelizer2-revB.cfg
index 4584040..34ae861 100644
--- a/tcl/interface/ftdi/turtelizer2-revB.cfg
+++ b/tcl/interface/ftdi/turtelizer2-revB.cfg
@@ -9,7 +9,7 @@ echo "This file was not tested with real interface, it is based on schematics an
 echo "in ft2232.c. Please report your experience with this file to openocd-devel"
 echo "mailing list, so it could be marked as working or fixed."
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Turtelizer JTAG/RS232 Adapter"
 ftdi_vid_pid 0x0403 0xbdc8
 
diff --git a/tcl/interface/ftdi/turtelizer2-revC.cfg b/tcl/interface/ftdi/turtelizer2-revC.cfg
index 918ac49..f5192fb 100644
--- a/tcl/interface/ftdi/turtelizer2-revC.cfg
+++ b/tcl/interface/ftdi/turtelizer2-revC.cfg
@@ -4,7 +4,7 @@
 # http://www.ethernut.de/en/hardware/turtelizer/index.html
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "Turtelizer JTAG/RS232 Adapter"
 ftdi_vid_pid 0x0403 0xbdc8
 
diff --git a/tcl/interface/ftdi/um232h.cfg b/tcl/interface/ftdi/um232h.cfg
index 6ba6f43..2dabbec 100644
--- a/tcl/interface/ftdi/um232h.cfg
+++ b/tcl/interface/ftdi/um232h.cfg
@@ -7,7 +7,7 @@
 # Note that UM232H and UM232H-B are 3.3V only.
 #
 
-interface ftdi
+adapter driver ftdi
 #ftdi_device_desc "UM232H"
 ftdi_vid_pid 0x0403 0x6014
 
diff --git a/tcl/interface/ftdi/vpaclink.cfg b/tcl/interface/ftdi/vpaclink.cfg
index 2057619..ed4895a 100644
--- a/tcl/interface/ftdi/vpaclink.cfg
+++ b/tcl/interface/ftdi/vpaclink.cfg
@@ -10,7 +10,7 @@ echo "interface uses the same layout as configs that were verified. Please repor
 echo "experience with this file to openocd-devel mailing list, so it could be marked"
 echo "as working or fixed."
 
-interface ftdi
+adapter driver ftdi
 ftdi_device_desc "VPACLink"
 ftdi_vid_pid 0x0403 0x6010
 
diff --git a/tcl/interface/ftdi/xds100v2.cfg b/tcl/interface/ftdi/xds100v2.cfg
index 2628aa0..860a758 100644
--- a/tcl/interface/ftdi/xds100v2.cfg
+++ b/tcl/interface/ftdi/xds100v2.cfg
@@ -7,7 +7,7 @@
 # to the registered TI users.
 #
 
-interface ftdi
+adapter driver ftdi
 ftdi_vid_pid 0x0403 0xa6d0 0x0403 0x6010
 
 ftdi_layout_init 0x0038 0x597b
diff --git a/tcl/interface/imx-native.cfg b/tcl/interface/imx-native.cfg
index c2f80eb..9e1f38d 100644
--- a/tcl/interface/imx-native.cfg
+++ b/tcl/interface/imx-native.cfg
@@ -7,7 +7,7 @@
 #
 #
 
-interface imx_gpio
+adapter driver imx_gpio
 
 # For most IMX processors 0x0209c000
 imx_gpio_peripheral_base 0x0209c000
@@ -32,4 +32,4 @@ imx_gpio_swd_nums 1 6
 # reset_config srst_only srst_push_pull
 
 # or if you have both connected,
-# reset_config trst_and_srst srst_push_pull
-\ No newline at end of file
+# reset_config trst_and_srst srst_push_pull
diff --git a/tcl/interface/jlink.cfg b/tcl/interface/jlink.cfg
index a4f9ddd..51f420b 100644
--- a/tcl/interface/jlink.cfg
+++ b/tcl/interface/jlink.cfg
@@ -4,7 +4,7 @@
 # http://www.segger.com/jlink.html
 #
 
-interface jlink
+adapter driver jlink
 
 # The serial number can be used to select a specific device in case more than
 # one is connected to the host.
diff --git a/tcl/interface/jtag_vpi.cfg b/tcl/interface/jtag_vpi.cfg
index a37a11e..e665a63 100644
--- a/tcl/interface/jtag_vpi.cfg
+++ b/tcl/interface/jtag_vpi.cfg
@@ -1,4 +1,4 @@
-interface jtag_vpi
+adapter driver jtag_vpi
 
 # Set the VPI JTAG server port
 if { [info exists VPI_PORT] } {
diff --git a/tcl/interface/kitprog.cfg b/tcl/interface/kitprog.cfg
index 9449714..29fce48 100644
--- a/tcl/interface/kitprog.cfg
+++ b/tcl/interface/kitprog.cfg
@@ -6,7 +6,7 @@
 # interface driver or switch the KitProg to KitProg mode.
 #
 
-interface kitprog
+adapter driver kitprog
 
 # Optionally specify the serial number of the KitProg you want to use.
 #kitprog_serial 1926402735485200
diff --git a/tcl/interface/nds32-aice.cfg b/tcl/interface/nds32-aice.cfg
index 5363b4c..3b21025 100644
--- a/tcl/interface/nds32-aice.cfg
+++ b/tcl/interface/nds32-aice.cfg
@@ -4,12 +4,12 @@
 # http://www.andestech.com
 #
 
-interface aice
+adapter driver aice
 aice desc "Andes AICE adapter"
 aice serial "C001-42163"
 aice vid_pid 0x1CFC 0x0000
 aice port aice_usb
 reset_config trst_and_srst
-adapter_khz 24000
+adapter speed 24000
 aice retry_times 50
 aice count_to_check_dbger 30
diff --git a/tcl/interface/opendous.cfg b/tcl/interface/opendous.cfg
index 21ced6f..23fddc6 100644
--- a/tcl/interface/opendous.cfg
+++ b/tcl/interface/opendous.cfg
@@ -4,4 +4,4 @@
 # http://code.google.com/p/opendous-jtag/
 #
 
-interface opendous
+adapter driver opendous
diff --git a/tcl/interface/openjtag.cfg b/tcl/interface/openjtag.cfg
index b20c22b..9a5827b 100644
--- a/tcl/interface/openjtag.cfg
+++ b/tcl/interface/openjtag.cfg
@@ -4,5 +4,5 @@
 # www.openjtag.org
 #
 
-interface openjtag
-openjtag_device_desc "Open JTAG Project"
-\ No newline at end of file
+adapter driver openjtag
+openjtag_device_desc "Open JTAG Project"
diff --git a/tcl/interface/osbdm.cfg b/tcl/interface/osbdm.cfg
index e88ce50..6e88c07 100644
--- a/tcl/interface/osbdm.cfg
+++ b/tcl/interface/osbdm.cfg
@@ -3,5 +3,5 @@
 #
 # http://pemicro.com/osbdm/
 #
-interface osbdm
+adapter driver osbdm
 reset_config srst_only
diff --git a/tcl/interface/parport.cfg b/tcl/interface/parport.cfg
index ae3f8f1..4c0b260 100644
--- a/tcl/interface/parport.cfg
+++ b/tcl/interface/parport.cfg
@@ -14,6 +14,6 @@ if { [info exists PARPORTADDR] } {
    }
 }
 
-interface parport
+adapter driver parport
 parport_port $_PARPORTADDR
 parport_cable wiggler
diff --git a/tcl/interface/parport_dlc5.cfg b/tcl/interface/parport_dlc5.cfg
index 9834580..e9beaaf 100644
--- a/tcl/interface/parport_dlc5.cfg
+++ b/tcl/interface/parport_dlc5.cfg
@@ -10,7 +10,6 @@ if { [info exists PARPORTADDR] } {
    set _PARPORTADDR 0
 }
 
-interface parport
+adapter driver parport
 parport_port $_PARPORTADDR
 parport_cable dlc5
-
diff --git a/tcl/interface/raspberrypi-native.cfg b/tcl/interface/raspberrypi-native.cfg
index c63dfdb..2d0547f 100644
--- a/tcl/interface/raspberrypi-native.cfg
+++ b/tcl/interface/raspberrypi-native.cfg
@@ -8,7 +8,7 @@
 # Do not forget the GND connection, pin 6 of the expansion header.
 #
 
-interface bcm2835gpio
+adapter driver bcm2835gpio
 
 bcm2835gpio_peripheral_base 0x20000000
 
diff --git a/tcl/interface/raspberrypi2-native.cfg b/tcl/interface/raspberrypi2-native.cfg
index 26a31c5..e53b0f3 100644
--- a/tcl/interface/raspberrypi2-native.cfg
+++ b/tcl/interface/raspberrypi2-native.cfg
@@ -8,7 +8,7 @@
 # Do not forget the GND connection, pin 6 of the expansion header.
 #
 
-interface bcm2835gpio
+adapter driver bcm2835gpio
 
 bcm2835gpio_peripheral_base 0x3F000000
 
diff --git a/tcl/interface/rlink.cfg b/tcl/interface/rlink.cfg
index 2f13cc4..29d3ce5 100644
--- a/tcl/interface/rlink.cfg
+++ b/tcl/interface/rlink.cfg
@@ -4,5 +4,4 @@
 # http://www.mcu-raisonance.com/~rlink-debugger-programmer__microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html
 #
 
-interface rlink
-
+adapter driver rlink
diff --git a/tcl/interface/rshim.cfg b/tcl/interface/rshim.cfg
new file mode 100644
index 0000000..accabf5
--- /dev/null
+++ b/tcl/interface/rshim.cfg
@@ -0,0 +1,6 @@
+#
+# BlueField SoC in-circuit debugger/programmer
+#
+
+adapter driver rshim
+transport select dapdirect_swd
diff --git a/tcl/interface/stlink-dap.cfg b/tcl/interface/stlink-dap.cfg
new file mode 100644
index 0000000..ac4de18
--- /dev/null
+++ b/tcl/interface/stlink-dap.cfg
@@ -0,0 +1,20 @@
+#
+# STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1, STLINK-V3 in-circuit
+# debugger/programmer
+#
+# This new interface driver creates a ST-Link wrapper for ARM-DAP named "dapdirect"
+# Old ST-LINK/V1 and ST-LINK/V2 pre version V2J24 don't support "dapdirect"
+#
+# SWIM transport is natively supported
+#
+
+adapter driver st-link
+st-link vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753
+
+# transport select dapdirect_jtag
+# transport select dapdirect_swd
+# transport select swim
+
+# Optionally specify the serial number of usb device
+# e.g.
+# st-link serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f"
diff --git a/tcl/interface/stlink.cfg b/tcl/interface/stlink.cfg
index 735ad5a..54cd63e 100644
--- a/tcl/interface/stlink.cfg
+++ b/tcl/interface/stlink.cfg
@@ -3,7 +3,7 @@
 # debugger/programmer
 #
 
-interface hla
+adapter driver hla
 hla_layout stlink
 hla_device_desc "ST-LINK"
 hla_vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753
@@ -14,4 +14,3 @@ hla_vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374
 # number reset issues.
 # eg.
 #hla_serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f"
-
diff --git a/tcl/interface/sysfsgpio-raspberrypi.cfg b/tcl/interface/sysfsgpio-raspberrypi.cfg
index 9f5b87c..ebb1502 100644
--- a/tcl/interface/sysfsgpio-raspberrypi.cfg
+++ b/tcl/interface/sysfsgpio-raspberrypi.cfg
@@ -8,7 +8,7 @@
 # Do not forget the GND connection, pin 6 of the expansion header.
 #
 
-interface sysfsgpio
+adapter driver sysfsgpio
 
 # Each of the JTAG lines need a gpio number set: tck tms tdi tdo
 # Header pin numbers: 23 22 19 21
diff --git a/tcl/interface/ti-icdi.cfg b/tcl/interface/ti-icdi.cfg
index 0fc3a9b..9b46b43 100644
--- a/tcl/interface/ti-icdi.cfg
+++ b/tcl/interface/ti-icdi.cfg
@@ -7,7 +7,7 @@
 # http://www.ti.com/tool/ek-lm4f232
 #
 
-interface hla
+adapter driver hla
 hla_layout ti-icdi
 hla_vid_pid 0x1cbe 0x00fd
 
diff --git a/tcl/interface/ulink.cfg b/tcl/interface/ulink.cfg
index 3b1fad0..164b990 100644
--- a/tcl/interface/ulink.cfg
+++ b/tcl/interface/ulink.cfg
@@ -5,4 +5,4 @@
 # http://article.gmane.org/gmane.comp.debugging.openocd.devel/17362
 #
 
-interface ulink
+adapter driver ulink
diff --git a/tcl/interface/usb-jtag.cfg b/tcl/interface/usb-jtag.cfg
index cb4d29b..8617c78 100644
--- a/tcl/interface/usb-jtag.cfg
+++ b/tcl/interface/usb-jtag.cfg
@@ -29,7 +29,7 @@
 # level driver. Loading firmware is currently only supported on the ublast2
 # driver but ixo-usb-jtag requires the ftdi driver.
 
-interface usb_blaster
+adapter driver usb_blaster
 usb_blaster_vid_pid 0x16C0 0x06AD
 usb_blaster_device_desc "Van Ooijen Technische Informatica"
 # ixo-usb-jtag is only compatible with the ublast1 protocol implemented via the
diff --git a/tcl/interface/usbprog.cfg b/tcl/interface/usbprog.cfg
index b4f0da3..f65c1d4 100644
--- a/tcl/interface/usbprog.cfg
+++ b/tcl/interface/usbprog.cfg
@@ -4,7 +4,7 @@
 # http://embedded-projects.net/index.php?page_id=135
 #
 
-interface usbprog
+adapter driver usbprog
 # USBprog is broken w/short TMS sequences, this is a workaround
 # until the C code can be fixed.
 tms_sequence long
diff --git a/tcl/interface/vsllink.cfg b/tcl/interface/vsllink.cfg
index fad7934..d40dbb4 100644
--- a/tcl/interface/vsllink.cfg
+++ b/tcl/interface/vsllink.cfg
@@ -4,5 +4,4 @@
 # http://www.versaloon.com/
 #
 
-interface vsllink
-
+adapter driver vsllink
diff --git a/tcl/interface/xds110.cfg b/tcl/interface/xds110.cfg
index 495e202..edc438d 100644
--- a/tcl/interface/xds110.cfg
+++ b/tcl/interface/xds110.cfg
@@ -5,7 +5,7 @@
 # http://processors.wiki.ti.com/index.php/Emulation_Software_Package#XDS110_Support_Utilities
 #
 
-interface xds110
+adapter driver xds110
 
 # Use serial number option to use a specific XDS110
 # when more than one are connected to the host.
diff --git a/tcl/memory.tcl b/tcl/memory.tcl
index 83c96d6..3066c11 100644
--- a/tcl/memory.tcl
+++ b/tcl/memory.tcl
@@ -58,7 +58,7 @@ set ACCESS_WIDTH_ANY  [expr $ACCESS_WIDTH_8 + $ACCESS_WIDTH_16 + $ACCESS_WIDTH_3
 set UNKNOWN(0,ACCESS_WIDTH) $ACCESS_WIDTH_NONE
 
 proc iswithin { ADDRESS BASE LEN } {
-    return [expr ((($ADDRESS - $BASE) > 0) && (($ADDRESS - $BASE + $LEN) > 0))]
+    return [expr ((($ADDRESS - $BASE) >= 0) && (($BASE + $LEN - $ADDRESS) > 0))]
 }
 
 proc address_info { ADDRESS } {
diff --git a/tcl/mmr_helpers.tcl b/tcl/mmr_helpers.tcl
index ce116e4..e6b1c67 100644
--- a/tcl/mmr_helpers.tcl
+++ b/tcl/mmr_helpers.tcl
@@ -28,7 +28,7 @@ proc show_mmr32_reg { NAME } {
 }
 
 
-# Give: NAMES - an array of names accessable
+# Give: NAMES - an array of names accessible
 #               in the callers symbol-scope.
 #       VAL - the bits to display.
 
diff --git a/tcl/target/1986Be1T.cfg b/tcl/target/1986Be1T.cfg
index ecb3f8a..b7c9d63 100644
--- a/tcl/target/1986Be1T.cfg
+++ b/tcl/target/1986Be1T.cfg
@@ -50,9 +50,9 @@ if { [info exists IMEMORY] && [string equal $IMEMORY true] } {
 }
 
 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
+adapter speed 1000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
    jtag_ntrst_delay 100
 }
diff --git a/tcl/target/K1879x61R.cfg b/tcl/target/K1879x61R.cfg
index 7d8c113..0a8467f 100644
--- a/tcl/target/K1879x61R.cfg
+++ b/tcl/target/K1879x61R.cfg
@@ -1,7 +1,7 @@
 # СБИС К1879ХБ1Я
 # http://www.module.ru/catalog/micro/mikroshema_dekodera_cifrovogo_televizionnogo_signala_sbis_k1879hb1ya/
 
-adapter_khz 1000
+adapter speed 1000
 
 if { [info exists CHIPNAME] } {
     set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/adsp-sc58x.cfg b/tcl/target/adsp-sc58x.cfg
index 8c9ef12..6073bb2 100644
--- a/tcl/target/adsp-sc58x.cfg
+++ b/tcl/target/adsp-sc58x.cfg
@@ -50,4 +50,3 @@ proc sc58x_enabledebug {} {
    # it is not possible to halt the target unless these bits have been set
    ap0.mem mww 0x31131000 0xFFFF
 }
-
diff --git a/tcl/target/aduc702x.cfg b/tcl/target/aduc702x.cfg
index fca0a7f..9c756be 100644
--- a/tcl/target/aduc702x.cfg
+++ b/tcl/target/aduc702x.cfg
@@ -17,7 +17,7 @@ if { [info exists CPUTAPID] } {
    set _CPUTAPID 0x3f0f0f0f
 }
 
-adapter_nsrst_delay 200
+adapter srst delay 200
 jtag_ntrst_delay 200
 
 ## JTAG scan chain
diff --git a/tcl/target/aducm360.cfg b/tcl/target/aducm360.cfg
index ca4bc68..b381728 100755..100644
--- a/tcl/target/aducm360.cfg
+++ b/tcl/target/aducm360.cfg
@@ -10,7 +10,7 @@ if { [info exists CHIPNAME] } {
    set _CHIPNAME aducm360
 }
 
-# Endianess
+# Endianness
 if { [info exists ENDIAN] } {
    set _ENDIAN $ENDIAN
 } else {
@@ -36,7 +36,7 @@ swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 # SWD/JTAG speed
-adapter_khz 1000
+adapter speed 1000
 
 ##
 ## Target configuration
@@ -51,6 +51,6 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME aducm360 0x00 0 0 0 $_TARGETNAME
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 
 cortex_m reset_config sysresetreq
diff --git a/tcl/target/allwinner_v3s.cfg b/tcl/target/allwinner_v3s.cfg
index 32fd188..d8d78bd 100644
--- a/tcl/target/allwinner_v3s.cfg
+++ b/tcl/target/allwinner_v3s.cfg
@@ -34,7 +34,7 @@
 # 0220ms	JTAG pins switched to SD mode
 #
 # The time frame of 20ms can be not enough to init and halt the CPU. In this
-# case I would recommend to set: "adapter_khz 15000"
+# case I would recommend to set: "adapter speed 15000"
 # To get more or less precise timings, the board should provide reset pin,
 # or some bench power supply with remote function. In my case I used
 # EEZ H24005 with this command to power on and halt the target:
diff --git a/tcl/target/altera_fpgasoc.cfg b/tcl/target/altera_fpgasoc.cfg
index 9a83b5c..0fc8d67 100644
--- a/tcl/target/altera_fpgasoc.cfg
+++ b/tcl/target/altera_fpgasoc.cfg
@@ -36,7 +36,7 @@ jtag newtap $_CHIPNAME.fpga tap -irlen 10 -ircapture 0x01 -irmask 0x3 -expected-
 # core 1  -  0x80112000
 
 # Slow speed to be sure it will work
-adapter_khz 1000
+adapter speed 1000
 
 set _TARGETNAME1 $_CHIPNAME.cpu.0
 set _TARGETNAME2 $_CHIPNAME.cpu.1
@@ -46,7 +46,7 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 target create $_TARGETNAME1 cortex_a -dap $_CHIPNAME.dap \
         -coreid 0 -dbgbase 0x80110000
 
-$_TARGETNAME1 configure -event reset-start { adapter_khz 1000 }
+$_TARGETNAME1 configure -event reset-start { adapter speed 1000 }
 $_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
 
 
@@ -54,7 +54,7 @@ $_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
 #target create $_TARGETNAME2 cortex_a -dap $_CHIPNAME.dap \
 #        -coreid 1 -dbgbase 0x80112000
 
-#$_TARGETNAME2 configure -event reset-start { adapter_khz 1000 }
+#$_TARGETNAME2 configure -event reset-start { adapter speed 1000 }
 #$_TARGETNAME2 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME2"
 
 proc cycv_dbginit {target} {
diff --git a/tcl/target/amdm37x.cfg b/tcl/target/amdm37x.cfg
index 5c4e315..3db24b4 100644
--- a/tcl/target/amdm37x.cfg
+++ b/tcl/target/amdm37x.cfg
@@ -45,7 +45,7 @@ if { [info exists CHIPTYPE] } {
 
 # Run the adapter at the fastest acceptable speed with the slowest possible
 # core clock.
-adapter_khz 10
+adapter speed 10
 
 ###############################################################################
 # JTAG setup
@@ -157,7 +157,7 @@ $_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
 #  slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up
 #  *after* PLL and clock tree setup.
 
-$_TARGETNAME configure -event "reset-start" { adapter_khz 10 }
+$_TARGETNAME configure -event "reset-start" { adapter speed 10 }
 
 # Describe the reset assert process for openocd - this is asserted with the
 # ICEPick
@@ -176,7 +176,7 @@ $_TARGETNAME configure -event reset-assert-post {
 
    global _TARGETNAME
    amdm37x_dbginit $_TARGETNAME
-   adapter_khz 1000
+   adapter speed 1000
 }
 
 $_TARGETNAME configure -event gdb-attach {
@@ -209,4 +209,3 @@ proc amdm37x_dbginit {target} {
    # at this address and this bit.
    $target mww phys 0x5401d030 0x00002000
 }
-
diff --git a/tcl/target/ar71xx.cfg b/tcl/target/ar71xx.cfg
index 196b048..57833f4 100644
--- a/tcl/target/ar71xx.cfg
+++ b/tcl/target/ar71xx.cfg
@@ -1,7 +1,7 @@
 # Atheros AR71xx MIPS 24Kc SoC.
 # tested on PB44 refererence board
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 
 reset_config trst_and_srst
@@ -54,4 +54,3 @@ $_TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000
 
 # serial SPI capable flash
 # flash bank <driver> <base> <size> <chip_width> <bus_width>
-
diff --git a/tcl/target/armada370.cfg b/tcl/target/armada370.cfg
index 5b84637..3b4be9f 100644
--- a/tcl/target/armada370.cfg
+++ b/tcl/target/armada370.cfg
@@ -31,4 +31,3 @@ $_TARGETNAME configure -event reset-assert-post "armada370_dbginit $_TARGETNAME"
 # We need to init now, so we can run the apsel command.
 init
 dap apsel 1
-
diff --git a/tcl/target/at91rm9200.cfg b/tcl/target/at91rm9200.cfg
index 2e8c1e0..3d9a8d9 100644
--- a/tcl/target/at91rm9200.cfg
+++ b/tcl/target/at91rm9200.cfg
@@ -28,7 +28,7 @@ if { $_CPUTAPID == 0x15b0203f } {
    echo "- ERROR:                                              -"
    echo "- ERROR: In one position (0x05b0203f) it selects the  -"
    echo "- ERROR: ARM CPU, in the other position (0x1b0203f)   -"
-   echo "- ERROR: it selects boundry-scan not the ARM          -"
+   echo "- ERROR: it selects boundary-scan not the ARM         -"
    echo "- ERROR:                                              -"
    echo "-------------------------------------------------------"
 }
diff --git a/tcl/target/at91sam3XXX.cfg b/tcl/target/at91sam3XXX.cfg
index e7dec4b..7d01ccd 100644
--- a/tcl/target/at91sam3XXX.cfg
+++ b/tcl/target/at91sam3XXX.cfg
@@ -74,9 +74,9 @@ $_TARGETNAME configure -event gdb-flash-erase-start {
 # running off a crystal, we can run closer to the limit. Note
 # that there can be a pretty wide band where things are more or less stable.
 
-adapter_khz 500
+adapter speed 500
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
    jtag_ntrst_delay 100
 }
diff --git a/tcl/target/at91sam3ax_8x.cfg b/tcl/target/at91sam3ax_8x.cfg
index e249383..2bb66fb 100644
--- a/tcl/target/at91sam3ax_8x.cfg
+++ b/tcl/target/at91sam3ax_8x.cfg
@@ -7,5 +7,3 @@ flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
 # This is a 512K chip - it has the 2nd bank
 set _FLASHNAME $_CHIPNAME.flash1
 flash bank $_FLASHNAME at91sam3 0x0000C0000 0 1 1 $_TARGETNAME
-
-
diff --git a/tcl/target/at91sam3ax_xx.cfg b/tcl/target/at91sam3ax_xx.cfg
index e561771..5e01d66 100644
--- a/tcl/target/at91sam3ax_xx.cfg
+++ b/tcl/target/at91sam3ax_xx.cfg
@@ -8,4 +8,3 @@
 # at91sam3X8E
 # at91sam3X8H
 source [find target/at91sam3XXX.cfg]
-
diff --git a/tcl/target/at91sam3u1c.cfg b/tcl/target/at91sam3u1c.cfg
index 47c227b..dc5c82c 100644
--- a/tcl/target/at91sam3u1c.cfg
+++ b/tcl/target/at91sam3u1c.cfg
@@ -4,5 +4,3 @@ source [find target/at91sam3uxx.cfg]
 # size is automatically "calculated" by probing
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
-
-
diff --git a/tcl/target/at91sam3u1e.cfg b/tcl/target/at91sam3u1e.cfg
index 47c227b..dc5c82c 100644
--- a/tcl/target/at91sam3u1e.cfg
+++ b/tcl/target/at91sam3u1e.cfg
@@ -4,5 +4,3 @@ source [find target/at91sam3uxx.cfg]
 # size is automatically "calculated" by probing
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
-
-
diff --git a/tcl/target/at91sam3u2c.cfg b/tcl/target/at91sam3u2c.cfg
index 47c227b..dc5c82c 100644
--- a/tcl/target/at91sam3u2c.cfg
+++ b/tcl/target/at91sam3u2c.cfg
@@ -4,5 +4,3 @@ source [find target/at91sam3uxx.cfg]
 # size is automatically "calculated" by probing
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
-
-
diff --git a/tcl/target/at91sam3u2e.cfg b/tcl/target/at91sam3u2e.cfg
index 47c227b..dc5c82c 100644
--- a/tcl/target/at91sam3u2e.cfg
+++ b/tcl/target/at91sam3u2e.cfg
@@ -4,5 +4,3 @@ source [find target/at91sam3uxx.cfg]
 # size is automatically "calculated" by probing
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
-
-
diff --git a/tcl/target/at91sam3u4c.cfg b/tcl/target/at91sam3u4c.cfg
index 5cacbcb..14af008 100644
--- a/tcl/target/at91sam3u4c.cfg
+++ b/tcl/target/at91sam3u4c.cfg
@@ -7,5 +7,3 @@ flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
 # This is a 256K chip, it has the 2nd bank
 set _FLASHNAME $_CHIPNAME.flash1
 flash bank $_FLASHNAME at91sam3 0x000100000 0 1 1 $_TARGETNAME
-
-
diff --git a/tcl/target/at91sam3u4e.cfg b/tcl/target/at91sam3u4e.cfg
index a48f992..fbe2dd9 100644
--- a/tcl/target/at91sam3u4e.cfg
+++ b/tcl/target/at91sam3u4e.cfg
@@ -7,5 +7,3 @@ flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
 # This is a 256K chip - it has the 2nd bank
 set _FLASHNAME $_CHIPNAME.flash1
 flash bank $_FLASHNAME at91sam3 0x000100000 0 1 1 $_TARGETNAME
-
-
diff --git a/tcl/target/at91sam3uxx.cfg b/tcl/target/at91sam3uxx.cfg
index b42ae19..5b1748b 100644
--- a/tcl/target/at91sam3uxx.cfg
+++ b/tcl/target/at91sam3uxx.cfg
@@ -8,4 +8,3 @@
 # at91sam3u1c
 
 source [find target/at91sam3XXX.cfg]
-
diff --git a/tcl/target/at91sam4XXX.cfg b/tcl/target/at91sam4XXX.cfg
index ff73670..ebb7eed 100644
--- a/tcl/target/at91sam4XXX.cfg
+++ b/tcl/target/at91sam4XXX.cfg
@@ -50,9 +50,9 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 # running off a crystal, we can run closer to the limit. Note
 # that there can be a pretty wide band where things are more or less stable.
 
-adapter_khz 500
+adapter speed 500
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
diff --git a/tcl/target/at91sam4lXX.cfg b/tcl/target/at91sam4lXX.cfg
index 4aee7d0..b73babc 100644
--- a/tcl/target/at91sam4lXX.cfg
+++ b/tcl/target/at91sam4lXX.cfg
@@ -21,7 +21,7 @@ reset_config srst_gates_jtag
 # Datasheet does not specify SYSCLK to JTAG/SWD clock ratio.
 # Usually used SYSCLK/6 is hell slow, testing shows that debugging can work @ SYSCLK/2
 # but your mileage may vary.
-adapter_khz 50
+adapter speed 50
 
 # System RC oscillator RCSYS starts in 3 cycles
-adapter_nsrst_delay 0
+adapter srst delay 0
diff --git a/tcl/target/at91sam7se512.cfg b/tcl/target/at91sam7se512.cfg
index ab09701..61b4781 100644
--- a/tcl/target/at91sam7se512.cfg
+++ b/tcl/target/at91sam7se512.cfg
@@ -36,4 +36,3 @@ $_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-a
 #flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
-
diff --git a/tcl/target/at91sam9.cfg b/tcl/target/at91sam9.cfg
index bf99fb2..e0ea316 100644
--- a/tcl/target/at91sam9.cfg
+++ b/tcl/target/at91sam9.cfg
@@ -24,10 +24,10 @@ reset_config trst_and_srst separate trst_push_pull srst_open_drain
 
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
-adapter_nsrst_delay 300
+adapter srst delay 300
 jtag_ntrst_delay 200
 
-adapter_khz 3
+adapter speed 3
 
 ######################
 # Target configuration
diff --git a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
index 9ab7409..3e4b7d7 100644
--- a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
+++ b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
@@ -6,15 +6,15 @@ source [find target/at91sam9261.cfg]
 
 reset_config trst_and_srst
 
-adapter_khz 4
+adapter speed 4
 
-adapter_nsrst_delay 200
+adapter srst delay 200
 jtag_ntrst_delay 200
 
 scan_chain
 $_TARGETNAME configure -event reset-start {
 	# at reset chip runs at 32khz
-	adapter_khz 8
+	adapter speed 8
 }
 
 $_TARGETNAME configure -event reset-init {at91sam_init}
@@ -46,7 +46,7 @@ proc at91sam_init { } {
 	sleep 10                          ;# wait 10 ms
 
 	# Now run at anything fast... ie: 10mhz!
-	adapter_khz 10000                    ;# Increase JTAG Speed to 6 MHz
+	adapter speed 10000               ;# Increase JTAG Speed to 6 MHz
 
 	mww 0xffffec00 0x0a0a0a0a         ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
 	mww 0xffffec04 0x0b0b0b0b         ;# SMC_PULSE0
diff --git a/tcl/target/at91sam9g20.cfg b/tcl/target/at91sam9g20.cfg
index 3f5e3c6..6e45df2 100644
--- a/tcl/target/at91sam9g20.cfg
+++ b/tcl/target/at91sam9g20.cfg
@@ -12,7 +12,7 @@ source [find target/at91sam9.cfg]
 
 # Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock).
 
-adapter_khz 5
+adapter speed 5
 
 # Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc.  The
 # AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000.
diff --git a/tcl/target/at91samdXX.cfg b/tcl/target/at91samdXX.cfg
index f0644d1..9a396fa 100644
--- a/tcl/target/at91samdXX.cfg
+++ b/tcl/target/at91samdXX.cfg
@@ -66,12 +66,12 @@ reset_config srst_gates_jtag
 # This limit is most probably imposed by incorrectly handled SWD WAIT
 # on some SWD adapters.
 
-adapter_khz 400
+adapter speed 400
 
 # Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works
 # without problem at maximal clock speed. Atmel recommends
 # adapter speed less than 10 * CPU clock.
-# adapter_khz 5000
+# adapter speed 5000
 
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
diff --git a/tcl/target/atheros_ar9331.cfg b/tcl/target/atheros_ar9331.cfg
index bea37ed..6ab238c 100644
--- a/tcl/target/atheros_ar9331.cfg
+++ b/tcl/target/atheros_ar9331.cfg
@@ -41,12 +41,12 @@ reset_config none srst_pulls_trst
 # For SRST based variant we still need proper timings.
 # For ETH part the reset should be asserted at least for 10ms
 # Since there is no other information let's take 100ms to be sure.
-adapter_nsrst_assert_width 100
+adapter srst pulse_width 100
 
 # according to the SoC documentation it should take at least 5ms from
 # reset end till bootstrap end. In the practice we need 8ms to get JTAG back
 # to live.
-adapter_nsrst_delay 8
+adapter srst delay 8
 
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $_CHIPNAME
diff --git a/tcl/target/atmega128.cfg b/tcl/target/atmega128.cfg
index b8f7d01..07161d5 100644
--- a/tcl/target/atmega128.cfg
+++ b/tcl/target/atmega128.cfg
@@ -4,10 +4,10 @@
    set _ENDIAN little
 
 # jtag speed
-adapter_khz 4500
+adapter speed 4500
 
 reset_config srst_only
-adapter_nsrst_delay 100
+adapter srst delay 100
 
 #jtag scan chain
 if { [info exists CPUTAPID] } {
@@ -27,7 +27,7 @@ flash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME
 
 #to use it, script will be like:
 #init
-#adapter_khz 4500
+#adapter speed 4500
 #reset init
 #verify_ircapture disable
 #
diff --git a/tcl/target/atmega128rfa1.cfg b/tcl/target/atmega128rfa1.cfg
index 2c12a61..cda439d 100644
--- a/tcl/target/atmega128rfa1.cfg
+++ b/tcl/target/atmega128rfa1.cfg
@@ -2,7 +2,7 @@ set _CHIPNAME avr
 set _ENDIAN little
 
 # jtag speed
-adapter_khz 4500
+adapter speed 4500
 
 # avr jtag docs never connect RSTN
 reset_config none
diff --git a/tcl/target/atsame5x.cfg b/tcl/target/atsame5x.cfg
index 61949cf..351a2ca 100644
--- a/tcl/target/atsame5x.cfg
+++ b/tcl/target/atsame5x.cfg
@@ -63,7 +63,7 @@ reset_config srst_gates_jtag
 # Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works
 # without problem at clock speed over 5000 khz. Atmel recommends
 # adapter speed less than 10 * CPU clock.
-adapter_khz 2000
+adapter speed 2000
 
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
diff --git a/tcl/target/atsamv.cfg b/tcl/target/atsamv.cfg
index 43962de..fdd8354 100644
--- a/tcl/target/atsamv.cfg
+++ b/tcl/target/atsamv.cfg
@@ -39,7 +39,7 @@ target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20400000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
-adapter_khz 1800
+adapter speed 1800
 
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
@@ -57,4 +57,3 @@ if {![using_hla]} {
 
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME
-
diff --git a/tcl/target/avr32.cfg b/tcl/target/avr32.cfg
index f5ee1a4..8295f5e 100644
--- a/tcl/target/avr32.cfg
+++ b/tcl/target/avr32.cfg
@@ -3,7 +3,7 @@ set _ENDIAN big
 
 set _CPUTAPID 0x21e8203f
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 
 reset_config trst_and_srst separate
@@ -14,4 +14,3 @@ jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_CP
 
 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
 target create $_TARGETNAME avr32_ap7k -endian $_ENDIAN -chain-position $_TARGETNAME
-
diff --git a/tcl/target/bcm6348.cfg b/tcl/target/bcm6348.cfg
index 2540b51..a9be559 100644
--- a/tcl/target/bcm6348.cfg
+++ b/tcl/target/bcm6348.cfg
@@ -1,7 +1,7 @@
 set _CHIPNAME bcm6348
 set _CPUID 0x0634817f
 
-adapter_khz 1000
+adapter speed 1000
 
 jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID
 
diff --git a/tcl/target/bluefield.cfg b/tcl/target/bluefield.cfg
new file mode 100644
index 0000000..b31dfe8
--- /dev/null
+++ b/tcl/target/bluefield.cfg
@@ -0,0 +1,78 @@
+# BlueField SoC Target
+
+set _CHIPNAME bluefield
+
+# Specify the target device
+#rshim device /dev/rshim0/rshim
+
+# Main DAP
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x4ba00477
+}
+
+adapter speed 1500
+
+swd newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# Initialize the target name and command variable.
+set _TARGETNAME $_CHIPNAME.cpu
+set _smp_command ""
+
+# CTI relative address
+set $_TARGETNAME.cti(0) 0xC4020000
+set $_TARGETNAME.cti(1) 0xC4120000
+set $_TARGETNAME.cti(2) 0xC8020000
+set $_TARGETNAME.cti(3) 0xC8120000
+set $_TARGETNAME.cti(4) 0xCC020000
+set $_TARGETNAME.cti(5) 0xCC120000
+set $_TARGETNAME.cti(6) 0xD0020000
+set $_TARGETNAME.cti(7) 0xD0120000
+set $_TARGETNAME.cti(8) 0xD4020000
+set $_TARGETNAME.cti(9) 0xD4120000
+set $_TARGETNAME.cti(10) 0xD8020000
+set $_TARGETNAME.cti(11) 0xD8120000
+set $_TARGETNAME.cti(12) 0xDC020000
+set $_TARGETNAME.cti(13) 0xDC120000
+set $_TARGETNAME.cti(14) 0xE0020000
+set $_TARGETNAME.cti(15) 0xE0120000
+
+# Create debug targets for a number of cores starting from core '_core_start'.
+# Adjust the numbers according to board configuration.
+set _core_start 0
+set _cores 16
+
+# Create each core
+for { set _core $_core_start } { $_core < $_core_start + $_cores } { incr _core 1 } {
+    cti create cti$_core -dap $_CHIPNAME.dap -ctibase [set $_TARGETNAME.cti($_core)] -ap-num 0
+
+    set _command "target create ${_TARGETNAME}$_core aarch64 \
+                         -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core"
+
+    if { $_core != $_core_start } {
+        set _smp_command "$_smp_command ${_TARGETNAME}$_core"
+    } else {
+        set _smp_command "target smp ${_TARGETNAME}$_core"
+    }
+
+    eval $_command
+}
+
+# Configure SMP
+if { $_cores > 1 } {
+    eval $_smp_command
+}
+
+# Make sure the default target is the boot core
+targets ${_TARGETNAME}0
+
+proc core_up { args } {
+	global _TARGETNAME
+
+	# Examine remaining cores
+	foreach _core [set args] {
+		${_TARGETNAME}$_core arp_examine
+	}
+}
diff --git a/tcl/target/bluenrg-x.cfg b/tcl/target/bluenrg-x.cfg
index b0dd61a..a9d321e 100644
--- a/tcl/target/bluenrg-x.cfg
+++ b/tcl/target/bluenrg-x.cfg
@@ -1,8 +1,9 @@
 #
-# bluenrg-1/2 devices support only SWD transports.
+# bluenrg-1/2 and bluenrg-lp devices support only SWD transports.
 #
 
 source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
@@ -20,15 +21,9 @@ if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE 0x5F00
 }
 
-adapter_khz 4000
+adapter speed 4000
 
-if { [info exists CPUTAPID] } {
-   set _CPUTAPID $CPUTAPID
-} else {
-   set _CPUTAPID 0x0bb11477
-}
-
-swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+swj_newdap $_CHIPNAME cpu -expected-id 0x0bb11477 -expected-id 0x0bc11477
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
@@ -53,22 +48,27 @@ if {![using_hla]} {
 }
 
 $_TARGETNAME configure -event halted {
-	global WDOG_VALUE
-	global WDOG_VALUE_SET
-	# Stop watchdog during halt, if enabled
-	mem2array value 32 0x40700008 1
-	set WDOG_VALUE [expr ($value(0))]
-	if [expr ($value(0) & (1 << 1))] {
-		set WDOG_VALUE_SET 1
-		mww 0x40700008 [expr ($value(0) & 0xFFFFFFFD)]
-	}
+    global WDOG_VALUE
+    global WDOG_VALUE_SET
+    set _JTAG_IDCODE [mrw 0x40000004]
+    if {$_JTAG_IDCODE != 0x0201E041} {
+        # Stop watchdog during halt, if enabled. Only Bluenrg-1/2
+        set WDOG_VALUE [mrw 0x40700008]
+        if [expr ($WDOG_VALUE & (1 << 1))] {
+            set WDOG_VALUE_SET 1
+            mww 0x40700008 [expr ($WDOG_VALUE & 0xFFFFFFFD)]
+        }
+    }
 }
 $_TARGETNAME configure -event resumed {
-	global WDOG_VALUE
-	global WDOG_VALUE_SET
-	if [expr $WDOG_VALUE_SET] {
-		# Restore watchdog enable value after resume
-		mww 0x40700008 $WDOG_VALUE
-		set WDOG_VALUE_SET 0
-       }
+    global WDOG_VALUE
+    global WDOG_VALUE_SET
+    set _JTAG_IDCODE [mrw 0x40000004]
+    if {$_JTAG_IDCODE != 0x0201E041} {
+        if [expr $WDOG_VALUE_SET] {
+            # Restore watchdog enable value after resume. Only Bluenrg-1/2
+            mww 0x40700008 $WDOG_VALUE
+            set WDOG_VALUE_SET 0
+           }
+   }
 }
diff --git a/tcl/target/c100.cfg b/tcl/target/c100.cfg
index 1eaa8fe..5b4354e 100644
--- a/tcl/target/c100.cfg
+++ b/tcl/target/c100.cfg
@@ -3,7 +3,7 @@
 # this script only configures one core (that is used to run Linux)
 
 # assume no PLL lock, start slowly
-adapter_khz 100
+adapter speed 100
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/c100config.tcl b/tcl/target/c100config.tcl
index 52efa83..53b2c5d 100644
--- a/tcl/target/c100config.tcl
+++ b/tcl/target/c100config.tcl
@@ -1,5 +1,5 @@
 
-# board(-config) specfic parameters file.
+# board(-config) specific parameters file.
 
 # set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ]
 proc config {label} {
@@ -409,4 +409,4 @@ proc flashUBOOT {file} {
     putsUART0 "done.\n"
     putsUART0 "Rebooting, please wait!\n"
     reboot
-}
-\ No newline at end of file
+}
diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl
index c9124cb..725ba70 100644
--- a/tcl/target/c100helper.tcl
+++ b/tcl/target/c100helper.tcl
@@ -15,7 +15,7 @@ proc helpC100 {} {
     echo "12) ooma_board_detect: will show which version of Telo you have"
     echo "13) setupDDR2:         will configure DDR2 controller, you must have PLLs configureg"
     echo "14) showDDR2:          will show DDR2 config registers"
-    echo "15) showWatchdog:      will show current regster config for watchdog"
+    echo "15) showWatchdog:      will show current register config for watchdog"
     echo "16) reboot:            will trigger watchdog and reboot Telo (hw reset)"
     echo "17) bootNOR:           will boot Telo from NOR"
     echo "18) setupUART0:        will configure UART0 for 115200 8N1, PLLs have to be confiured"
@@ -176,7 +176,7 @@ proc setupAmbaClk {} {
     mmw $CLKCORE_AHB_CLK_CNTRL 0x0 0xFFFFFF
     mmw $CLKCORE_AHB_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
     # wait for PLL to lock
-    echo "Wating for Amba PLL to lock"
+    echo "Waiting for Amba PLL to lock"
     while {[expr [mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK] == 0} { sleep 1 }
     # remove the internal PLL bypass
     mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL
@@ -250,7 +250,7 @@ proc setupArmClk {} {
     mmw $CLKCORE_ARM_CLK_CNTRL 0x0 0xFFFFFF
     mmw $CLKCORE_ARM_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
     # wait for PLL to lock
-    echo "Wating for Amba PLL to lock"
+    echo "Waiting for Amba PLL to lock"
     while {[expr [mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK] == 0} { sleep 1 }
     # remove the internal PLL bypass
     mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL
@@ -300,7 +300,7 @@ proc setupDDR2 {} {
 
     # Memory setup register
     mww $MEMORY_MAX_ADDR  [expr ($ddr_size - 1) + $MEMORY_BASE_ADDR]
-    # disbale ROM remap
+    # disable ROM remap
     mww $MEMORY_CR 0x0
     # Take DDR controller out of reset
     mmw $BLOCK_RESET_REG $DDR_RST 0x0
@@ -486,15 +486,15 @@ proc reboot {} {
     set TIMER_WDT_CURRENT_COUNT	[regs TIMER_WDT_CURRENT_COUNT]
 
     # allow the counter to count to high value  before triggering
-    # this is because regsiter writes are slow over JTAG and
+    # this is because register writes are slow over JTAG and
     # I don't want to miss the high_bound==curr_count condition
     mww $TIMER_WDT_HIGH_BOUND  0xffffff
     mww $TIMER_WDT_CURRENT_COUNT 0x0
     echo "JTAG speed lowered to 100kHz"
-    adapter_khz 100
+    adapter speed 100
     mww $TIMER_WDT_CONTROL 0x1
     # wait until the reset
-    echo -n "Wating for watchdog to trigger..."
+    echo -n "Waiting for watchdog to trigger..."
     #while {[mrw $TIMER_WDT_CONTROL] == 1} {
     #    echo [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
     #    sleep 1
diff --git a/tcl/target/cc2538.cfg b/tcl/target/cc2538.cfg
index 63fd9c2..8d232f4 100755..100644
--- a/tcl/target/cc2538.cfg
+++ b/tcl/target/cc2538.cfg
@@ -1,7 +1,7 @@
 # Config for Texas Instruments low power RF SoC CC2538
 # http://www.ti.com/lit/pdf/swru319
 
-adapter_khz 100
+adapter speed 100
 
 source [find target/icepick.cfg]
 source [find target/ti-cjtag.cfg]
diff --git a/tcl/target/cs351x.cfg b/tcl/target/cs351x.cfg
index cb05da2..8fabda6 100644
--- a/tcl/target/cs351x.cfg
+++ b/tcl/target/cs351x.cfg
@@ -28,4 +28,3 @@ target create $_TARGETNAME fa526 -endian $_ENDIAN -chain-position $_TARGETNAME
 
 # This chip has a DCC ... use it
 arm7_9 dcc_downloads enable
-
diff --git a/tcl/target/dragonite.cfg b/tcl/target/dragonite.cfg
index 750fd64..b9d73a2 100644
--- a/tcl/target/dragonite.cfg
+++ b/tcl/target/dragonite.cfg
@@ -26,6 +26,5 @@ set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME dragonite -endian $_ENDIAN -chain-position $_TARGETNAME
 
 reset_config trst_and_srst
-adapter_nsrst_delay 200
+adapter srst delay 200
 jtag_ntrst_delay 200
-
diff --git a/tcl/target/dsp56321.cfg b/tcl/target/dsp56321.cfg
index 6f32223..78ecb3b 100644
--- a/tcl/target/dsp56321.cfg
+++ b/tcl/target/dsp56321.cfg
@@ -1,13 +1,13 @@
 # Script for freescale DSP56321
 #
 
-if { [info exists CHIPNAME] } {	
+if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
 } else {
    set _CHIPNAME dsp56321
 }
 
-if { [info exists ENDIAN] } {	
+if { [info exists ENDIAN] } {
    set _ENDIAN $ENDIAN
 } else {
   # this defaults to a big endian
@@ -21,7 +21,7 @@ if { [info exists CPUTAPID] } {
 }
 
 #jtag speed
-adapter_khz 4500
+adapter speed 4500
 
 #has only srst
 reset_config srst_only
diff --git a/tcl/target/dsp568013.cfg b/tcl/target/dsp568013.cfg
index 0c491fa..67d4419 100644
--- a/tcl/target/dsp568013.cfg
+++ b/tcl/target/dsp568013.cfg
@@ -1,12 +1,12 @@
 # Script for freescale DSP568013
 
-if { [info exists CHIPNAME] } {	
+if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
 } else {
    set _CHIPNAME dsp568013
 }
 
-if { [info exists ENDIAN] } {	
+if { [info exists ENDIAN] } {
    set _ENDIAN $ENDIAN
 } else {
   # this defaults to a big endian
@@ -20,7 +20,7 @@ if { [info exists CPUTAPID] } {
 }
 
 #jtag speed
-adapter_khz 800
+adapter speed 800
 
 reset_config srst_only
 
@@ -35,7 +35,7 @@ set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME dsp5680xx -endian $_ENDIAN -chain-position $_TARGETNAME
 
 # Setup the interesting tap
-# Disable polling to be able to get idcode from core tap. If re enabled, can be re enabled, but it should be disabled to correctly unlock flash (operations requiere certain instruction to be in the IR register during reset, and polling would change this)
+# Disable polling to be able to get idcode from core tap. If re enabled, can be re enabled, but it should be disabled to correctly unlock flash (operations require certain instruction to be in the IR register during reset, and polling would change this)
 jtag configure $_CHIPNAME.chp -event setup "
      jtag tapenable $_TARGETNAME
      poll off
@@ -73,4 +73,3 @@ $_TARGETNAME configure -work-area-virt 0
 #setup flash
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME dsp5680xx_flash 0 0 2 1 $_TARGETNAME
-
diff --git a/tcl/target/dsp568037.cfg b/tcl/target/dsp568037.cfg
index 01194d0..fc57bd4 100644
--- a/tcl/target/dsp568037.cfg
+++ b/tcl/target/dsp568037.cfg
@@ -20,7 +20,7 @@ if { [info exists CPUTAPID] } {
 }
 
 #jtag speed
-adapter_khz 800
+adapter speed 800
 
 reset_config srst_only
 
@@ -69,4 +69,3 @@ $_TARGETNAME configure -work-area-virt 0
 #setup flash
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME dsp5680xx_flash 0 0 2 1 $_TARGETNAME
-
diff --git a/tcl/target/efm32.cfg b/tcl/target/efm32.cfg
index e22ce5c..c789efc 100644
--- a/tcl/target/efm32.cfg
+++ b/tcl/target/efm32.cfg
@@ -34,7 +34,7 @@ if { [info exists CPUTAPID] } {
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
-adapter_khz 1000
+adapter speed 1000
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
diff --git a/tcl/target/epc9301.cfg b/tcl/target/epc9301.cfg
index f186d37..252bbab 100644
--- a/tcl/target/epc9301.cfg
+++ b/tcl/target/epc9301.cfg
@@ -20,7 +20,7 @@ if { [info exists CPUTAPID] } {
 }
 
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 
 set _TARGETNAME $_CHIPNAME.cpu
diff --git a/tcl/target/esi32xx.cfg b/tcl/target/esi32xx.cfg
index d32af39..6be84ab 100644
--- a/tcl/target/esi32xx.cfg
+++ b/tcl/target/esi32xx.cfg
@@ -26,7 +26,7 @@ if { [info exists CACHEARCH] } {
     $_TARGETNAME esirisc cache_arch $CACHEARCH
 }
 
-adapter_khz 2000
+adapter speed 2000
 
 reset_config none
 
diff --git a/tcl/target/feroceon.cfg b/tcl/target/feroceon.cfg
index 389576e..d4f710e 100644
--- a/tcl/target/feroceon.cfg
+++ b/tcl/target/feroceon.cfg
@@ -26,6 +26,5 @@ set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME feroceon -endian $_ENDIAN -chain-position $_TARGETNAME
 
 reset_config trst_and_srst
-adapter_nsrst_delay 200
+adapter srst delay 200
 jtag_ntrst_delay 200
-
diff --git a/tcl/target/fm3.cfg b/tcl/target/fm3.cfg
index a0610ce..544cff9 100644
--- a/tcl/target/fm3.cfg
+++ b/tcl/target/fm3.cfg
@@ -22,7 +22,7 @@ if { [info exists CPUTAPID] } {
 }
 
 # delays on reset lines
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
    jtag_ntrst_delay 100
 }
@@ -36,16 +36,16 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
-# MB9BF506 has 64kB of SRAM on its main system bus 
+# MB9BF506 has 64kB of SRAM on its main system bus
 $_TARGETNAME configure -work-area-phys 0x1FFF8000 -work-area-size 0x10000 -work-area-backup 0
 
-# MB9BF506 has 512kB internal FLASH 
+# MB9BF506 has 512kB internal FLASH
 
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
 
 # 4MHz / 6 = 666kHz, so use 500
-adapter_khz 500
+adapter speed 500
 
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
diff --git a/tcl/target/fm4.cfg b/tcl/target/fm4.cfg
index b79634d..bfe7115 100644
--- a/tcl/target/fm4.cfg
+++ b/tcl/target/fm4.cfg
@@ -24,7 +24,7 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
 
-adapter_khz 500
+adapter speed 500
 
 if {![using_hla]} {
 	cortex_m reset_config sysresetreq
diff --git a/tcl/target/gp326xxxa.cfg b/tcl/target/gp326xxxa.cfg
index feb7554..df42c44 100644
--- a/tcl/target/gp326xxxa.cfg
+++ b/tcl/target/gp326xxxa.cfg
@@ -33,11 +33,11 @@ $_TARGETNAME configure -work-area-phys 0xf8000000 -work-area-size 0x8000 -work-a
 reset_config trst_and_srst srst_pulls_trst
 # This delay is needed otherwise communication with the target would
 # be unreliable
-adapter_nsrst_delay 100
+adapter srst delay 100
 
 # Set the adapter speed ridiculously low just in case we are
 # running off of a 32kHz clock
-adapter_khz 2
+adapter speed 2
 
 proc gp32xxxa_halt_and_reset_control_registers {} {
 	# System control registers
@@ -57,7 +57,7 @@ proc gp32xxxa_halt_and_reset_control_registers {} {
 
 	# Set the adapter speed ridiculously low just in case we are
 	# running off of a 32kHz clock
-	adapter_khz 2
+	adapter speed 2
 
 	# Disable any advanced features at this stage
 	arm7_9 dcc_downloads disable
@@ -86,7 +86,7 @@ proc gp32xxxa_halt_and_reset_control_registers {} {
 
 	# Now that we know that we are running at 48Mhz
 	# Increase JTAG speed and enable speed optimization features
-	adapter_khz 5000
+	adapter speed 5000
 	arm7_9 dcc_downloads enable
 	arm7_9 fast_memory_access enable
 }
diff --git a/tcl/target/hilscher_netx10.cfg b/tcl/target/hilscher_netx10.cfg
index 3f96607..668de8f 100644
--- a/tcl/target/hilscher_netx10.cfg
+++ b/tcl/target/hilscher_netx10.cfg
@@ -28,4 +28,3 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CP
 # that TAP is associated with a target
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
-
diff --git a/tcl/target/icepick.cfg b/tcl/target/icepick.cfg
index a945bea..d125071 100644
--- a/tcl/target/icepick.cfg
+++ b/tcl/target/icepick.cfg
@@ -75,9 +75,22 @@ proc icepick_c_setup {jrc} {
 }
 
 # jrc	== TAP name for the ICEpick
-# port	== a port number, 0..15
+# port	== a port number, 0..15 for debug tap, 16..31 for test tap
 proc icepick_c_tapenable {jrc port} {
 
+	if { ($port >= 0) && ($port < 16) } {
+		# Debug tap"
+		set tap $port
+		set block 0x2
+	} elseif { $port < 32 } {
+		# Test tap
+		set tap [expr ($port - 16)]
+		set block 0x1
+	} else {
+		echo "ERROR: Invalid ICEPick C port number: $port"
+		return
+	}
+
 	# First CONNECT to the ICEPick
 #	echo "Connecting to ICEPick"
 	icepick_c_connect $jrc
@@ -90,18 +103,18 @@ proc icepick_c_tapenable {jrc port} {
 	# And never to enter RESET, which will disable the TAPs.
 
 	# first enable power and clock for TAP
-	icepick_c_router $jrc 1 0x2 $port 0x110048
+	icepick_c_router $jrc 1 $block $tap 0x110048
 
 	# TRM states that the register should be read back here, skipped for now
 
 	# enable debug "default" mode
-	icepick_c_router $jrc 1 0x2 $port 0x112048
+	icepick_c_router $jrc 1 $block $tap 0x112048
 
 	# TRM states that debug enable and debug mode should be read back and
 	# confirmed - skipped for now
 
 	# Finally select the tap
-	icepick_c_router $jrc 1 0x2 $port 0x112148
+	icepick_c_router $jrc 1 $block $tap 0x112148
 
 	# Enter the bypass state
 	irscan $jrc [CONST IR_BYPASS] -endstate RUN/IDLE
@@ -119,6 +132,7 @@ proc icepick_d_set_core_control {jrc coreid value } {
 # Follow the sequence described in
 # http://processors.wiki.ti.com/images/f/f6/Router_Scan_Sequence-ICEpick-D.pdf
 proc icepick_d_tapenable {jrc port coreid { value 0x2008 } } {
+
 	# First CONNECT to the ICEPick
 	icepick_c_connect $jrc
 	icepick_c_setup $jrc
@@ -140,4 +154,3 @@ proc icepick_c_wreset {jrc} {
 	# send a router write, block is 0, register is 1, value is 0x2100
 	icepick_c_router $jrc 1 0x0 0x1 0x002101
 }
-
diff --git a/tcl/target/imx.cfg b/tcl/target/imx.cfg
index 9eea53e..ccfddb6 100644
--- a/tcl/target/imx.cfg
+++ b/tcl/target/imx.cfg
@@ -6,7 +6,7 @@ set TARGETNAME $_TARGETNAME
 # rewrite commands of the form below to arm11 mcr...
 #	Data.Set c15:0x042f %long 0x40000015
 proc setc15 {regs value} {
-	global TARGETNAME 
+	global TARGETNAME
 
 	echo [format "set p15 0x%04x, 0x%08x" $regs $value]
 
diff --git a/tcl/target/imx28.cfg b/tcl/target/imx28.cfg
index 4cc3950..1fea3fa 100644
--- a/tcl/target/imx28.cfg
+++ b/tcl/target/imx28.cfg
@@ -4,7 +4,7 @@
 reset_config trst_and_srst
 
 #jtag nTRST and nSRST delay
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 
 if { [info exists CHIPNAME] } {
diff --git a/tcl/target/imx31.cfg b/tcl/target/imx31.cfg
index ca63951..d850657 100644
--- a/tcl/target/imx31.cfg
+++ b/tcl/target/imx31.cfg
@@ -3,7 +3,7 @@
 
 reset_config trst_and_srst srst_gates_jtag
 
-adapter_nsrst_delay 5
+adapter srst delay 5
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/imx6.cfg b/tcl/target/imx6.cfg
index f359346..2945334 100644
--- a/tcl/target/imx6.cfg
+++ b/tcl/target/imx6.cfg
@@ -75,7 +75,7 @@ proc imx6_dbginit {target} {
 }
 
 # Slow speed to be sure it will work
-adapter_khz 1000
-$_TARGETNAME configure -event reset-start { adapter_khz 1000 }
+adapter speed 1000
+$_TARGETNAME configure -event reset-start { adapter speed 1000 }
 
 $_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME"
diff --git a/tcl/target/infineon/tle987x.cfg b/tcl/target/infineon/tle987x.cfg
new file mode 100644
index 0000000..84cc238
--- /dev/null
+++ b/tcl/target/infineon/tle987x.cfg
@@ -0,0 +1,36 @@
+#
+# Infineon TLE987x family (Arm Cortex-M3 @ up to 40 MHz)
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME tle987x
+}
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CPU_SWD_TAPID] } {
+	set _CPU_SWD_TAPID $CPU_SWD_TAPID
+} else {
+	set _CPU_SWD_TAPID 0x2BA01477
+}
+
+if { [using_jtag] } {
+	# JTAG not supported, only SWD
+	set _CPU_TAPID 0
+} else {
+	set _CPU_TAPID $_CPU_SWD_TAPID
+}
+
+swj_newdap $_CHIPNAME dap -irlen 4 -expected-id $_CPU_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+if { ![using_hla] } {
+	cortex_m reset_config sysresetreq
+}
+
+adapter speed 1000
diff --git a/tcl/target/is5114.cfg b/tcl/target/is5114.cfg
index 31f1aa1..1a06b09 100644
--- a/tcl/target/is5114.cfg
+++ b/tcl/target/is5114.cfg
@@ -23,7 +23,7 @@ if { [info exists CPUTAPID] } {
 }
 
 # jtag speed. We need to stick to 16kHz until we've finished reset.
-adapter_khz 16
+adapter speed 16
 
 reset_config trst_and_srst
 
@@ -38,9 +38,9 @@ jtag newtap $_CHIPNAME unknown2 -irlen 5 -ircapture 1 -irmask 1
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
 
-$_TARGETNAME configure -event reset-start { adapter_khz 16 }
+$_TARGETNAME configure -event reset-start { adapter speed 16 }
 $_TARGETNAME configure -event reset-init {
 	# We can increase speed now that we know the target is halted.
-	adapter_khz 3000
+	adapter speed 3000
 }
 $_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 1
diff --git a/tcl/target/ixp42x.cfg b/tcl/target/ixp42x.cfg
index d7b5bf4..624fe29 100644
--- a/tcl/target/ixp42x.cfg
+++ b/tcl/target/ixp42x.cfg
@@ -66,8 +66,8 @@ set IXP42x_SDRAM_256MB_32Mx16_2BANK	0x0015
 
 # helper function to init SDRAM on IXP42x.
 # SDRAM_CFG: one of IXP42X_SDRAM_xxx
-# REFRESH: refresh counter reload value (integer) 
-# CASLAT: 2 or 3 
+# REFRESH: refresh counter reload value (integer)
+# CASLAT: 2 or 3
 proc ixp42x_init_sdram { SDRAM_CFG REFRESH CASLAT } {
 
     switch $CASLAT {
@@ -104,4 +104,3 @@ proc ixp42x_init_sdram { SDRAM_CFG REFRESH CASLAT } {
 proc ixp42x_set_bigendian { } {
     reg XSCALE_CTRL 0xF8
 }
-
diff --git a/tcl/target/k1921vk01t.cfg b/tcl/target/k1921vk01t.cfg
index 1a84021..926f3c7 100755..100644
--- a/tcl/target/k1921vk01t.cfg
+++ b/tcl/target/k1921vk01t.cfg
@@ -40,9 +40,9 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 
 flash bank $_CHIPNAME.flash niietcm4 0 0 0 0 $_TARGETNAME
 
-adapter_khz 2000
+adapter speed 2000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
    jtag_ntrst_delay 100
 }
diff --git a/tcl/target/ke0x.cfg b/tcl/target/ke0x.cfg
index 8239400..b92721f 100644
--- a/tcl/target/ke0x.cfg
+++ b/tcl/target/ke0x.cfg
@@ -35,7 +35,7 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
 
-adapter_khz 1000
+adapter speed 1000
 
 reset_config srst_nogate
 
diff --git a/tcl/target/klx.cfg b/tcl/target/klx.cfg
index 5d9286a..84f6535 100644
--- a/tcl/target/klx.cfg
+++ b/tcl/target/klx.cfg
@@ -40,7 +40,7 @@ kinetis create_banks
 # Table 5-1. Clock Summary of KL25 Sub-Family Reference Manual
 # specifies up to 1MHz for VLPR mode and up to 24MHz for run mode;
 # Table 17 of Sub-Family Data Sheet rev4 lists 25MHz as the maximum frequency.
-adapter_khz 1000
+adapter speed 1000
 
 reset_config srst_nogate
 
@@ -56,9 +56,9 @@ if {[using_hla]} {
    echo " it without mass erase. Don't set write protection on the first block."
    echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!"
    echo ""
-} {
-   # Detect secured MCU or boot lock-up in RESET/WDOG loop
-   $_CHIPNAME.cpu configure -event examine-start {
+} else {
+   # Detect secured MCU
+   $_TARGETNAME configure -event examine-fail {
       kinetis mdm check_security
    }
 
diff --git a/tcl/target/ks869x.cfg b/tcl/target/ks869x.cfg
index 0f6829c..78cc402 100644
--- a/tcl/target/ks869x.cfg
+++ b/tcl/target/ks869x.cfg
@@ -18,7 +18,7 @@ if { [info exists CPUTAPID] } {
    set  _CPUTAPID 0x00922f0f
 }
 
-adapter_khz 6000
+adapter speed 6000
 
 # jtag scan chain
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
diff --git a/tcl/target/kx.cfg b/tcl/target/kx.cfg
index 73ee62a..9fda4ed 100644
--- a/tcl/target/kx.cfg
+++ b/tcl/target/kx.cfg
@@ -41,7 +41,7 @@ set _FLASHNAME $_CHIPNAME.pflash
 flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
 kinetis create_banks
 
-adapter_khz 1000
+adapter speed 1000
 
 reset_config srst_nogate
 
@@ -58,9 +58,13 @@ if {[using_hla]} {
    echo " it without mass erase. Don't set write protection on the first block."
    echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!"
    echo ""
-} {
+} else {
    # Detect secured MCU or boot lock-up in RESET/WDOG loop
-   $_CHIPNAME.cpu configure -event examine-start {
+   $_TARGETNAME configure -event examine-fail {
+      kinetis mdm check_security
+   }
+   # During RESET/WDOG loop the target is sometimes falsely examined
+   $_TARGETNAME configure -event examine-end {
       kinetis mdm check_security
    }
 
@@ -75,4 +79,3 @@ if {[using_hla]} {
 $_TARGETNAME configure -event reset-init {
    kinetis disable_wdog
 }
-
diff --git a/tcl/target/lpc1850.cfg b/tcl/target/lpc1850.cfg
index 925a049..481dc8a 100644
--- a/tcl/target/lpc1850.cfg
+++ b/tcl/target/lpc1850.cfg
@@ -1,6 +1,6 @@
 source [find target/swj-dp.tcl]
 
-adapter_khz 500
+adapter speed 500
 
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/lpc1xxx.cfg b/tcl/target/lpc1xxx.cfg
index 1969e46..946d1ce 100644
--- a/tcl/target/lpc1xxx.cfg
+++ b/tcl/target/lpc1xxx.cfg
@@ -145,10 +145,10 @@ if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "l
 # Run with *real slow* clock by default since the
 # boot rom could have been playing with the PLL, so
 # we have no idea what clock the target is running at.
-adapter_khz 10
+adapter speed 10
 
 # delays on reset lines
-adapter_nsrst_delay 200
+adapter srst delay 200
 if {[using_jtag]} {
  jtag_ntrst_delay 200
 }
diff --git a/tcl/target/lpc2103.cfg b/tcl/target/lpc2103.cfg
index f55777f..131b9ef 100644
--- a/tcl/target/lpc2103.cfg
+++ b/tcl/target/lpc2103.cfg
@@ -15,7 +15,7 @@ proc setup_lpc2103 {core_freq_khz adapter_freq_khz} {
 proc init_targets {} {
 	# default to core clocked with 12MHz crystal
 	echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
-	
+
 	# setup_lpc2103 <core_freq_khz> <adapter_freq_khz>
 	setup_lpc2103 12000 1500
 }
diff --git a/tcl/target/lpc2124.cfg b/tcl/target/lpc2124.cfg
index 0251738..ddbde22 100644
--- a/tcl/target/lpc2124.cfg
+++ b/tcl/target/lpc2124.cfg
@@ -15,7 +15,7 @@ proc setup_lpc2124 {core_freq_khz adapter_freq_khz} {
 proc init_targets {} {
 	# default to core clocked with 12MHz crystal
 	echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
-	
+
 	# setup_lpc2124 <core_freq_khz> <adapter_freq_khz>
 	setup_lpc2124 12000 1500
 }
diff --git a/tcl/target/lpc2129.cfg b/tcl/target/lpc2129.cfg
index 2c33cde..a1c3fe7 100644
--- a/tcl/target/lpc2129.cfg
+++ b/tcl/target/lpc2129.cfg
@@ -15,7 +15,7 @@ proc setup_lpc2129 {core_freq_khz adapter_freq_khz} {
 proc init_targets {} {
 	# default to core clocked with 12MHz crystal
 	echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
-	
+
 	# setup_lpc2129 <core_freq_khz> <adapter_freq_khz>
 	setup_lpc2129 12000 1500
 }
diff --git a/tcl/target/lpc2148.cfg b/tcl/target/lpc2148.cfg
index f3a2011..503a682 100644
--- a/tcl/target/lpc2148.cfg
+++ b/tcl/target/lpc2148.cfg
@@ -15,7 +15,7 @@ proc setup_lpc2148 {core_freq_khz adapter_freq_khz} {
 proc init_targets {} {
 	# default to core clocked with 12MHz crystal
 	echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
-	
+
 	# setup_lpc2148 <core_freq_khz> <adapter_freq_khz>
 	setup_lpc2148 12000 1500
 }
diff --git a/tcl/target/lpc2294.cfg b/tcl/target/lpc2294.cfg
index 83d595d..1320cda 100644
--- a/tcl/target/lpc2294.cfg
+++ b/tcl/target/lpc2294.cfg
@@ -9,7 +9,7 @@ source [find target/lpc2xxx.cfg]
 proc setup_lpc2294 {core_freq_khz adapter_freq_khz} {
 	# 256kB flash and 16kB SRAM
 	# setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>
-	
+
 	# !! TAPID unknown !!
 	setup_lpc2xxx lpc2294 0xffffffff 0x40000 lpc2000_v1 0x4000 $core_freq_khz $adapter_freq_khz
 }
@@ -17,7 +17,7 @@ proc setup_lpc2294 {core_freq_khz adapter_freq_khz} {
 proc init_targets {} {
 	# default to core clocked with 12MHz crystal
 	echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
-	
+
 	# setup_lpc2294 <core_freq_khz> <adapter_freq_khz>
 	setup_lpc2294 12000 1500
 }
diff --git a/tcl/target/lpc2378.cfg b/tcl/target/lpc2378.cfg
index 0b66b82..235456a 100644
--- a/tcl/target/lpc2378.cfg
+++ b/tcl/target/lpc2378.cfg
@@ -15,7 +15,7 @@ proc setup_lpc2378 {core_freq_khz adapter_freq_khz} {
 proc init_targets {} {
 	# default to core clocked with 4MHz internal oscillator
 	echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different."
-	
+
 	# setup_lpc2378 <core_freq_khz> <adapter_freq_khz>
 	setup_lpc2378 4000 500
 }
diff --git a/tcl/target/lpc2460.cfg b/tcl/target/lpc2460.cfg
index 69fdc4a..c229f6d 100644
--- a/tcl/target/lpc2460.cfg
+++ b/tcl/target/lpc2460.cfg
@@ -15,7 +15,7 @@ proc setup_lpc2460 {core_freq_khz adapter_freq_khz} {
 proc init_targets {} {
 	# default to core clocked with 4MHz internal oscillator
 	echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different."
-	
+
 	# setup_lpc2460 <core_freq_khz> <adapter_freq_khz>
 	setup_lpc2460 4000 500
 }
diff --git a/tcl/target/lpc2478.cfg b/tcl/target/lpc2478.cfg
index 48e5bdf..36b5c46 100644
--- a/tcl/target/lpc2478.cfg
+++ b/tcl/target/lpc2478.cfg
@@ -15,7 +15,7 @@ proc setup_lpc2478 {core_freq_khz adapter_freq_khz} {
 proc init_targets {} {
 	# default to core clocked with 4MHz internal oscillator
 	echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different."
-	
+
 	# setup_lpc2478 <core_freq_khz> <adapter_freq_khz>
 	setup_lpc2478 4000 500
 }
diff --git a/tcl/target/lpc2900.cfg b/tcl/target/lpc2900.cfg
index 5367787..523bc21 100644
--- a/tcl/target/lpc2900.cfg
+++ b/tcl/target/lpc2900.cfg
@@ -14,7 +14,7 @@ if { [info exists CPUTAPID] } {
 if { [info exists HAS_ETB] } {
 } else {
     # Set default (no ETB).
-    # Show a warning, because this should have been configured explicitely.
+    # Show a warning, because this should have been configured explicitly.
     set HAS_ETB 0
     # TODO: warning?
 }
diff --git a/tcl/target/lpc2xxx.cfg b/tcl/target/lpc2xxx.cfg
index 11f1c48..f947c1b 100644
--- a/tcl/target/lpc2xxx.cfg
+++ b/tcl/target/lpc2xxx.cfg
@@ -13,10 +13,10 @@ proc setup_lpc2xxx {chip_name cputapids flash_size flash_variant workarea_size c
 	reset_config trst_and_srst
 
 	# reset delays
-	adapter_nsrst_delay 100
+	adapter srst delay 100
 	jtag_ntrst_delay 100
 
-	adapter_khz $adapter_freq_khz
+	adapter speed $adapter_freq_khz
 
 	foreach i $cputapids {
 		append expected_ids "-expected-id " $i " "
@@ -40,5 +40,5 @@ proc setup_lpc2xxx {chip_name cputapids flash_size flash_variant workarea_size c
 proc init_targets {} {
 	# FIX!!! read out CPUTAPID here and choose right setup. In addition to the
 	# CPUTAPID some querying of the target would be required.
-	return -error "This is a generic LPC2xxx configuration file, use a specific target file." 
+	return -error "This is a generic LPC2xxx configuration file, use a specific target file."
 }
diff --git a/tcl/target/lpc3131.cfg b/tcl/target/lpc3131.cfg
index 27c1f67..89bbf02 100644
--- a/tcl/target/lpc3131.cfg
+++ b/tcl/target/lpc3131.cfg
@@ -22,7 +22,7 @@ if { [info exists CPUTAPID] } {
 }
 
 # Scan Tap
-# Wired to seperate STDO pin on the lpc3131, externally muxed to TDO on ea3131 module 
+# Wired to separate STDO pin on the lpc3131, externally muxed to TDO on ea3131 module
 # JTAGSEL pin must be 0 to activate, which reassigns arm tdo to a pass through.
 if { [info exists SJCTAPID] } {
    set _SJCTAPID $SJCTAPID
@@ -52,11 +52,11 @@ dict set lpc313x wdt			0x13002400
 # Target configuration
 ##################################################################
 
-adapter_nsrst_delay 1000
+adapter srst delay 1000
 jtag_ntrst_delay 0
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME 
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
 
 $_TARGETNAME invoke-event halted
 
diff --git a/tcl/target/lpc4350.cfg b/tcl/target/lpc4350.cfg
index 2b72884..0c6d0ff 100644
--- a/tcl/target/lpc4350.cfg
+++ b/tcl/target/lpc4350.cfg
@@ -1,6 +1,6 @@
 source [find target/swj-dp.tcl]
 
-adapter_khz 500
+adapter speed 500
 
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/lpc4370.cfg b/tcl/target/lpc4370.cfg
index 1374ef2..9db2b9e 100644
--- a/tcl/target/lpc4370.cfg
+++ b/tcl/target/lpc4370.cfg
@@ -2,7 +2,7 @@
 # NXP LPC4370 - 1x ARM Cortex-M4 + 2x ARM Cortex-M0 @ up to 204 MHz each
 #
 
-adapter_khz 500
+adapter speed 500
 
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/lpc8nxx.cfg b/tcl/target/lpc8nxx.cfg
index b933290..1bc77b2 100644
--- a/tcl/target/lpc8nxx.cfg
+++ b/tcl/target/lpc8nxx.cfg
@@ -22,7 +22,7 @@ if {![using_hla]} {
 	# If srst is not fitted use SYSRESETREQ to  perform a soft reset
 	cortex_m reset_config sysresetreq
 }
-adapter_nsrst_delay 100
+adapter srst delay 100
 
 $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x1ff0 -work-area-backup 0
 
diff --git a/tcl/target/ls1012a.cfg b/tcl/target/ls1012a.cfg
index 9a9e684..19d3e58 100644
--- a/tcl/target/ls1012a.cfg
+++ b/tcl/target/ls1012a.cfg
@@ -32,4 +32,4 @@ target create $_TARGETNAME aarch64 -dap $_CHIPNAME.dap -dbgbase 0x80410000 -cti
 
 target smp $_TARGETNAME
 
-adapter_khz 2000
+adapter speed 2000
diff --git a/tcl/target/max32620.cfg b/tcl/target/max32620.cfg
index 80cb25a..6187bb9 100644
--- a/tcl/target/max32620.cfg
+++ b/tcl/target/max32620.cfg
@@ -2,7 +2,7 @@
 # www.maximintegrated.com
 
 # adapter speed
-adapter_khz 4000
+adapter speed 4000
 
 # reset pin configuration
 reset_config srst_only
diff --git a/tcl/target/max32625.cfg b/tcl/target/max32625.cfg
index 7182b23..159b360 100644
--- a/tcl/target/max32625.cfg
+++ b/tcl/target/max32625.cfg
@@ -2,7 +2,7 @@
 # www.maximintegrated.com
 
 # adapter speed
-adapter_khz 4000
+adapter speed 4000
 
 # reset pin configuration
 reset_config srst_only
diff --git a/tcl/target/max3263x.cfg b/tcl/target/max3263x.cfg
index f23b0b6..fc7d11f 100644
--- a/tcl/target/max3263x.cfg
+++ b/tcl/target/max3263x.cfg
@@ -2,7 +2,7 @@
 # www.maximintegrated.com
 
 # adapter speed
-adapter_khz 4000
+adapter speed 4000
 
 # reset pin configuration
 reset_config srst_only
diff --git a/tcl/target/mc13224v.cfg b/tcl/target/mc13224v.cfg
index 27ac8c3..f756dd9 100644
--- a/tcl/target/mc13224v.cfg
+++ b/tcl/target/mc13224v.cfg
@@ -35,8 +35,8 @@ reset_config srst_only
 jtag_ntrst_delay 200
 
 # rclk hasn't been working well. This maybe the mc13224v or something else.
-#adapter_khz 2000
-adapter_khz 2000
+#adapter speed 2000
+adapter speed 2000
 
 ######################
 # Target configuration
diff --git a/tcl/target/mdr32f9q2i.cfg b/tcl/target/mdr32f9q2i.cfg
index 6748102..820d2dd 100644
--- a/tcl/target/mdr32f9q2i.cfg
+++ b/tcl/target/mdr32f9q2i.cfg
@@ -49,9 +49,9 @@ if { [info exists IMEMORY] && [string equal $IMEMORY true] } {
 }
 
 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
+adapter speed 1000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
    jtag_ntrst_delay 100
 }
diff --git a/tcl/target/nrf51.cfg b/tcl/target/nrf51.cfg
index 4f24020..d51a50e 100644
--- a/tcl/target/nrf51.cfg
+++ b/tcl/target/nrf51.cfg
@@ -50,7 +50,7 @@ flash bank $_CHIPNAME.uicr nrf51 0x10001000 0 1 1 $_TARGETNAME
 #  The chip should start up from internal 16Mhz RC, so setting adapter
 #  clock to 1Mhz should be OK
 #
-adapter_khz 1000
+adapter speed 1000
 
 proc enable_all_ram {} {
 	# nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM banks
diff --git a/tcl/target/nrf52.cfg b/tcl/target/nrf52.cfg
index c29adbd..88f2c69 100644
--- a/tcl/target/nrf52.cfg
+++ b/tcl/target/nrf52.cfg
@@ -30,13 +30,86 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
 
-adapter_khz 1000
+adapter speed 1000
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
-if { ![using_hla] } {
+if { [using_hla] } {
+	echo ""
+	echo "nRF52 device has a CTRL-AP dedicated to recover the device from AP lock."
+	echo "A high level adapter (like a ST-Link) you are currently using cannot access"
+	echo "the CTRL-AP so 'nrf52_recover' command will not work."
+	echo "Do not enable UICR APPROTECT."
+	echo ""
+} else {
 	cortex_m reset_config sysresetreq
+
+	$_TARGETNAME configure -event examine-fail nrf52_check_ap_lock
 }
 
 flash bank $_CHIPNAME.flash nrf5 0x00000000 0 1 1 $_TARGETNAME
 flash bank $_CHIPNAME.uicr nrf5 0x10001000 0 1 1 $_TARGETNAME
+
+# Test if MEM-AP is locked by UICR APPROTECT
+proc nrf52_check_ap_lock {} {
+	set dap [[target current] cget -dap]
+	set err [catch {set APPROTECTSTATUS [ocd_$dap apreg 1 0xc]}]
+	if {$err == 0 && $APPROTECTSTATUS != 1} {
+		echo "****** WARNING ******"
+		echo "nRF52 device has AP lock engaged (see UICR APPROTECT register)."
+		echo "Debug access is denied."
+		echo "Use 'nrf52_recover' to erase and unlock the device."
+		echo ""
+		poll off
+	}
+}
+
+# Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #1)
+# http://www.ebyte.com produces modules with nRF52 locked by default,
+# use nrf52_recover to enable flashing and debug.
+proc nrf52_recover {} {
+	set target [target current]
+	set dap [$target cget -dap]
+
+	set IDR [ocd_$dap apreg 1 0xfc]
+	if {$IDR != 0x02880000} {
+		echo "Error: Cannot access nRF52 CTRL-AP!"
+		return
+	}
+
+	poll off
+
+	# Assert reset
+	$dap apreg 1 0 1
+
+	# Reset ERASEALLSTATUS event
+	$dap apreg 1 8 0
+
+	# Trigger ERASEALL task
+	$dap apreg 1 4 0
+	$dap apreg 1 4 1
+
+	for {set i 0} {1} {incr i} {
+		set ERASEALLSTATUS [ocd_$dap apreg 1 8]
+		if {$ERASEALLSTATUS == 1} {
+			echo "$target device has been successfully erased and unlocked."
+			break
+		}
+		if {$i >= 5} {
+			echo "Error: $target recovery failed."
+			break
+		}
+		sleep 100
+	}
+
+	# Deassert reset
+	$dap apreg 1 0 0
+
+	if {$ERASEALLSTATUS == 1} {
+		sleep 100
+		$target arp_examine
+		poll on
+	}
+}
+
+add_help_text nrf52_recover "Mass erase and unlock nRF52 device"
diff --git a/tcl/target/numicro.cfg b/tcl/target/numicro.cfg
index c42dfbc..73022df 100644
--- a/tcl/target/numicro.cfg
+++ b/tcl/target/numicro.cfg
@@ -48,7 +48,7 @@ set _FLASHNAME $_CHIPNAME.flash_config
 flash bank $_FLASHNAME numicro 0x00300000 0 0 0 $_TARGETNAME
 
 # set default SWCLK frequency
-adapter_khz 1000
+adapter speed 1000
 
 # set default srst setting "none"
 reset_config none
diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg
index 078d7f2..dcf7c51 100644
--- a/tcl/target/omap3530.cfg
+++ b/tcl/target/omap3530.cfg
@@ -63,8 +63,8 @@ proc omap3_dbginit {target} {
 # be absolutely certain the JTAG clock will work with the worst-case
 # 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
 # OK to speed up *after* PLL and clock tree setup.
-adapter_khz 1000
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1000 }
+adapter speed 1000
+$_TARGETNAME configure -event "reset-start" { adapter speed 1000 }
 
 # Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
 # ourselves using PRM_RSTCTRL.  RST_GS (2) is a warm reset, like ICEpick
diff --git a/tcl/target/omap5912.cfg b/tcl/target/omap5912.cfg
index c4ff40e..2f9338b 100644
--- a/tcl/target/omap5912.cfg
+++ b/tcl/target/omap5912.cfg
@@ -14,7 +14,7 @@ if { [info exists CPUTAPID] } {
    set _CPUTAPID 0x0692602f
 }
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 
 # NOTE: presumes irlen 38 is the C55x DSP, matching BSDL for
 # its standalone siblings (like TMS320VC5502) of the same era
diff --git a/tcl/target/omapl138.cfg b/tcl/target/omapl138.cfg
index fd9ff4c..30cf23c 100644
--- a/tcl/target/omapl138.cfg
+++ b/tcl/target/omapl138.cfg
@@ -52,8 +52,8 @@ $_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000
 # be absolutely certain the JTAG clock will work with the worst-case
 # CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
 # on the PLL and starts using it.  OK to speed up after clock setup.
-adapter_khz 1500
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
 
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable
diff --git a/tcl/target/pic32mx.cfg b/tcl/target/pic32mx.cfg
index d53b99a..51a6bbd 100644
--- a/tcl/target/pic32mx.cfg
+++ b/tcl/target/pic32mx.cfg
@@ -23,7 +23,7 @@ if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE 0x4000
 }
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 
 #jtag scan chain
diff --git a/tcl/target/psoc4.cfg b/tcl/target/psoc4.cfg
index 544e109..b568282 100644
--- a/tcl/target/psoc4.cfg
+++ b/tcl/target/psoc4.cfg
@@ -36,7 +36,7 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
 
-adapter_khz 1500
+adapter speed 1500
 
 # Reset, bloody PSoC 4 reset
 #
@@ -118,7 +118,7 @@ proc ocd_process_reset_inner { MODE } {
 	}
 
 	if { ! [info exists PSOC4_USE_ACQUIRE] } {
-		if { 0 == [string compare [adapter_name] kitprog ] } {
+		if { 0 == [string compare [adapter name] kitprog ] } {
 			set PSOC4_USE_ACQUIRE 1
 		} else {
 			set PSOC4_USE_ACQUIRE 0
@@ -138,7 +138,7 @@ proc ocd_process_reset_inner { MODE } {
 	$t invoke-event reset-assert-pre
 
 	if { $halt && $PSOC4_USE_ACQUIRE } {
-		catch { [adapter_name] acquire_psoc }
+		catch { [adapter name] acquire_psoc }
 		$t arp_examine
 	} else {
 		if { $PSOC4_TEST_MODE_WORKAROUND } {
diff --git a/tcl/target/psoc6.cfg b/tcl/target/psoc6.cfg
index fc0c711..51d032b 100644
--- a/tcl/target/psoc6.cfg
+++ b/tcl/target/psoc6.cfg
@@ -6,7 +6,7 @@
 
 source [find target/swj-dp.tcl]
 
-adapter_khz 1000
+adapter speed 1000
 
 global _CHIPNAME
 if { [info exists CHIPNAME] } {
diff --git a/tcl/target/pxa255.cfg b/tcl/target/pxa255.cfg
index 3862425..73518bf 100644
--- a/tcl/target/pxa255.cfg
+++ b/tcl/target/pxa255.cfg
@@ -28,8 +28,8 @@ target create $_TARGETNAME xscale -endian $_ENDIAN \
 # PXA255 comes out of reset using 3.6864 MHz oscillator.
 # Until the PLL kicks in, keep the JTAG clock slow enough
 # that we get no errors.
-adapter_khz 300
-$_TARGETNAME configure -event "reset-start" { adapter_khz 300 }
+adapter speed 300
+$_TARGETNAME configure -event "reset-start" { adapter speed 300 }
 
 # both TRST and SRST are *required* for debug
 # DCSR is often accessed with SRST active
@@ -38,11 +38,11 @@ reset_config trst_and_srst separate srst_nogate
 # reset processing that works with PXA
 proc init_reset {mode} {
 	# assert both resets; equivalent to power-on reset
-	jtag_reset 1 1
+	adapter assert trst assert srst
 
 	# drop TRST after at least 32 cycles
 	sleep 1
-	jtag_reset 0 1
+	adapter deassert trst assert srst
 
 	# minimum 32 TCK cycles to wake up the controller
 	runtest 50
@@ -51,7 +51,7 @@ proc init_reset {mode} {
 	jtag arp_init
 
 	# ... and take it out of reset
-	jtag_reset 0 0
+	adapter deassert trst deassert srst
 }
 
 proc jtag_init {} {
diff --git a/tcl/target/pxa270.cfg b/tcl/target/pxa270.cfg
index 95f7f16..bd904b5 100644
--- a/tcl/target/pxa270.cfg
+++ b/tcl/target/pxa270.cfg
@@ -34,9 +34,9 @@ if { [info exists CPUTAPID3] } {
    set _CPUTAPID3 0x89265013
 }
 
-# set adapter_nsrst_delay to the delay introduced by your reset circuit
+# set adapter srst delay to the delay introduced by your reset circuit
 # the rest of the needed delays are built into the openocd program
-adapter_nsrst_delay 260
+adapter srst delay 260
 # set the jtag_ntrst_delay to the delay introduced by a reset circuit
 # the rest of the needed delays are built into the openocd program
 jtag_ntrst_delay 250
diff --git a/tcl/target/pxa3xx.cfg b/tcl/target/pxa3xx.cfg
index c459f6e..1a4539c 100644
--- a/tcl/target/pxa3xx.cfg
+++ b/tcl/target/pxa3xx.cfg
@@ -59,9 +59,9 @@ if { [info exists CPUTAPID_PXA32X_C0] } {
    set _CPUTAPID_PXA32X_C0 0x7E642013
 }
 
-# set adapter_nsrst_delay to the delay introduced by your reset circuit
+# set adapter srst delay to the delay introduced by your reset circuit
 # the rest of the needed delays are built into the openocd program
-adapter_nsrst_delay 260
+adapter srst delay 260
 
 # set the jtag_ntrst_delay to the delay introduced by a reset circuit
 # the rest of the needed delays are built into the openocd program
diff --git a/tcl/target/qualcomm_qca4531.cfg b/tcl/target/qualcomm_qca4531.cfg
index 3d21578..0b046b8 100644
--- a/tcl/target/qualcomm_qca4531.cfg
+++ b/tcl/target/qualcomm_qca4531.cfg
@@ -38,12 +38,12 @@ reset_config none srst_pulls_trst
 # For SRST based variant we still need proper timings.
 # For ETH part the reset should be asserted at least for 10ms
 # Since there is no other information let's take 100ms to be sure.
-adapter_nsrst_assert_width 100
+adapter srst pulse_width 100
 
 # according to the SoC documentation it should take at least 5ms from
 # reset end till bootstrap end. In the practice we need 8ms to get JTAG back
 # to live.
-adapter_nsrst_delay 8
+adapter srst delay 8
 
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $_CHIPNAME
diff --git a/tcl/target/readme.txt b/tcl/target/readme.txt
index f028b11..91bb2d5 100644
--- a/tcl/target/readme.txt
+++ b/tcl/target/readme.txt
@@ -26,16 +26,15 @@ assumed that all write-protect mechanisms should be disabled.
 flash write_image [file] <parameters>
 verify_image [file] <parameters>
 
-4. adapter_khz sets the maximum speed (or alternatively RCLK). If invoked
+4. adapter speed sets the maximum speed (or alternatively RCLK). If invoked
 multiple times only the last setting is used.
 
 interface/xxx.cfg files are always executed *before* target/xxx.cfg
-files, so any adapter_khz in interface/xxx.cfg will be overridden by
-target/xxx.cfg. adapter_khz in interface/xxx.cfg would then, effectively,
+files, so any adapter speed in interface/xxx.cfg will be overridden by
+target/xxx.cfg. adapter speed in interface/xxx.cfg would then, effectively,
 set the default JTAG speed.
 
 Note that a target/xxx.cfg file can invoke another target/yyy.cfg file,
 so one can create target subtype configurations where e.g. only
 amount of DRAM, oscillator speeds differ and having a single
 config file for the default/common settings.
-
diff --git a/tcl/target/renesas_r7s72100.cfg b/tcl/target/renesas_r7s72100.cfg
index f9466fc..5220b3c 100644
--- a/tcl/target/renesas_r7s72100.cfg
+++ b/tcl/target/renesas_r7s72100.cfg
@@ -1,4 +1,4 @@
-# Renesas R-Car RZ/A1H
+# Renesas RZ/A1H
 # https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rza/rza1h.html
 
 if { [info exists DAP_TAPID] } {
diff --git a/tcl/target/renesas_r8a7790.cfg b/tcl/target/renesas_r8a7790.cfg
deleted file mode 100644
index a662b6b..0000000
--- a/tcl/target/renesas_r8a7790.cfg
+++ /dev/null
@@ -1,36 +0,0 @@
-# Renesas R-Car H2
-# https://www.renesas.com/en-us/solutions/automotive/products/rcar-h2.html
-
-if { [info exists DAP_TAPID] } {
-	set _DAP_TAPID $DAP_TAPID
-} else {
-	set _DAP_TAPID 0x4ba00477
-}
-
-if { [info exists CHIPNAME] } {
-	set _CHIPNAME $CHIPNAME
-} else {
-	set _CHIPNAME r8a7790
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID
-
-# Configuring only one core using DAP.
-# Base addresses of Cortex A15 cores:
-#  core 0  -  0x800B0000
-#  core 1  -  0x800B2000
-#  core 2  -  0x800B4000
-#  core 3  -  0x800B6000
-# Base addresses of Cortex A7 cores (not supported yet):
-#  core 0  -  0x800F0000
-#  core 1  -  0x800F2000
-#  core 2  -  0x800F4000
-#  core 3  -  0x800F6000
-set _TARGETNAME $_CHIPNAME.ca15.
-dap create ${_CHIPNAME}.dap -chain-position $_CHIPNAME.cpu
-target create ${_TARGETNAME}0 cortex_a -dap ${_CHIPNAME}.dap -coreid 0 -dbgbase 0x800B0000
-target create ${_TARGETNAME}1 cortex_a -dap ${_CHIPNAME}.dap -coreid 1 -dbgbase 0x800B2000 -defer-examine
-target create ${_TARGETNAME}2 cortex_a -dap ${_CHIPNAME}.dap -coreid 2 -dbgbase 0x800B4000 -defer-examine
-target create ${_TARGETNAME}3 cortex_a -dap ${_CHIPNAME}.dap -coreid 3 -dbgbase 0x800B6000 -defer-examine
-
-targets ${_TARGETNAME}0
diff --git a/tcl/target/renesas_r8a7791.cfg b/tcl/target/renesas_r8a7791.cfg
deleted file mode 100644
index f93cbb8..0000000
--- a/tcl/target/renesas_r8a7791.cfg
+++ /dev/null
@@ -1,27 +0,0 @@
-# Renesas R-Car M2
-# https://www.renesas.com/en-us/solutions/automotive/products/rcar-m2.html
-
-if { [info exists DAP_TAPID] } {
-	set _DAP_TAPID $DAP_TAPID
-} else {
-	set _DAP_TAPID 0x4ba00477
-}
-
-if { [info exists CHIPNAME] } {
-	set _CHIPNAME $CHIPNAME
-} else {
-	set _CHIPNAME r8a7791
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID
-
-# Configuring only one core using DAP.
-# Base addresses of cores:
-#  core 0  -  0x800B0000
-#  core 1  -  0x800B2000
-set _TARGETNAME $_CHIPNAME.ca15.
-dap create ${_CHIPNAME}.dap -chain-position $_CHIPNAME.cpu
-target create ${_TARGETNAME}0 cortex_a -dap ${_CHIPNAME}.dap -coreid 0 -dbgbase 0x800B0000
-target create ${_TARGETNAME}1 cortex_a -dap ${_CHIPNAME}.dap -coreid 1 -dbgbase 0x800B2000 -defer-examine
-
-targets ${_TARGETNAME}0
diff --git a/tcl/target/renesas_r8a7794.cfg b/tcl/target/renesas_r8a7794.cfg
deleted file mode 100644
index e3e2724..0000000
--- a/tcl/target/renesas_r8a7794.cfg
+++ /dev/null
@@ -1,27 +0,0 @@
-# Renesas R-Car E2
-# https://www.renesas.com/en-us/solutions/automotive/products/rcar-e2.html
-
-if { [info exists DAP_TAPID] } {
-	set _DAP_TAPID $DAP_TAPID
-} else {
-	set _DAP_TAPID 0x4ba00477
-}
-
-if { [info exists CHIPNAME] } {
-	set _CHIPNAME $CHIPNAME
-} else {
-	set _CHIPNAME r8a7794
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID
-
-# Configuring only one core using DAP.
-# Base addresses of cores:
-#  core 0  -  0x800F0000
-#  core 1  -  0x800F2000
-set _TARGETNAME $_CHIPNAME.ca7.
-dap create ${_CHIPNAME}.dap -chain-position $_CHIPNAME.cpu
-target create ${_TARGETNAME}0 cortex_a -dap ${_CHIPNAME}.dap -coreid 0 -dbgbase 0x800F0000
-target create ${_TARGETNAME}1 cortex_a -dap ${_CHIPNAME}.dap -coreid 1 -dbgbase 0x800F2000 -defer-examine
-
-targets ${_TARGETNAME}0
diff --git a/tcl/target/renesas_rcar_gen2.cfg b/tcl/target/renesas_rcar_gen2.cfg
new file mode 100644
index 0000000..91baa6c
--- /dev/null
+++ b/tcl/target/renesas_rcar_gen2.cfg
@@ -0,0 +1,125 @@
+# Renesas R-Car Generation 2 SOCs
+# - There are a combination of Cortex-A15s and Cortex-A7s for each Gen2 SOC
+# - Each SOC can boot through any of the, up to 2, core types that it has
+#   e.g. H2 can boot through Cortex-A15 or Cortex-A7
+
+# Supported Gen2 SOCs and their cores:
+# H2:  Cortex-A15 x 4, Cortex-A7 x 4
+# M2:  Cortex-A15 x 2
+# V2H: Cortex-A15 x 2
+# M2N: Cortex-A15 x 2
+# E2:                  Cortex-A7 x 2
+
+# Usage:
+# There are 2 configuration options:
+# SOC:       Selects the supported SOC. (Default 'H2')
+# BOOT_CORE: Selects the booting core. 'CA15', or 'CA7'
+#            Defaults to 'CA15' if the SOC has one, else defaults to 'CA7'
+
+if { [info exists SOC] } {
+	set _soc $SOC
+} else {
+	set _soc H2
+}
+
+# Set configuration for each SOC and the default 'BOOT_CORE'
+switch $_soc {
+	H2 {
+		set _CHIPNAME r8a7790
+		set _num_ca15 4
+		set _num_ca7 4
+		set _boot_core CA15
+	}
+	M2 {
+		set _CHIPNAME r8a7791
+		set _num_ca15 2
+		set _num_ca7 0
+		set _boot_core CA15
+	}
+	V2H {
+		set _CHIPNAME r8a7792
+		set _num_ca15 2
+		set _num_ca7 0
+		set _boot_core CA15
+	}
+	M2N {
+		set _CHIPNAME r8a7793
+		set _num_ca15 2
+		set _num_ca7 0
+		set _boot_core CA15
+	}
+	E2 {
+		set _CHIPNAME r8a7794
+		set _num_ca15 0
+		set _num_ca7 2
+		set _boot_core CA7
+	}
+	default {
+		error "'$_soc' is invalid!"
+	}
+}
+
+# If configured, override the default 'CHIPNAME'
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+}
+
+# If configured, override the default 'BOOT_CORE'
+if { [info exists BOOT_CORE] } {
+	set _boot_core $BOOT_CORE
+}
+
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x4ba00477
+}
+
+echo "\t$_soc - $_num_ca15 CA15(s), $_num_ca7 CA7(s)"
+echo "\tBoot Core - $_boot_core\n"
+
+set _DAPNAME $_CHIPNAME.dap
+
+# TAP and DAP
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID
+dap create $_DAPNAME -chain-position $_CHIPNAME.cpu
+
+set CA15_DBGBASE {0x800B0000 0x800B2000 0x800B4000 0x800B6000}
+set CA7_DBGBASE  {0x800F0000 0x800F2000 0x800F4000 0x800F6000}
+
+set smp_targets ""
+
+proc setup_ca {core_name dbgbase num boot} {
+	global _CHIPNAME
+	global _DAPNAME
+	global smp_targets
+	for { set _core 0 } { $_core < $num } { incr _core } {
+		set _TARGETNAME $_CHIPNAME.$core_name.$_core
+		set _CTINAME $_TARGETNAME.cti
+		set _command "target create $_TARGETNAME cortex_a -dap $_DAPNAME \
+			-coreid $_core -dbgbase [lindex $dbgbase $_core]"
+		if { $_core == 0  && $boot == 1 } {
+			set _targets "$_TARGETNAME"
+		} else {
+			set _command "$_command -defer-examine"
+		}
+		set smp_targets "$smp_targets $_TARGETNAME"
+		eval $_command
+	}
+}
+
+# Organize target list based on the boot core
+if { [string equal $_boot_core CA15] } {
+	setup_ca a15 $CA15_DBGBASE $_num_ca15 1
+	setup_ca a7  $CA7_DBGBASE  $_num_ca7 0
+} elseif { [string equal $_boot_core CA7] } {
+	setup_ca a7  $CA7_DBGBASE  $_num_ca7 1
+	setup_ca a15 $CA15_DBGBASE $_num_ca15 0
+} else {
+	setup_ca a15 $CA15_DBGBASE $_num_ca15 0
+	setup_ca a7  $CA7_DBGBASE  $_num_ca7 0
+}
+
+source [find target/renesas_rcar_reset_common.cfg]
+
+eval "target smp $smp_targets"
diff --git a/tcl/target/renesas_rcar_gen3.cfg b/tcl/target/renesas_rcar_gen3.cfg
index 2c478b2..72f185d 100644
--- a/tcl/target/renesas_rcar_gen3.cfg
+++ b/tcl/target/renesas_rcar_gen3.cfg
@@ -76,7 +76,7 @@ switch $_soc {
 		set _boot_core CA53
 	}
 	default {
-		echo "'$_soc' is invalid!"
+		error "'$_soc' is invalid!"
 	}
 }
 
@@ -166,4 +166,6 @@ if { [string equal $_boot_core CA57] } {
 	setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0
 }
 
+source [find target/renesas_rcar_reset_common.cfg]
+
 eval "target smp $smp_targets"
diff --git a/tcl/board/renesas_gen2_common.cfg b/tcl/target/renesas_rcar_reset_common.cfg
index 00fa777..3e4579b 100644
--- a/tcl/board/renesas_gen2_common.cfg
+++ b/tcl/target/renesas_rcar_reset_common.cfg
@@ -4,10 +4,10 @@ reset_config trst_and_srst srst_nogate
 
 proc init_reset {mode} {
     # Assert both resets: equivalent to a power-on reset
-    jtag_reset 1 1
+    adapter assert trst assert srst
 
     # Deassert TRST to begin TAP communication
-    jtag_reset 0 1
+    adapter deassert trst assert srst
 
     # TAP should now be responsive, validate the scan-chain
     jtag arp_init
diff --git a/tcl/target/renesas_s7g2.cfg b/tcl/target/renesas_s7g2.cfg
index 78fb3e8..b4be88f 100644
--- a/tcl/target/renesas_s7g2.cfg
+++ b/tcl/target/renesas_s7g2.cfg
@@ -48,4 +48,4 @@ if { ![using_hla] } {
 	cortex_m reset_config sysresetreq
 }
 
-adapter_khz 1000
+adapter speed 1000
diff --git a/tcl/target/samsung_s3c2440.cfg b/tcl/target/samsung_s3c2440.cfg
index 2a0a915..a97659b 100644
--- a/tcl/target/samsung_s3c2440.cfg
+++ b/tcl/target/samsung_s3c2440.cfg
@@ -32,4 +32,3 @@ $_TARGETNAME configure -work-area-phys 0x200000 -work-area-size 0x4000 -work-are
 
 #reset configuration
 reset_config trst_and_srst
-
diff --git a/tcl/target/samsung_s3c2450.cfg b/tcl/target/samsung_s3c2450.cfg
index 1bc4f2d..2482557 100644
--- a/tcl/target/samsung_s3c2450.cfg
+++ b/tcl/target/samsung_s3c2450.cfg
@@ -7,11 +7,11 @@
 #
 # RCLK?
 #
-# adapter_khz 0
+# adapter speed 0
 #
 # Really low clock during reset?
 #
-# adapter_khz 1
+# adapter speed 1
 
 if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/samsung_s3c4510.cfg b/tcl/target/samsung_s3c4510.cfg
index 461d047..8bc5da5 100644
--- a/tcl/target/samsung_s3c4510.cfg
+++ b/tcl/target/samsung_s3c4510.cfg
@@ -21,4 +21,3 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CP
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
-
diff --git a/tcl/target/samsung_s3c6410.cfg b/tcl/target/samsung_s3c6410.cfg
index 88fe966..9f7c2cd 100644
--- a/tcl/target/samsung_s3c6410.cfg
+++ b/tcl/target/samsung_s3c6410.cfg
@@ -40,7 +40,7 @@ jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_C
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
 
-adapter_nsrst_delay 500
+adapter srst delay 500
 jtag_ntrst_delay 500
 
 #reset configuration
diff --git a/tcl/target/sharp_lh79532.cfg b/tcl/target/sharp_lh79532.cfg
index 6f2cf22..a464839 100644
--- a/tcl/target/sharp_lh79532.cfg
+++ b/tcl/target/sharp_lh79532.cfg
@@ -22,5 +22,3 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CP
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
-
-
diff --git a/tcl/target/sim3x.cfg b/tcl/target/sim3x.cfg
index ed46a3b..3d3fc5c 100755..100644
--- a/tcl/target/sim3x.cfg
+++ b/tcl/target/sim3x.cfg
@@ -48,9 +48,9 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
 
-adapter_khz 1000
+adapter speed 1000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
diff --git a/tcl/target/smp8634.cfg b/tcl/target/smp8634.cfg
index c13414c..e95f633 100644
--- a/tcl/target/smp8634.cfg
+++ b/tcl/target/smp8634.cfg
@@ -18,7 +18,7 @@ if { [info exists CPUTAPID] } {
    set _CPUTAPID 0x08630001
 }
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 
 reset_config trst_and_srst separate
diff --git a/tcl/target/snps_em_sk_fpga.cfg b/tcl/target/snps_em_sk_fpga.cfg
new file mode 100644
index 0000000..2f7fecb
--- /dev/null
+++ b/tcl/target/snps_em_sk_fpga.cfg
@@ -0,0 +1,33 @@
+#  Copyright (C) 2014-2015,2020 Synopsys, Inc.
+#  Anton Kolesov <anton.kolesov@synopsys.com>
+#  Didin Evgeniy <didin@synopsys.com>
+#
+#  SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Xilinx Spartan-6 XC6SLX45  FPGA on EM Starter Kit v1.
+# Xilinx Spartan-6 XC6SLX150 FPGA on EM Starter Kit v2.
+#
+
+source [find cpu/arc/em.tcl]
+
+set _CHIPNAME arc-em
+set _TARGETNAME $_CHIPNAME.cpu
+
+# EM SK IDENTITY is 0x200444b1
+# EM SK v2 IDENTITY is 0x200044b1
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -expected-id 0x200444b1 \
+  -expected-id 0x200044b1
+
+set _coreid 0
+set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
+
+target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME \
+  -coreid 0 -dbgbase $_dbgbase -endian little
+
+# There is no SRST, so do a software reset
+$_TARGETNAME configure -event reset-assert "arc_em_reset $_TARGETNAME"
+
+arc_em_init_regs
+
+# vim:ft=tcl
diff --git a/tcl/target/stellaris.cfg b/tcl/target/stellaris.cfg
index 7fffd2a..3cab4d1 100644
--- a/tcl/target/stellaris.cfg
+++ b/tcl/target/stellaris.cfg
@@ -68,7 +68,7 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 # NOTE: this may be increased by a reset-init handler, after it
 # configures and enables the PLL.  Or you might need to decrease
 # this, if you're using a slower clock.
-adapter_khz 500
+adapter speed 500
 
 source [find mem_helper.tcl]
 
@@ -132,7 +132,7 @@ proc reset_peripherals {family} {
 }
 
 $_TARGETNAME configure -event reset-start {
-	adapter_khz 500
+	adapter speed 500
 
 	#
 	# When nRST is asserted on most Stellaris devices, it clears some of
@@ -164,7 +164,7 @@ $_TARGETNAME configure -event reset-start {
 	} else {
 		if {![using_hla]} {
 		   # Tempest and Firestorm default to using NVIC VECTRESET
-		   # peripherals will need reseting manually, see proc reset_peripherals
+		   # peripherals will need resetting manually, see proc reset_peripherals
 		   cortex_m reset_config vectreset
 		}
 		# reset peripherals, based on code in
diff --git a/tcl/target/stm32f0x.cfg b/tcl/target/stm32f0x.cfg
index baac9b6..b20d036 100644
--- a/tcl/target/stm32f0x.cfg
+++ b/tcl/target/stm32f0x.cfg
@@ -52,9 +52,9 @@ set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
 
 # adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
+adapter speed 1000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 
 reset_config srst_nogate
 
@@ -66,7 +66,7 @@ if {![using_hla]} {
 
 proc stm32f0x_default_reset_start {} {
 	# Reset clock is HSI (8 MHz)
-	adapter_khz 1000
+	adapter speed 1000
 }
 
 proc stm32f0x_default_examine_end {} {
@@ -86,7 +86,7 @@ proc stm32f0x_default_reset_init {} {
 	mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
 
 	# Boost JTAG frequency
-	adapter_khz 8000
+	adapter speed 8000
 }
 
 # Default hooks
diff --git a/tcl/target/stm32f1x.cfg b/tcl/target/stm32f1x.cfg
index 471878d..3e85fb2 100644
--- a/tcl/target/stm32f1x.cfg
+++ b/tcl/target/stm32f1x.cfg
@@ -60,9 +60,9 @@ set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
 
 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
+adapter speed 1000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
diff --git a/tcl/target/stm32f2x.cfg b/tcl/target/stm32f2x.cfg
index 1e8b94a..d790feb 100644
--- a/tcl/target/stm32f2x.cfg
+++ b/tcl/target/stm32f2x.cfg
@@ -28,9 +28,9 @@ if { [info exists WORKAREASIZE] } {
 # bit more to be on the safe side. Perhaps superstition, but if are
 # running off a crystal, we can run closer to the limit. Note
 # that there can be a pretty wide band where things are more or less stable.
-adapter_khz 1000
+adapter speed 1000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg
index 86e9f59..e3f1a34 100644
--- a/tcl/target/stm32f3x.cfg
+++ b/tcl/target/stm32f3x.cfg
@@ -28,9 +28,9 @@ if { [info exists WORKAREASIZE] } {
 # bit more to be on the safe side. Perhaps superstition, but if are
 # running off a crystal, we can run closer to the limit. Note
 # that there can be a pretty wide band where things are more or less stable.
-adapter_khz 1000
+adapter speed 1000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
@@ -73,7 +73,7 @@ if {![using_hla]} {
 
 proc stm32f3x_default_reset_start {} {
 	# Reset clock is HSI (8 MHz)
-	adapter_khz 1000
+	adapter speed 1000
 }
 
 proc stm32f3x_default_examine_end {} {
@@ -93,7 +93,7 @@ proc stm32f3x_default_reset_init {} {
 	mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
 
 	# Boost JTAG frequency
-	adapter_khz 8000
+	adapter speed 8000
 }
 
 # Default hooks
diff --git a/tcl/target/stm32f4x.cfg b/tcl/target/stm32f4x.cfg
index 09ce14a..b95e783 100644
--- a/tcl/target/stm32f4x.cfg
+++ b/tcl/target/stm32f4x.cfg
@@ -58,9 +58,9 @@ flash bank $_CHIPNAME.otp stm32f2x 0x1fff7800 0 0 0 $_TARGETNAME
 # bit more to be on the safe side. Perhaps superstition, but if are
 # running off a crystal, we can run closer to the limit. Note
 # that there can be a pretty wide band where things are more or less stable.
-adapter_khz 2000
+adapter speed 2000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
@@ -100,10 +100,10 @@ $_TARGETNAME configure -event reset-init {
 	mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
 
 	# Boost JTAG frequency
-	adapter_khz 8000
+	adapter speed 8000
 }
 
 $_TARGETNAME configure -event reset-start {
 	# Reduce speed since CPU speed will slow down to 16MHz with the reset
-	adapter_khz 2000
+	adapter speed 2000
 }
diff --git a/tcl/target/stm32f7x.cfg b/tcl/target/stm32f7x.cfg
index ba1d12f..6ad4b65 100755..100644
--- a/tcl/target/stm32f7x.cfg
+++ b/tcl/target/stm32f7x.cfg
@@ -65,9 +65,9 @@ flash bank $_CHIPNAME.otp stm32f2x 0x1ff0f000 0 0 0 $_TARGETNAME
 flash bank $_CHIPNAME.itcm-flash.alias virtual 0x00200000 0 0 0 $_TARGETNAME $_FLASHNAME
 
 # adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
-adapter_khz 2000
+adapter speed 2000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
@@ -162,12 +162,11 @@ $_TARGETNAME configure -event reset-init {
 	if {[using_jtag]} {
 		[[target current] cget -dap] memaccess 16
 	} {
-		adapter_khz 8000
+		adapter speed 8000
 	}
 }
 
 $_TARGETNAME configure -event reset-start {
 	# Reduce speed since CPU speed will slow down to 16MHz with the reset
-	adapter_khz 2000
+	adapter speed 2000
 }
-
diff --git a/tcl/target/stm32g0x.cfg b/tcl/target/stm32g0x.cfg
new file mode 100644
index 0000000..50836ea
--- /dev/null
+++ b/tcl/target/stm32g0x.cfg
@@ -0,0 +1,88 @@
+# script for stm32g0x family
+
+#
+# stm32g0 devices support SWD transports only.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32g0x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# Smallest proposed target has 8kB ram, use 4kB by default to avoid surprises
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x1000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	# Section 37.5.5 - corresponds to Cortex-M0+
+	set _CPUTAPID 0x0bc11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
+
+# reasonable default
+adapter speed 2000
+
+adapter srst delay 100
+if {[using_jtag]} {
+	jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+	# if srst is not fitted use SYSRESETREQ to
+	# perform a soft reset
+	cortex_m reset_config sysresetreq
+}
+
+proc stm32g0x_default_reset_start {} {
+	# Reset clock is HSI16 (16 MHz)
+	adapter speed 2000
+}
+
+proc stm32g0x_default_examine_end {} {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+	mmw 0x40015804 0x00000006 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0x40015808 0x00001800 0
+}
+
+proc stm32g0x_default_reset_init {} {
+	# Increase clock to 64 Mhz
+	mmw 0x40022000 0x00000002 0x00000005	;# FLASH_ACR: Latency = 2
+	mww 0x4002100C 0x30000802				;# RCC_PLLCFGR = PLLR=/2, PLLN=8, PLLM=/1, PLLSRC=0x2
+	mmw 0x40021000 0x01000000 0x00000000	;# RCC_CR |= PLLON
+	mmw 0x40021008 0x00000002 0x00000005	;# RCC_CFGR: SW=PLLRCLK
+
+	# Boost JTAG frequency
+	adapter speed 4000
+}
+
+# Default hooks
+$_TARGETNAME configure -event examine-end { stm32g0x_default_examine_end }
+$_TARGETNAME configure -event reset-start { stm32g0x_default_reset_start }
+$_TARGETNAME configure -event reset-init { stm32g0x_default_reset_init }
diff --git a/tcl/target/stm32g4x.cfg b/tcl/target/stm32g4x.cfg
new file mode 100644
index 0000000..9f144a0
--- /dev/null
+++ b/tcl/target/stm32g4x.cfg
@@ -0,0 +1,103 @@
+# script for stm32g4x family
+
+#
+# stm32g4 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32g4x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# Smallest current target has 32kB ram, use 16kB by default to avoid surprises
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x4000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		# See STM Document RM0440
+		# Section 46.6.3 - corresponds to Cortex-M4 r0p1
+		set _CPUTAPID 0x4ba00477
+	} {
+		set _CPUTAPID 0x2ba01477
+	}
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+	jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
+
+if { [info exists QUADSPI] && $QUADSPI } {
+	set a [llength [flash list]]
+	set _QSPINAME $_CHIPNAME.qspi
+	flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
+}
+
+# reasonable default
+adapter speed 2000
+
+adapter srst delay 100
+if {[using_jtag]} {
+	jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+	# if srst is not fitted use SYSRESETREQ to
+	# perform a soft reset
+	cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event reset-init {
+	# CPU comes out of reset with HSION | HSIRDY.
+	# Use HSI 16 MHz clock, compliant even with VOS == 2.
+	# 1 WS compliant with VOS == 2 and 16 MHz.
+	mmw 0x40022000 0x00000001 0x0000000E	;# FLASH_ACR: Latency = 1
+	mmw 0x40021000 0x00000100 0x00000000	;# RCC_CR |= HSION
+	mmw 0x40021008 0x00000001 0x00000002	;# RCC_CFGR: SW=HSI16
+}
+
+$_TARGETNAME configure -event reset-start {
+	# Reset clock is HSI (16 MHz)
+	adapter speed 2000
+}
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0xE0042008 0x00001800 0
+}
+
+$_TARGETNAME configure -event trace-config {
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0042004 0x00000020 0
+}
diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg
index 0bfc43d..2d92eca 100644
--- a/tcl/target/stm32h7x.cfg
+++ b/tcl/target/stm32h7x.cfg
@@ -12,6 +12,39 @@ if { [info exists CHIPNAME] } {
    set _CHIPNAME stm32h7x
 }
 
+if { [info exists DUAL_BANK] } {
+	set $_CHIPNAME.DUAL_BANK $DUAL_BANK
+	unset DUAL_BANK
+} else {
+	set $_CHIPNAME.DUAL_BANK 0
+}
+
+if { [info exists DUAL_CORE] } {
+	set $_CHIPNAME.DUAL_CORE $DUAL_CORE
+	unset DUAL_CORE
+} else {
+	set $_CHIPNAME.DUAL_CORE 0
+}
+
+# Issue a warning when hla is used, and fallback to single core configuration
+if { [set $_CHIPNAME.DUAL_CORE] && [using_hla] } {
+	echo "Warning : hla does not support multicore debugging"
+	set $_CHIPNAME.DUAL_CORE 0
+}
+
+if { [info exists USE_CTI] } {
+	set $_CHIPNAME.USE_CTI $USE_CTI
+	unset USE_CTI
+} else {
+	set $_CHIPNAME.USE_CTI 0
+}
+
+# Issue a warning when DUAL_CORE=0 and USE_CTI=1, and fallback to USE_CTI=0
+if { ![set $_CHIPNAME.DUAL_CORE] && [set $_CHIPNAME.USE_CTI] } {
+	echo "Warning : could not use CTI with a single core device, CTI is disabled"
+	set $_CHIPNAME.USE_CTI 0
+}
+
 set _ENDIAN little
 
 # Work-area is a space in RAM used for flash programming
@@ -40,18 +73,41 @@ if {[using_jtag]} {
  swj_newdap $_CHIPNAME bs -irlen 5
 }
 
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+if {![using_hla]} {
+	# STM32H7 provides an APB-AP at access port 2, which allows the access to
+	# the debug and trace features on the system APB System Debug Bus (APB-D).
+	target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
+}
+
+target create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0
+
+$_CHIPNAME.cpu0 configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+flash bank $_CHIPNAME.bank1.cpu0 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu0
+
+if {[set $_CHIPNAME.DUAL_BANK]} {
+	flash bank $_CHIPNAME.bank2.cpu0 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu0
+}
+
+if {[set $_CHIPNAME.DUAL_CORE]} {
+	target create $_CHIPNAME.cpu1 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 3
 
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+	$_CHIPNAME.cpu1 configure -work-area-phys 0x38000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+	flash bank $_CHIPNAME.bank1.cpu1 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu1
+
+	if {[set $_CHIPNAME.DUAL_BANK]} {
+		flash bank $_CHIPNAME.bank2.cpu1 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu1
+	}
+}
 
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME stm32h7x 0x08000000 0 0 0 $_TARGETNAME
+# Make sure that cpu0 is selected
+targets $_CHIPNAME.cpu0
 
 # Clock after reset is HSI at 64 MHz, no need of PLL
-adapter_khz 1800
+adapter speed 1800
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
@@ -72,7 +128,11 @@ reset_config srst_only srst_nogate
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
-   cortex_m reset_config sysresetreq
+	$_CHIPNAME.cpu0 cortex_m reset_config sysresetreq
+
+	if {[set $_CHIPNAME.DUAL_CORE]} {
+		$_CHIPNAME.cpu1 cortex_m reset_config sysresetreq
+	}
 
    # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
    # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
@@ -83,31 +143,133 @@ if {![using_hla]} {
    $_CHIPNAME.dap apcsw 0x08000000 0x08000000
 }
 
-$_TARGETNAME configure -event examine-end {
+$_CHIPNAME.cpu0 configure -event examine-end {
 	# Enable D3 and D1 DBG clocks
 	# DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN
-	mmw 0x5C001004 0x00600000 0
+	stm32h7x_dbgmcu_mmw 0x004 0x00600000 0
 
 	# Enable debug during low power modes (uses more power)
-	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3 & D1 Domains
-	mmw 0x5C001004 0x00000187 0
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3, D2 & D1 Domains
+	stm32h7x_dbgmcu_mmw 0x004 0x000001BF 0
 
 	# Stop watchdog counters during halt
 	# DBGMCU_APB3FZ1 |= WWDG1
-	mmw 0x5C001034 0x00000040 0
-	# DBGMCU_APB4FZ1 |= WDGLSD1
-	mmw 0x5C001054 0x00040000 0
+	stm32h7x_dbgmcu_mmw 0x034 0x00000040 0
+	# DBGMCU_APB1LFZ1 |= WWDG2
+	stm32h7x_dbgmcu_mmw 0x03C 0x00000800 0
+	# DBGMCU_APB4FZ1 |= WDGLSD1 | WDGLSD2
+	stm32h7x_dbgmcu_mmw 0x054 0x000C0000 0
 }
 
-$_TARGETNAME configure -event trace-config {
+$_CHIPNAME.cpu0 configure -event trace-config {
 	# Set TRACECLKEN; TRACE_MODE is set to async; when using sync
 	# change this value accordingly to configure trace pins
 	# assignment
-	mmw 0x5C001004 0x00100000 0
+	stm32h7x_dbgmcu_mmw 0x004 0x00100000 0
 }
 
-$_TARGETNAME configure -event reset-init {
+$_CHIPNAME.cpu0 configure -event reset-init {
 	# Clock after reset is HSI at 64 MHz, no need of PLL
-	adapter_khz 4000
+	adapter speed 4000
+}
+
+if {[set $_CHIPNAME.DUAL_CORE]} {
+	$_CHIPNAME.cpu1 configure -event examine-end {
+		# get _CHIPNAME from the current target
+		set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+		global $_CHIPNAME.USE_CTI
+
+		# Stop watchdog counters during halt
+		# DBGMCU_APB3FZ2 |= WWDG1
+		stm32h7x_dbgmcu_mmw 0x038 0x00000040 0
+		# DBGMCU_APB1LFZ2 |= WWDG2
+		stm32h7x_dbgmcu_mmw 0x040 0x00000800 0
+		# DBGMCU_APB4FZ2 |= WDGLSD1 | WDGLSD2
+		stm32h7x_dbgmcu_mmw 0x058 0x000C0000 0
+
+		if {[set $_CHIPNAME.USE_CTI]} {
+			stm32h7x_cti_start
+		}
+	}
+}
+
+# like mrw, but with target selection
+proc stm32h7x_mrw {used_target reg} {
+	set value ""
+	$used_target mem2array value 32 $reg 1
+	return $value(0)
+}
+
+# like mmw, but with target selection
+proc stm32h7x_mmw {used_target reg setbits clearbits} {
+	set old [stm32h7x_mrw $used_target $reg]
+	set new [expr ($old & ~$clearbits) | $setbits]
+	$used_target mww $reg $new
+}
+
+# mmw for dbgmcu component registers, it accepts the register offset from dbgmcu base
+# this procedure will use the mem_ap on AP2 whenever possible
+proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} {
+	# use $_CHIPNAME.ap2 if possible, and use the proper dbgmcu base address
+	if {![using_hla]} {
+		# get _CHIPNAME from the current target
+		set _CHIPNAME [regsub ".(cpu|ap)\\d*$" [target current] ""]
+		set used_target $_CHIPNAME.ap2
+		set reg_addr [expr 0xE00E1000 + $reg_offset]
+	} {
+		set used_target [target current]
+		set reg_addr [expr 0x5C001000 + $reg_offset]
+	}
+
+	stm32h7x_mmw $used_target $reg_addr $setbits $clearbits
 }
 
+if {[set $_CHIPNAME.USE_CTI]} {
+	# create CTI instances for both cores
+	cti create $_CHIPNAME.cti0 -dap $_CHIPNAME.dap -ap-num 0 -ctibase 0xE0043000
+	cti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 3 -ctibase 0xE0043000
+
+	$_CHIPNAME.cpu0 configure -event halted { stm32h7x_cti_prepare_restart_all }
+	$_CHIPNAME.cpu1 configure -event halted { stm32h7x_cti_prepare_restart_all }
+
+	$_CHIPNAME.cpu0 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
+	$_CHIPNAME.cpu1 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
+
+	proc stm32h7x_cti_start {} {
+		# get _CHIPNAME from the current target
+		set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+
+		# Configure Cores' CTIs to halt each other
+		# TRIGIN0 (DBGTRIGGER) and TRIGOUT0 (EDBGRQ) at CTM_CHANNEL_0
+		$_CHIPNAME.cti0 write INEN0 0x1
+		$_CHIPNAME.cti0 write OUTEN0 0x1
+		$_CHIPNAME.cti1 write INEN0 0x1
+		$_CHIPNAME.cti1 write OUTEN0 0x1
+
+		# enable CTIs
+		$_CHIPNAME.cti0 enable on
+		$_CHIPNAME.cti1 enable on
+	}
+
+	proc stm32h7x_cti_stop {} {
+		# get _CHIPNAME from the current target
+		set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+
+		$_CHIPNAME.cti0 enable off
+		$_CHIPNAME.cti1 enable off
+	}
+
+	proc stm32h7x_cti_prepare_restart_all {} {
+		stm32h7x_cti_prepare_restart cti0
+		stm32h7x_cti_prepare_restart cti1
+	}
+
+	proc stm32h7x_cti_prepare_restart {cti} {
+		# get _CHIPNAME from the current target
+		set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+
+		# Acknowlodge EDBGRQ at TRIGOUT0
+		$_CHIPNAME.$cti write INACK 0x01
+		$_CHIPNAME.$cti write INACK 0x00
+	}
+}
diff --git a/tcl/target/stm32h7x_dual_bank.cfg b/tcl/target/stm32h7x_dual_bank.cfg
index 7e342f9..a88d70d 100644
--- a/tcl/target/stm32h7x_dual_bank.cfg
+++ b/tcl/target/stm32h7x_dual_bank.cfg
@@ -1,7 +1,6 @@
 # script for stm32h7x family (dual flash bank)
-source [find target/stm32h7x.cfg]
 
 # STM32H7xxxI 2Mo have a dual bank flash.
-# Add the second flash bank.
-set _FLASHNAME $_CHIPNAME.flash1
-flash bank $_FLASHNAME stm32h7x 0x08100000 0 0 0 $_TARGETNAME
+set DUAL_BANK 1
+
+source [find target/stm32h7x.cfg]
diff --git a/tcl/target/stm32l0.cfg b/tcl/target/stm32l0.cfg
index ec5d546..7653d13 100644
--- a/tcl/target/stm32l0.cfg
+++ b/tcl/target/stm32l0.cfg
@@ -24,9 +24,9 @@ if { [info exists WORKAREASIZE] } {
 
 # JTAG speed should be <= F_CPU/6.
 # F_CPU after reset is ~2MHz, so use F_JTAG max = 333kHz
-adapter_khz 300
+adapter speed 300
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 
 if { [info exists CPUTAPID] } {
     set _CPUTAPID $CPUTAPID
@@ -61,13 +61,16 @@ proc stm32l0_enable_HSI16 {} {
 	echo "STM32L0: Enabling HSI16"
 
 	# Set HSI16ON in RCC_CR (leave MSI enabled)
-	mww 0x40021000 0x00000101
+    mmw 0x40021000 0x00000101 0
 
 	# Set HSI16 as SYSCLK (RCC_CFGR)
-	mww 0x4002100c 0x00000001
+	mmw 0x4002100c 0x00000001 0
+
+	# Wait until System clock switches to HSI16
+	while { ([ mrw 0x4002100c ] & 0x0c) != 0x04 } { }
 
 	# Increase speed
-	adapter_khz 2500
+	adapter speed 2500
 }
 
 $_TARGETNAME configure -event reset-init {
@@ -75,7 +78,7 @@ $_TARGETNAME configure -event reset-init {
 }
 
 $_TARGETNAME configure -event reset-start {
-	adapter_khz 300
+	adapter speed 300
 }
 
 $_TARGETNAME configure -event examine-end {
diff --git a/tcl/target/stm32l1.cfg b/tcl/target/stm32l1.cfg
index 054fa9b..a81d7c7 100644
--- a/tcl/target/stm32l1.cfg
+++ b/tcl/target/stm32l1.cfg
@@ -23,9 +23,9 @@ if { [info exists WORKAREASIZE] } {
 
 # JTAG speed should be <= F_CPU/6.
 # F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz
-adapter_khz 300
+adapter speed 300
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
@@ -73,13 +73,13 @@ proc stm32l_enable_HSI {} {
 	echo "STM32L: Enabling HSI"
 
 	# Set HSION in RCC_CR
-	mww 0x40023800 0x00000101
+	mmw 0x40023800 0x00000101 0
 
 	# Set HSI as SYSCLK
-	mww 0x40023808 0x00000001
+	mmw 0x40023808 0x00000001 0
 
 	# Increase JTAG speed
-	adapter_khz 2000
+	adapter speed 2000
 }
 
 $_TARGETNAME configure -event reset-init {
@@ -87,7 +87,7 @@ $_TARGETNAME configure -event reset-init {
 }
 
 $_TARGETNAME configure -event reset-start {
-	adapter_khz 300
+	adapter speed 300
 }
 
 $_TARGETNAME configure -event examine-end {
diff --git a/tcl/target/stm32l4x.cfg b/tcl/target/stm32l4x.cfg
index 496b47a..46e6f7e 100644
--- a/tcl/target/stm32l4x.cfg
+++ b/tcl/target/stm32l4x.cfg
@@ -56,9 +56,9 @@ flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
 #
 # Note that there is a pretty wide band where things are
 # more or less stable, see http://openocd.zylin.com/#/c/3366/
-adapter_khz 500
+adapter speed 500
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
@@ -78,12 +78,12 @@ $_TARGETNAME configure -event reset-init {
 	mww 0x40022000 0x00000103   ;# FLASH_ACR = PRFTBE | 3(Latency)
 	mww 0x40021000 0x00000099   ;# RCC_CR = MSI_ON | MSIRGSEL | MSI Range 9
 	# Boost JTAG frequency
-	adapter_khz 4000
+	adapter speed 4000
 }
 
 $_TARGETNAME configure -event reset-start {
 	# Reset clock is MSI (4 MHz)
-	adapter_khz 500
+	adapter speed 500
 }
 
 $_TARGETNAME configure -event examine-end {
diff --git a/tcl/target/stm32mp15x.cfg b/tcl/target/stm32mp15x.cfg
new file mode 100644
index 0000000..f2ba94e
--- /dev/null
+++ b/tcl/target/stm32mp15x.cfg
@@ -0,0 +1,121 @@
+# STMicroelectronics STM32MP15x (Single/Dual Cortex-A7 plus Cortex-M4)
+# http://www.st.com/stm32mp1
+
+# HLA does not support multi-cores nor custom CSW nor AP other than 0
+if { [using_hla] } {
+	echo "ERROR: HLA transport cannot work with this target."
+	echo "ERROR: To use STLink switch to DAP mode, as in \"board/stm32mp15x_dk2.cfg\"."
+	shutdown
+}
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32mp15x
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		set _CPUTAPID 0x6ba00477
+	} else {
+		set _CPUTAPID 0x6ba02477
+	}
+}
+
+# Chip Level TAP Controller, only in jtag mode
+if { [info exists CLCTAPID] } {
+	set _CLCTAPID $CLCTAPID
+} else {
+	set _CLCTAPID 0x06500041
+}
+
+swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4
+if { [using_jtag] } {
+	jtag newtap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
+}
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack
+
+# FIXME: Cortex-M code requires target accessible during reset, but this is not possible in STM32MP1
+# so defer-examine it until the reset framework get merged
+# NOTE: keep ap-num and dbgbase to speed-up examine after reset
+# NOTE: do not change the order of target create
+target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
+target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
+target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
+target create $_CHIPNAME.cpu0 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000
+target create $_CHIPNAME.cpu1 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 1 -dbgbase 0xE00D2000
+target create $_CHIPNAME.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine
+
+targets $_CHIPNAME.cpu0
+
+target smp $_CHIPNAME.cpu0 $_CHIPNAME.cpu1
+$_CHIPNAME.cpu0 cortex_a maskisr on
+$_CHIPNAME.cpu1 cortex_a maskisr on
+$_CHIPNAME.cpu0 cortex_a dacrfixup on
+$_CHIPNAME.cpu1 cortex_a dacrfixup on
+
+cti create $_CHIPNAME.cti.sys  -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0xE0094000
+cti create $_CHIPNAME.cti.cpu0 -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0xE00D8000
+cti create $_CHIPNAME.cti.cpu1 -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0xE00D9000
+cti create $_CHIPNAME.cti.cm4  -dap $_CHIPNAME.dap -ap-num 2 -ctibase 0xE0043000
+
+# interface does not work while srst is asserted
+# this is target specific, valid for every board
+# Errata "2.3.5 Incorrect reset of glitch-free kernel clock switch" requires
+# srst to force VDDCORE power cycle or pull srst_core. Both cases reset the
+# debug unit, behavior equivalent to "srst_pulls_trst"
+reset_config srst_gates_jtag srst_pulls_trst
+
+adapter speed 5000
+adapter srst pulse_width 200
+# bootrom has an internal timeout of 1 second for detecting the boot flash.
+# wait at least 1 second to guarantee we are out of bootrom
+adapter srst delay 1100
+
+add_help_text axi_secure "Set secure mode for following AXI accesses"
+proc axi_secure {} {
+	$::_CHIPNAME.dap apsel 0
+	$::_CHIPNAME.dap apcsw 0x10006000
+}
+
+add_help_text axi_nsecure "Set non-secure mode for following AXI accesses"
+proc axi_nsecure {} {
+	$::_CHIPNAME.dap apsel 0
+	$::_CHIPNAME.dap apcsw 0x30006000
+}
+
+axi_secure
+
+proc dbgmcu_enable_debug {} {
+	# set debug enable bits in DBGMCU_CR to get ap2 and cm4 visible
+	catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000007}
+}
+
+proc toggle_cpu0_dbg_claim0 {} {
+	# toggle CPU0 DBG_CLAIM[0]
+	$::_CHIPNAME.ap1 mww 0xe00d0fa0 1
+	$::_CHIPNAME.ap1 mww 0xe00d0fa4 1
+}
+
+proc detect_cpu1 {} {
+	$::_CHIPNAME.ap1 mem2array cpu1_prsr 32 0xE00D2314 1
+	set dual_core [expr $cpu1_prsr(0) & 1]
+	if {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine}
+}
+
+# FIXME: most of handler below will be removed once reset framework get merged
+$_CHIPNAME.ap1  configure -event reset-deassert-pre  {adapter deassert srst deassert trst;dap init;catch {$::_CHIPNAME.dap apid 1}}
+$_CHIPNAME.ap2  configure -event reset-deassert-pre  {dbgmcu_enable_debug}
+$_CHIPNAME.cpu0 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu0 arp_examine}
+$_CHIPNAME.cpu1 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu1 arp_examine allow-defer}
+$_CHIPNAME.cpu0 configure -event reset-deassert-post {toggle_cpu0_dbg_claim0}
+$_CHIPNAME.cm4  configure -event reset-deassert-post {$::_CHIPNAME.cm4 arp_examine;if {[$::_CHIPNAME.ap2 curstate] == "halted"} {$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_halt}}
+$_CHIPNAME.ap1  configure -event examine-start       {dap init}
+$_CHIPNAME.ap2  configure -event examine-start       {dbgmcu_enable_debug}
+$_CHIPNAME.cpu0 configure -event examine-end         {detect_cpu1}
+$_CHIPNAME.ap2  configure -event examine-end         {$::_CHIPNAME.cm4 arp_examine}
diff --git a/tcl/target/stm32wbx.cfg b/tcl/target/stm32wbx.cfg
new file mode 100644
index 0000000..90f53bb
--- /dev/null
+++ b/tcl/target/stm32wbx.cfg
@@ -0,0 +1,103 @@
+# script for stm32wbx family
+
+#
+# stm32wb devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32wbx
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x10000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x6ba00477
+   } else {
+      # SWD IDCODE (single drop, arm)
+      set _CPUTAPID 0x6ba02477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
+
+# Common knowledges tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://openocd.zylin.com/#/c/3366/
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event reset-init {
+    # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
+    # Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
+    # 2 WS compliant with VOS=Range1 and 24 MHz.
+    mmw 0x58004000 0x00000102 0  ;# FLASH_ACR |= PRFTBE | 2(Latency)
+    mmw 0x58000000 0x00000091 0  ;# RCC_CR = MSI_ON | MSI Range 24 MHz
+    # Boost JTAG frequency
+    adapter speed 4000
+}
+
+$_TARGETNAME configure -event reset-start {
+    # Reset clock is MSI (4 MHz)
+    adapter speed 500
+}
+
+$_TARGETNAME configure -event examine-end {
+    # Enable debug during low power modes (uses more power)
+    # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+    mmw 0xE0042004 0x00000007 0
+
+    # Stop watchdog counters during halt
+    # DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
+    mmw 0xE004203C 0x00001800 0
+}
+
+$_TARGETNAME configure -event trace-config {
+    # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+    # change this value accordingly to configure trace pins
+    # assignment
+    mmw 0xE0042004 0x00000020 0
+}
diff --git a/tcl/target/stm32wlx.cfg b/tcl/target/stm32wlx.cfg
new file mode 100644
index 0000000..98c9a7e
--- /dev/null
+++ b/tcl/target/stm32wlx.cfg
@@ -0,0 +1,100 @@
+# script for stm32wlx family
+
+#
+# stm32wl devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32wlx
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 20kB
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x5000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		set _CPUTAPID 0x6ba00477
+	} else {
+		# SWD IDCODE (single drop, arm)
+		set _CPUTAPID 0x6ba02477
+	}
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+	swj_newdap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
+
+# Common knowledges tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://openocd.zylin.com/#/c/3366/
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+	jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+	# if srst is not fitted use SYSRESETREQ to
+	# perform a soft reset
+	cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event reset-init {
+	# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
+	# Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
+	# 2 WS compliant with VOS=Range1 and 24 MHz.
+	mmw 0x58004000 0x00000102 0  ;# FLASH_ACR |= PRFTEN | 2(Latency)
+	mmw 0x58000000 0x00000091 0  ;# RCC_CR = MSI_ON | MSI Range 24 MHz
+	# Boost JTAG frequency
+	adapter speed 4000
+}
+
+$_TARGETNAME configure -event reset-start {
+	# Reset clock is MSI (4 MHz)
+	adapter speed 500
+}
+
+$_TARGETNAME configure -event examine-end {
+	# Enable debug during low power modes (uses more power)
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0xE004203C 0x00001800 0
+}
+
+$_TARGETNAME configure -event trace-config {
+	# nothing to do
+}
diff --git a/tcl/target/stm8l.cfg b/tcl/target/stm8l.cfg
index 5cc99e1..a06c4cb 100644
--- a/tcl/target/stm8l.cfg
+++ b/tcl/target/stm8l.cfg
@@ -4,7 +4,7 @@
 # stm8 devices support SWIM transports only.
 #
 
-transport select stlink_swim
+transport select swim
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
@@ -62,7 +62,7 @@ if { [info exists BLOCKSIZE] } {
    set _BLOCKSIZE 0x80
 }
 
-hla newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0
+swim newtap $_CHIPNAME cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
 
@@ -78,8 +78,10 @@ $_TARGETNAME configure -optionstart $_OPTIONSTART -optionend $_OPTIONEND -blocks
 # Set stm8l type
 $_TARGETNAME configure -enable_stm8l
 
-# The khz rate does not apply here, only slow <0> and fast <1>
-adapter_khz 1
+# Set high speed
+adapter speed 800
+# Set low speed
+#adapter speed 363
 
 reset_config srst_only
 
diff --git a/tcl/target/stm8s.cfg b/tcl/target/stm8s.cfg
index d55e61b..2dae655 100644
--- a/tcl/target/stm8s.cfg
+++ b/tcl/target/stm8s.cfg
@@ -4,7 +4,7 @@
 # stm8 devices support SWIM transports only.
 #
 
-transport select stlink_swim
+transport select swim
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
@@ -62,7 +62,7 @@ if { [info exists BLOCKSIZE] } {
    set _BLOCKSIZE 0x80
 }
 
-hla newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0
+swim newtap $_CHIPNAME cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
 
@@ -75,8 +75,10 @@ $_TARGETNAME configure -optionstart $_OPTIONSTART -optionend $_OPTIONEND -blocks
 # Uncomment this line to enable interrupts while instruction step
 #$_TARGETNAME configure -enable_step_irq
 
-# The khz rate does not apply here, only slow <0> and fast <1>
-adapter_khz 1
+# Set high speed
+adapter speed 800
+# Set low speed
+#adapter speed 363
 
 reset_config srst_only
 
diff --git a/tcl/target/stm8s103.cfg b/tcl/target/stm8s103.cfg
new file mode 100644
index 0000000..714acf4
--- /dev/null
+++ b/tcl/target/stm8s103.cfg
@@ -0,0 +1,13 @@
+#config script for STM8S103
+
+set FLASHEND 0x9FFF
+set EEPROMEND 0x427F
+set OPTIONEND 0x480A
+set BLOCKSIZE 0x40
+
+proc stm8_reset_rop {} {
+   mwb 0x4800 0x00
+   reset halt
+}
+
+source [find target/stm8s.cfg]
diff --git a/tcl/target/str710.cfg b/tcl/target/str710.cfg
index d26a8b1..29faaaa 100644
--- a/tcl/target/str710.cfg
+++ b/tcl/target/str710.cfg
@@ -1,5 +1,5 @@
 #start slow, speed up after reset
-adapter_khz 10
+adapter speed 10
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
@@ -29,9 +29,9 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_C
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
 
-$_TARGETNAME configure -event reset-start { adapter_khz 10 }
+$_TARGETNAME configure -event reset-start { adapter speed 10 }
 $_TARGETNAME configure -event reset-init {
-	adapter_khz 6000
+	adapter speed 6000
 
 # Because the hardware cannot be interrogated for the protection state
 # of sectors, initialize all the sectors to be unprotected. The initial
diff --git a/tcl/target/str730.cfg b/tcl/target/str730.cfg
index 48d3134..e9e2f26 100644
--- a/tcl/target/str730.cfg
+++ b/tcl/target/str730.cfg
@@ -1,6 +1,6 @@
 #STR730 CPU
 
-adapter_khz 3000
+adapter speed 3000
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
@@ -27,15 +27,15 @@ reset_config trst_and_srst srst_pulls_trst
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
 
 #jtag nTRST and nSRST delay
-adapter_nsrst_delay 500
+adapter srst delay 500
 jtag_ntrst_delay 500
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm7tdmi -endian little -chain-position 0
 
-$_TARGETNAME configure -event reset-start { adapter_khz 10 }
+$_TARGETNAME configure -event reset-start { adapter speed 10 }
 $_TARGETNAME configure -event reset-init {
-	adapter_khz 3000
+	adapter speed 3000
 
 # Because the hardware cannot be interrogated for the protection state
 # of sectors, initialize all the sectors to be unprotected. The initial
@@ -51,4 +51,3 @@ $_TARGETNAME configure -work-area-phys 0xA0000000 -work-area-size 0x4000 -work-a
 #flash bank <driver> <base> <size> <chip_width> <bus_width>
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME str7x 0x80000000 0x00040000 0 0 $_TARGETNAME STR73x
-
diff --git a/tcl/target/str750.cfg b/tcl/target/str750.cfg
index ef6e795..335d5ad 100644
--- a/tcl/target/str750.cfg
+++ b/tcl/target/str750.cfg
@@ -19,7 +19,7 @@ if { [info exists CPUTAPID] } {
 }
 
 # jtag speed
-adapter_khz 10
+adapter speed 10
 
 #use combined on interfaces or targets that can't set TRST/SRST separately
 reset_config trst_and_srst srst_pulls_trst
@@ -29,15 +29,15 @@ reset_config trst_and_srst srst_pulls_trst
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
 
 #jtag nTRST and nSRST delay
-adapter_nsrst_delay 500
+adapter srst delay 500
 jtag_ntrst_delay 500
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm7tdmi -endian little -chain-position 0
 
-$_TARGETNAME configure -event reset-start { adapter_khz 10 }
+$_TARGETNAME configure -event reset-start { adapter speed 10 }
 $_TARGETNAME configure -event reset-init {
-	adapter_khz 3000
+	adapter speed 3000
 
 	init_smi
 # Because the hardware cannot be interrogated for the protection state
diff --git a/tcl/target/str912.cfg b/tcl/target/str912.cfg
index 36c0b2a..7426276 100644
--- a/tcl/target/str912.cfg
+++ b/tcl/target/str912.cfg
@@ -13,9 +13,9 @@ if { [info exists ENDIAN] } {
 }
 
 # jtag speed. We need to stick to 16kHz until we've finished reset.
-adapter_khz 16
+adapter speed 16
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 
 #use combined on interfaces or targets that can't set TRST/SRST separately
@@ -48,11 +48,11 @@ jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BST
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
 
-$_TARGETNAME configure -event reset-start { adapter_khz 16 }
+$_TARGETNAME configure -event reset-start { adapter speed 16 }
 
 $_TARGETNAME configure -event reset-init {
 	# We can increase speed now that we know the target is halted.
-	#adapter_khz 3000
+	#adapter speed 3000
 
 	# -- Enable 96K RAM
 	# PFQBC enabled / DTCM & AHB wait-states disabled
diff --git a/tcl/target/swm050.cfg b/tcl/target/swm050.cfg
index a819f9c..e6f2ecb 100644
--- a/tcl/target/swm050.cfg
+++ b/tcl/target/swm050.cfg
@@ -1,5 +1,7 @@
 # Synwit SWM050
 
+source [find target/swj-dp.tcl]
+
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
 } else {
@@ -16,10 +18,10 @@ if { [info exists WORKAREASIZE] } {
 if { [info exists CPUTAPID] } {
 	set _CPUTAPID $CPUTAPID
 } else {
-	set _CPUTAPID 0x410CC200
+	set _CPUTAPID 0x0bb11477
 }
 
-swd newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
@@ -27,6 +29,7 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME swm050 0x0 0x2000 0 0 $_TARGETNAME
 
+adapter speed 1000
 
 $_TARGETNAME configure -event reset-init {
 	# Stop the watchdog, just to be safe
diff --git a/tcl/target/ti-cjtag.cfg b/tcl/target/ti-cjtag.cfg
index 7114b2a..7114b2a 100755..100644
--- a/tcl/target/ti-cjtag.cfg
+++ b/tcl/target/ti-cjtag.cfg
diff --git a/tcl/target/ti_calypso.cfg b/tcl/target/ti_calypso.cfg
index 9d3b293..52a84fb 100644
--- a/tcl/target/ti_calypso.cfg
+++ b/tcl/target/ti_calypso.cfg
@@ -32,7 +32,7 @@ if { [info exists WORKAREASIZE] } {
 	set _WORKAREASIZE 0x10000
 }
 
-adapter_khz 1000
+adapter speed 1000
 
 reset_config trst_and_srst
 
diff --git a/tcl/target/ti_cc26x0.cfg b/tcl/target/ti_cc26x0.cfg
index 7efecb6..f95d7b2 100644
--- a/tcl/target/ti_cc26x0.cfg
+++ b/tcl/target/ti_cc26x0.cfg
@@ -52,5 +52,4 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
 
-reset_config srst_only
-adapter_nsrst_delay 100
+cortex_m reset_config vectreset
diff --git a/tcl/target/ti_cc3220sf.cfg b/tcl/target/ti_cc3220sf.cfg
index f7d9bfe..74269aa 100644
--- a/tcl/target/ti_cc3220sf.cfg
+++ b/tcl/target/ti_cc3220sf.cfg
@@ -10,3 +10,31 @@ source [find target/ti_cc32xx.cfg]
 
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
+
+#
+# On CC32xx family of devices, sysreqreset is disabled, and vectreset is
+# blocked by the boot loader (stops in a while(1) statement). srst reset can
+# leave the target in a state that prevents debug. The following uses the
+# soft_reset_halt command to reset and halt the target. Then the PC and stack
+# are initialized from internal flash. This allows for a more reliable reset,
+# but with two caveats: it only works for the SF variant that has internal
+# flash, and it only resets the CPU and not any peripherals.
+#
+
+proc ocd_process_reset_inner { MODE } {
+
+	soft_reset_halt
+
+	# Initialize MSP, PSP, and PC from vector table at flash 0x01000800
+	mem2array boot 32 0x01000800 2
+
+	reg msp $boot(0)
+	reg psp $boot(0)
+	reg pc $boot(1)
+
+	if { 0 == [string compare $MODE run ] } {
+		resume
+	}
+
+	cc32xx.cpu invoke-event reset-end
+}
diff --git a/tcl/target/ti_cc32xx.cfg b/tcl/target/ti_cc32xx.cfg
index bc3038d..e3e3ebc 100644
--- a/tcl/target/ti_cc32xx.cfg
+++ b/tcl/target/ti_cc32xx.cfg
@@ -59,6 +59,3 @@ if { [info exists WORKAREASIZE] } {
 }
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-reset_config srst_only
-adapter_nsrst_delay 1100
diff --git a/tcl/target/ti_dm355.cfg b/tcl/target/ti_dm355.cfg
index 4f8f523..91c0087 100644
--- a/tcl/target/ti_dm355.cfg
+++ b/tcl/target/ti_dm355.cfg
@@ -98,8 +98,8 @@ $_TARGETNAME configure \
 # be absolutely certain the JTAG clock will work with the worst-case
 # CLKIN = 24 MHz (best case: 36 MHz) even when no bootloader turns
 # on the PLL and starts using it.  OK to speed up after clock setup.
-adapter_khz 1500
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
 
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable
diff --git a/tcl/target/ti_dm365.cfg b/tcl/target/ti_dm365.cfg
index 0db83db..8b52746 100644
--- a/tcl/target/ti_dm365.cfg
+++ b/tcl/target/ti_dm365.cfg
@@ -90,8 +90,8 @@ $_TARGETNAME configure \
 # be absolutely certain the JTAG clock will work with the worst-case
 # CLKIN = 19.2 MHz (best case: 36 MHz) even when no bootloader turns
 # on the PLL and starts using it.  OK to speed up after clock setup.
-adapter_khz 1500
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
 
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable
diff --git a/tcl/target/ti_dm6446.cfg b/tcl/target/ti_dm6446.cfg
index fa1e6e9..ccc650a 100644
--- a/tcl/target/ti_dm6446.cfg
+++ b/tcl/target/ti_dm6446.cfg
@@ -70,8 +70,8 @@ $_TARGETNAME configure -work-area-phys 0x0000a000 -work-area-size 0x2000
 # be absolutely certain the JTAG clock will work with the worst-case
 # CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
 # on the PLL and starts using it.  OK to speed up after clock setup.
-adapter_khz 1500
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
 
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable
diff --git a/tcl/target/ti_msp432.cfg b/tcl/target/ti_msp432.cfg
index 3407f75..77f81da 100644
--- a/tcl/target/ti_msp432.cfg
+++ b/tcl/target/ti_msp432.cfg
@@ -42,10 +42,10 @@ if { [info exists WORKAREASIZE] } {
 	set _WORKAREASIZE 0x4000
 }
 
+
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
 
-reset_config srst_only
-adapter_nsrst_delay 100
+cortex_m reset_config sysresetreq
diff --git a/tcl/target/ti_tms570.cfg b/tcl/target/ti_tms570.cfg
index ce3a176..d06ff97 100644
--- a/tcl/target/ti_tms570.cfg
+++ b/tcl/target/ti_tms570.cfg
@@ -1,4 +1,4 @@
-adapter_khz 1500
+adapter speed 1500
 
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/tmpa900.cfg b/tcl/target/tmpa900.cfg
index 3ba3591..8e70700 100644
--- a/tcl/target/tmpa900.cfg
+++ b/tcl/target/tmpa900.cfg
@@ -28,7 +28,7 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CP
 
 #use combined on interfaces or targets that can't set TRST/SRST separately
 reset_config trst_and_srst
-adapter_nsrst_delay 20
+adapter srst delay 20
 jtag_ntrst_delay 20
 
 ######################
diff --git a/tcl/target/tmpa910.cfg b/tcl/target/tmpa910.cfg
index 5d41c8c..d933c0b 100644
--- a/tcl/target/tmpa910.cfg
+++ b/tcl/target/tmpa910.cfg
@@ -28,7 +28,7 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CP
 
 #use combined on interfaces or targets that can't set TRST/SRST separately
 reset_config trst_and_srst
-adapter_nsrst_delay 20
+adapter srst delay 20
 jtag_ntrst_delay 20
 
 ######################
diff --git a/tcl/target/tnetc4401.cfg b/tcl/target/tnetc4401.cfg
new file mode 100644
index 0000000..48f7545
--- /dev/null
+++ b/tcl/target/tnetc4401.cfg
@@ -0,0 +1,17 @@
+# Texas Instruments (TI) TNETC4401, MIPS32 DOCSIS-tailored SoC (4Kc-based)
+# Used in Knovative KC-100 and Motorola Surfboard SB5120 cable modems.
+# Datasheet: https://brezn.muc.ccc.de/~mazzoo/DOCSIS/tnetc4401.pdf
+transport select jtag
+set _TARGETNAME tnetc4401
+set _CPUTAPID 0x0000100f
+jtag newtap $_TARGETNAME tap -irlen 5 -ircapture 0x01 -irmask 0x1f -expected-id $_CPUTAPID
+target create $_TARGETNAME mips_m4k -chain-position $_TARGETNAME.tap -endian big
+
+# May need to halt manually before calling reset init
+$_TARGETNAME configure -event reset-init {
+	halt
+	echo "Attempting to disable watchdog..."
+	mwb phys 0xa8610b00 0 256
+	halt
+	wait_halt
+}
diff --git a/tcl/target/u8500.cfg b/tcl/target/u8500.cfg
index 7ff3929..36e0db7 100644
--- a/tcl/target/u8500.cfg
+++ b/tcl/target/u8500.cfg
@@ -1,6 +1,6 @@
 #  Copyright (C) ST-Ericsson SA 2011
 #  Author : michel.jaouen@stericsson.com
-#  U8500 target 
+#  U8500 target
 
 proc mmu_off {} {
 	set cp [arm mrc 15 0 1 0 0]
@@ -31,7 +31,7 @@ proc ocd_gdb_restart {target_id} {
 proc smp_reg {} {
 	global _TARGETNAME_1
     global _TARGETNAME_2
-    targets $_TARGETNAME_1 
+    targets $_TARGETNAME_1
 	echo "$_TARGETNAME_1"
 	set pc1 [reg pc]
 	set stck1 [reg sp_svc]
@@ -68,7 +68,7 @@ proc pwrsts { } {
 		8 {
 			echo "A9 100% DVFS"
 		  }
-		c { 
+		c {
 			echo "A9 50% DVFS"
 		}
 	}
@@ -144,7 +144,7 @@ tcl_port 5555
 telnet_port 4444
 gdb_port 3333
 
-if { [info exists CHIPNAME] } {	
+if { [info exists CHIPNAME] } {
 global _CHIPNAME
     set _CHIPNAME $CHIPNAME
 } else {
@@ -194,12 +194,12 @@ set _TARGETNAME_1 $TARGETNAME_1
 if { [info exists DAP_DBG1] } {
 	set _DAP_DBG1 $DAP_DBG1
 } else {
-	set _DAP_DBG1 0x801A8000 
+	set _DAP_DBG1 0x801A8000
 }
 if { [info exists DAP_DBG2] } {
 	set _DAP_DBG2 $DAP_DBG2
 } else {
-	set _DAP_DBG2 0x801AA000 
+	set _DAP_DBG2 0x801AA000
 }
 
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
@@ -226,7 +226,7 @@ global _SMP
 set _SMP $SMP
 }
 global SMP
-if { $_SMP == 1} { 
+if { $_SMP == 1} {
 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
 }
 
@@ -264,7 +264,7 @@ proc att { } {
 	} else {
 		echo "target secured"
 	}
-	
+
 }
 
 
@@ -310,11 +310,11 @@ if {![info exists MAXSPEED]} {
 global _MAXSPEED
 set _MAXSPEED 15000
 } else {
-global _MAXSPEED 
+global _MAXSPEED
 set _MAXSPEED $MAXSPEED
 }
-global _MAXSPEED 
-adapter_khz $_MAXSPEED
+global _MAXSPEED
+adapter speed $_MAXSPEED
 
 
 gdb_breakpoint_override hard
@@ -322,5 +322,3 @@ set mem inaccessible-by-default-off
 
 jtag_ntrst_delay 100
 reset_config trst_and_srst combined
-
-
diff --git a/tcl/target/vybrid_vf6xx.cfg b/tcl/target/vybrid_vf6xx.cfg
index 7cb916d..c888d25 100644
--- a/tcl/target/vybrid_vf6xx.cfg
+++ b/tcl/target/vybrid_vf6xx.cfg
@@ -34,4 +34,4 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 set _TARGETNAME $_CHIPNAME.cpu
 target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap -dbgbase 0xc0088000
 target create ${_TARGETNAME}1 cortex_m -dap $_CHIPNAME.dap -ap-num 3 -defer-examine
-adapter_khz 1000
+adapter speed 1000
diff --git a/tcl/target/xmc1xxx.cfg b/tcl/target/xmc1xxx.cfg
index e693b59..eb94d7b 100644
--- a/tcl/target/xmc1xxx.cfg
+++ b/tcl/target/xmc1xxx.cfg
@@ -38,4 +38,4 @@ $_TARGETNAME configure -work-area-phys 0x20000000 \
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME xmc1xxx 0x10000000 0 0 0 $_TARGETNAME
 
-adapter_khz 1000
+adapter speed 1000
diff --git a/tcl/target/xmc4xxx.cfg b/tcl/target/xmc4xxx.cfg
index e106d34..3020b28 100644
--- a/tcl/target/xmc4xxx.cfg
+++ b/tcl/target/xmc4xxx.cfg
@@ -57,4 +57,4 @@ if { ![using_hla] } {
 	cortex_m reset_config sysresetreq
 }
 
-adapter_khz 1000
+adapter speed 1000
diff --git a/tcl/target/zynq_7000.cfg b/tcl/target/zynq_7000.cfg
index 1562768..b4b6f9f 100644
--- a/tcl/target/zynq_7000.cfg
+++ b/tcl/target/zynq_7000.cfg
@@ -23,7 +23,7 @@ target create ${_TARGETNAME}1 cortex_a -dap $_CHIPNAME.dap \
     -coreid 1 -dbgbase 0x80092000
 target smp ${_TARGETNAME}0 ${_TARGETNAME}1
 
-adapter_khz 1000
+adapter speed 1000
 
 ${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit"
 ${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit"
diff --git a/tcl/test/selftest.cfg b/tcl/test/selftest.cfg
index be420ca..be420ca 100755..100644
--- a/tcl/test/selftest.cfg
+++ b/tcl/test/selftest.cfg
diff --git a/tcl/test/syntax1.cfg b/tcl/test/syntax1.cfg
index 79d5384..2e66188 100644
--- a/tcl/test/syntax1.cfg
+++ b/tcl/test/syntax1.cfg
@@ -1,12 +1,12 @@
-adapter_nsrst_delay 200
+adapter srst delay 200
 jtag_ntrst_delay 200
 
 #use combined on interfaces or targets that can't set TRST/SRST separately
 reset_config trst_and_srst srst_pulls_trst
 
 #LPCs need reset pulled while RTCK is low. 0 to activate JTAG, power-on reset is not enough
-jtag_reset 1 1
-jtag_reset 0 0
+adapter assert trst assert srst
+adapter deassert trst deassert srst
 
 #jtag scan chain
 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
@@ -27,4 +27,3 @@ mvb 0xE01FC040 0x01
 
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 0 lpc2000_v2 14765
-
diff --git a/tcl/tools/firmware-recovery.tcl b/tcl/tools/firmware-recovery.tcl
index 8e017ce..9d7e0fc 100644
--- a/tcl/tools/firmware-recovery.tcl
+++ b/tcl/tools/firmware-recovery.tcl
@@ -29,7 +29,7 @@ dump_part <name> <filename>	save partition's contents to a file
 erase_part <name>		erase the given partition
 flash_part <name> <filename>	erase, flash and verify the given partition
 ram_boot <filename>		load binary file to RAM and run it
-adapter_khz <freq>		set JTAG clock frequency in kHz
+adapter speed <freq>		set JTAG clock frequency in kHz
 
 For example, to clear nvram and reflash CFE on an RT-N16 using TUMPA, run:
 openocd -f interface/ftdi/tumpa.cfg -f tools/firmware-recovery.tcl \\
@@ -38,8 +38,8 @@ openocd -f interface/ftdi/tumpa.cfg -f tools/firmware-recovery.tcl \\
     shutdown
 }
 
-# set default, can be overriden later
-adapter_khz 1000
+# set default, can be overridden later
+adapter speed 1000
 
 proc get_partition { name } {
     global partition_list
author	Tim Newsome <tim@sifive.com>	2020-06-23 13:05:43 -0700
committer	Tim Newsome <tim@sifive.com>	2020-06-23 13:05:43 -0700
commit	e07613de332d2cda48cd1a845b6e19171f084571 (patch)
tree	e32451d4730030a2b1e8539cbfd6abf590a07896 /tcl
parent	4579dd93586ab361f40da6cbd9e3e0681efc866b (diff)
parent	8833c889da07eae750bcbc11215cc84323de9b74 (diff)
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