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2023-04-28target/riscv: Support VS-stage and G-stage address translation.hypervisor_translateTim Newsome1-5/+212
2023-04-25target/riscv: Refactor to create riscv_effective_privilege_mode()Tim Newsome1-7/+34
2023-04-25target/riscv: Move some code from riscv_address_translate() to riscv_virt2phys()Tim Newsome1-53/+55
2023-04-25Comment pte_shiftTim Newsome1-0/+1
2023-04-25target/riscv: Add constants for vsatp, hgatpTim Newsome2-0/+5
2023-04-13workflow: Run checkpatch against diff with riscv (#822)Tim Newsome1-3/+7
2023-04-12Preserve artifact of Linux build, too. (#828)Tim Newsome1-6/+24
2023-04-11Merge pull request #835 from en-sc/en-sc/fix-err-resumeTim Newsome1-2/+2
2023-04-11Merge pull request #833 from zqb-all/read_log128Tim Newsome1-31/+40
2023-04-10target/riscv: Handle error code in resume_prepEvgeniy Naydanov1-2/+2
2023-04-10target/riscv: support log memory access128 for readMark Zhuang1-31/+40
2023-04-07Merge pull request #823 from panciyan/riscvTim Newsome1-1/+1
2023-04-06Merge pull request #821 from en-sc/en-sc/fix-reset-mhartsTim Newsome1-91/+62
2023-04-06Merge pull request #830 from zqb-all/csr_32bitTim Newsome1-2/+12
2023-04-05Merge pull request #825 from riscv/hypervisorTim Newsome2-3/+9
2023-04-05Merge branch 'riscv' into hypervisorTim Newsome1588-13975/+27065
2023-04-05target/riscv: simplify resetEvgeniy Naydanov1-91/+62
2023-04-05Merge pull request #816 from riscv/from_upstreamTim Newsome1588-13878/+26962
2023-04-04Merge pull request #819 from zqb-all/fix_size_assertTim Newsome3-90/+96
2023-04-04flash/nor/spi: Move mt25ql02 to match upstream.Tim Newsome1-1/+1
2023-04-03target/riscv: set some csr size to 32Mark Zhuang1-2/+12
2023-03-30Merge pull request #829 from XuHangHub/riscvTim Newsome1-3/+3
2023-03-29Merge pull request #824 from riscv/aiaTim Newsome1-3/+3
2023-03-29target/riscv: Set hypervisor bits.Tim Newsome2-3/+9
2023-03-29doc/openocd.texi: fix expose_csrs exampleHang Xu1-3/+3
2023-03-28Merge pull request #826 from riscv/icount_maskmaxTim Newsome1-1/+1
2023-03-25target/riscv: [NFC] rename variables named read/writeMark Zhuang3-74/+54
2023-03-25target/riscv: support log memory access128Mark Zhuang1-18/+44
2023-03-24target/riscv: Don't ignore maskmax for icount.Tim Newsome1-1/+1
2023-03-24target/riscv: AIA regs, check for H not VTim Newsome1-3/+3
2023-03-23target/riscv: leaf PTE check PTE_W missingpanciyan1-1/+1
2023-03-22Merge pull request #818 from riscv/windows_buildopenocd64-d486b21Tim Newsome1-0/+6
2023-03-21Upload Windows binary as artifact.Tim Newsome1-0/+6
2023-03-20Merge pull request #815 from riscv/s_aiaTim Newsome5-96/+250
2023-03-17workflow/checkpatch: Install python modules for spdxcheck.pyTim Newsome1-1/+1
2023-03-17gdb_server: Keep working if gdb requests a non-existent regTim Newsome1-1/+1
2023-03-16Fix build.Tim Newsome3-11/+10
2023-03-16Merge commit '1293ddd65713d6551775b67169387622ada477c1' into from_upstreamTim Newsome1587-13867/+26952
2023-03-16Merge pull request #800 from en-sc/en-sc/try-all-trigs-in-maybe-add-trigTim Newsome1-185/+245
2023-03-16Expose S?aia CSRs if they're on the target.Tim Newsome4-3/+88
2023-03-16Update encoding.h.Tim Newsome1-93/+162
2023-03-15Merge pull request #812 from XuHangHub/riscvTim Newsome1-5/+5
2023-03-15Try all triggers in maybe_add_trigger_t2 and _t6Evgeniy Naydanov1-185/+245
2023-03-13Merge pull request #811 from riscv/address_inTim Newsome1-2/+1
2023-03-12target/riscv: fix the bug of using S2 register in read_memory_progbufHang Xu1-5/+5
2023-03-10target/riscv: Remove unused address_in variable.Tim Newsome1-2/+1
2023-03-08Calculate the FreeRTOS type sizes and offsets more adaptively. (#806)Chao Du2-6/+55
2023-03-07Merge pull request #807 from riscv/from_upstreamTim Newsome65-440/+7139
2023-03-06Merge branch 'riscv' into from_upstreamTim Newsome1-1/+1
2023-03-06Merge pull request #810 from riscv/snapshotTim Newsome1-1/+1
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