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| author | Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> | 2024-05-08 18:46:30 +0300 |
|---|---|---|
| committer | Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> | 2024-06-04 19:22:11 +0300 |
| commit | c470cd21ae3b2e76551ec73782d48bc4520e7145 (patch) | |
| tree | 64f5ceabad5b69700b2fe147151121248a1141b1 | |
| parent | b548653f66db7cc73bd0bdce33bc51220e509078 (diff) | |
| download | riscv-openocd-c470cd21ae3b2e76551ec73782d48bc4520e7145.zip riscv-openocd-c470cd21ae3b2e76551ec73782d48bc4520e7145.tar.gz riscv-openocd-c470cd21ae3b2e76551ec73782d48bc4520e7145.tar.bz2 | |
Revert "Initialize all registers in examine"
This reverts commit 9d4df3420c51e75bcc1d6162fc9cc680d6fd2481.
I believe the reasoning behind this workaround is no longer valid.
Change-Id: Ie8705f75eb8ad7b72fc8ffcf39125be764cb43be
| -rw-r--r-- | src/target/riscv/riscv-011.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c index 64379dc..14af071 100644 --- a/src/target/riscv/riscv-011.c +++ b/src/target/riscv/riscv-011.c @@ -1584,8 +1584,6 @@ static int examine(struct target *target) return result; target_set_examined(target); - for (size_t i = 0; i < 32; ++i) - reg_cache_set(target, i, -1); LOG_INFO("Examined RISCV core; XLEN=%d, misa=0x%" PRIx64, riscv_xlen(target), r->misa); |