| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 16 hours | Merge pull request #1839 from ved-rivos/issue_1838HEADmaster | Andrew Waterman | 1 | -3/+2 | |
| add missing sdt/sie interaction when writing mstatus directly | |||||
| 24 hours | add missing sdt/sie interaction when writing mstatus directly | Ved Shanbhogue | 1 | -3/+2 | |
| 4 days | Merge pull request #1835 from joe-rivos/fix-ignored-attributes-warning | Andrew Waterman | 1 | -1/+1 | |
| Fix ignored-attributes warning for unique_ptr declaration | |||||
| 4 days | Fix ignored-attributes warning for unique_ptr declaration | Joseph Faulls | 1 | -1/+1 | |
| The attribute `__nonnull` was added to `fclose` in glibc 2.38, which causes a warning when using its `decltype` on a template argument. | |||||
| 5 days | Merge pull request #1834 from aap-sc/master | Andrew Waterman | 1 | -2/+2 | |
| update encoding.h to get rid of erroneous define | |||||
| 5 days | update encoding.h to get rid of erroneous define | Parshintsev Anatoly | 1 | -2/+2 | |
| 2024-10-04 | Merge pull request #1829 from NXP/update-zilsd-to-v0.10 | Andrew Waterman | 9 | -15/+15 | |
| Updated load/store pair for RV32 to v0.10 | |||||
| 2024-10-04 | Updated load/store pair for RV32 to v0.10 | Christian Herber | 9 | -15/+15 | |
| - renamed Zcmlsd to Zclsd - bumped version number | |||||
| 2024-10-02 | Merge pull request #1822 from howjmay/typos | Andrew Waterman | 5 | -6/+6 | |
| fix typos | |||||
| 2024-10-02 | fix typos | Yang Hau | 5 | -6/+6 | |
| 2024-10-01 | Merge pull request #1823 from YenHaoChen/pr-halt | Andrew Waterman | 1 | -3/+2 | |
| Change -H flag into --halted | |||||
| 2024-10-01 | Merge pull request #1826 from riscv-software-src/fix-1825 | Andrew Waterman | 1 | -7/+39 | |
| Fix f64_to_bf16 raising underflow when it shouldn't | |||||
| 2024-10-01 | Change -H flag into --halted | YenHaoChen | 1 | -3/+2 | |
| There is a comment about aiming at --halted but failing to achieve so. This commit provides the behavior. | |||||
| 2024-09-30 | Fix f64_to_bf16 raising underflow when it shouldn't | Andrew Waterman | 1 | -7/+39 | |
| Resolves #1825 | |||||
| 2024-09-27 | Merge pull request #1819 from riscv-software-src/ss-cbo-fault | Andrew Waterman | 2 | -5/+6 | |
| Raise store/AMO access fault on CBO to shadow-stack page | |||||
| 2024-09-26 | Merge pull request #1820 from YenHaoChen/pr-halt | Andrew Waterman | 4 | -6/+2 | |
| refactor: Remove dcsr::halt variable | |||||
| 2024-09-27 | refactor: Merge halt and halt_on_reset variables in processor_t | YenHaoChen | 3 | -5/+2 | |
| 2024-09-27 | refactor: Move halt out of dcsr | YenHaoChen | 5 | -5/+4 | |
| Suggested in https://github.com/riscv-software-src/riscv-isa-sim/pull/1816#pullrequestreview-2331806142. | |||||
| 2024-09-26 | Raise store/AMO access fault on CBO to shadow-stack page | Andrew Waterman | 2 | -5/+6 | |
| Proliferating the access_flags isn't ideal, but it wasn't clear how better to handle this case. | |||||
| 2024-09-26 | Merge pull request #1816 from YenHaoChen/pr-halt | Andrew Waterman | 1 | -0/+1 | |
| Only enter debug mode once with -H flag (halt_on_reset) | |||||
| 2024-09-26 | Only enter debug mode once with -H flag (halt_on_reset) | YenHaoChen | 1 | -0/+1 | |
| 2024-09-20 | Merge pull request #1812 from riscv-software-src/fix-1810 | Andrew Waterman | 1 | -2/+22 | |
| Further improve ISA-string input validation | |||||
| 2024-09-20 | Validate Zvl ISA string correctly | Andrew Waterman | 1 | -2/+22 | |
| See #1810 for explanation of how this can go wrong. Resolves #1810 | |||||
| 2024-09-20 | Merge pull request #1811 from riscv-software-src/fix-1810 | Andrew Waterman | 1 | -1/+1 | |
| Validate Zvl ISA string correctly | |||||
| 2024-09-20 | Validate Zvl ISA string correctly | Andrew Waterman | 1 | -1/+1 | |
| See #1810 for explanation of how this can go wrong. Resolves #1810 | |||||
| 2024-09-18 | Merge pull request #1804 from ved-rivos/ssdbltrp_typo | Andrew Waterman | 1 | -1/+1 | |
| Fix error in reading right sstatus | |||||
| 2024-09-17 | fix error in reading right sstatus | Ved Shanbhogue | 1 | -1/+1 | |
| 2024-09-14 | Merge pull request #1807 from riscv-software-src/remove-compile-flags | Jerry Zhao | 7 | -53/+5 | |
| Remove --with-isa/priv compile flags | |||||
| 2024-09-14 | Remove leftover config.h includes in dasm/log-parser | Jerry Zhao | 2 | -2/+0 | |
| 2024-09-14 | Remove --with-priv compile flag | Jerry Zhao | 5 | -25/+2 | |
| 2024-09-14 | Remove --with-isa compile-time option | Jerry Zhao | 6 | -26/+3 | |
| 2024-09-11 | Merge pull request #1796 from cyyself/tmp_mcountinhibit | Andrew Waterman | 4 | -4/+19 | |
| add support for mcountinhibit CSR | |||||
| 2024-09-11 | Merge pull request #1793 from rtwfroody/native_triggers2 | YenHaoChen | 5 | -26/+53 | |
| Only implement one solution for native triggers. | |||||
| 2024-09-09 | Only implement one solution for native triggers. | Tim Newsome | 2 | -15/+29 | |
| When S-mode is present, use option 1 (disable triggers in M-mode unless MIE is set) from the Debug Spec. When S-mode is not present, use option 2 (implement mte and mpte bits in tcontrol). See discussion in #1777. | |||||
| 2024-09-09 | triggers: Move allow_action() into common_match() | Tim Newsome | 2 | -23/+28 | |
| They are always called together, and now we get the previous privilege behavior in both. | |||||
| 2024-09-05 | Make allow_action() take proc instead of state | Tim Newsome | 2 | -6/+7 | |
| 2024-09-05 | Work if tcontrol doesn't exist. | Tim Newsome | 3 | -3/+10 | |
| 2024-09-06 | add support for mcountinhibit CSR | Yangyu Chen | 4 | -4/+19 | |
| We hardwired mcountinihibit to 0 previously. Now, we implemented it. Signed-off-by: Yangyu Chen <cyy@cyyself.name> | |||||
| 2024-09-02 | Merge pull request #1797 from YenHaoChen/pr-vector | Andrew Waterman | 1 | -20/+48 | |
| vector: disassemble: Let operand ordering be vd, [vrf]s1, vs2 to vector multiply-add instructions | |||||
| 2024-09-03 | vector: disassemble: Let operand ordering be vd, [vf]s1, vs2 to vector ↵ | YenHaoChen | 1 | -4/+4 | |
| widening floating-point fused multiply-add instructions | |||||
| 2024-09-03 | vector: disassemble: Let operand ordering be vd, [vf]s1, vs2 to vector ↵ | YenHaoChen | 1 | -8/+18 | |
| single-width floating-point fused multiply-add instructions | |||||
| 2024-09-03 | vector: disassemble: Let operand ordering be vd, [vr]s1, vs2 to vector ↵ | YenHaoChen | 1 | -4/+6 | |
| widening integer multiply-add instructions | |||||
| 2024-09-03 | vector: disassemble: Let operand ordering be vd, [vr]s1, vs2 to vector ↵ | YenHaoChen | 1 | -4/+20 | |
| single-width integer multiply-add instructions | |||||
| 2024-09-02 | Merge pull request #1788 from riscv-software-src/support-larger-addresses | Andrew Waterman | 4 | -43/+36 | |
| Lift restriction on physical-address size | |||||
| 2024-08-30 | Merge pull request #1779 from rtwfroody/trigger_timing | Andrew Waterman | 1 | -1/+8 | |
| For mcontrol6, default to BEFORE timing. | |||||
| 2024-08-29 | Merge pull request #1791 from YenHaoChen/pr-pm | Andrew Waterman | 1 | -1/+1 | |
| pointer masking: Always apply sstatus.MXR regardless of effective V | |||||
| 2024-08-29 | pointer masking: Always apply sstatus.MXR regardless of effective V | YenHaoChen | 1 | -1/+1 | |
| ISA spec says "Setting MXR at HS-level overrides both VS-stage and G-stage execute-only permissions." | |||||
| 2024-08-28 | Merge pull request #1789 from YenHaoChen/pr-pm | Andrew Waterman | 1 | -1/+1 | |
| pointer masking: Consider effective v bit instead of current v bit | |||||
| 2024-08-28 | pointer masking: Consider effective v bit instead of current v bit | YenHaoChen | 1 | -1/+1 | |
| A previous commit removes the effectiveness of MPRV to MXR. (https://github.com/riscv-software-src/riscv-isa-sim/pull/1784) However, the removal implies the MPRV affects point masking individually, and the MXR should consider the effective v bit. | |||||
| 2024-08-27 | Merge pull request #1787 from riscv-software-src/fix-cfg-priv | Jerry Zhao | 1 | -1/+1 | |
 |
index : riscv-tools/riscv-isa-sim.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
| aboutsummaryrefslogtreecommitdiff |