diff options
| author | Andrew Waterman <andrew@sifive.com> | 2024-09-18 04:06:33 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-09-18 04:06:33 -0700 |
| commit | 52aff0233f5cc844ea047b4e16806f576cd8815b (patch) | |
| tree | 548740ae114e488fd136370fb0e9b9594c82d412 | |
| parent | 0cc5ecce053c6dfa44e4a865d2838fc8d7d771dc (diff) | |
| parent | a8525b62430432c020bd01f1ce51d10f36cc8da3 (diff) | |
| download | riscv-isa-sim-52aff0233f5cc844ea047b4e16806f576cd8815b.zip riscv-isa-sim-52aff0233f5cc844ea047b4e16806f576cd8815b.tar.gz riscv-isa-sim-52aff0233f5cc844ea047b4e16806f576cd8815b.tar.bz2 | |
Merge pull request #1804 from ved-rivos/ssdbltrp_typo
Fix error in reading right sstatus
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 60f6a89..c4d8c06 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -446,7 +446,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc) // An unexpected trap - a trap when SDT is 1 - traps to M-mode if ((state.prv <= PRV_S && bit < max_xlen) && (((vsdeleg >> bit) & 1) || ((hsdeleg >> bit) & 1))) { - reg_t s = curr_virt ? state.nonvirtual_sstatus->read() : state.sstatus->read(); + reg_t s = state.sstatus->read(); supv_double_trap = get_field(s, MSTATUS_SDT); if (supv_double_trap) vsdeleg = hsdeleg = 0; |