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34 hoursMerge pull request #1812 from riscv-software-src/fix-1810HEADmasterAndrew Waterman1-2/+22
42 hoursValidate Zvl ISA string correctlyAndrew Waterman1-2/+22
42 hoursMerge pull request #1811 from riscv-software-src/fix-1810Andrew Waterman1-1/+1
42 hoursValidate Zvl ISA string correctlyAndrew Waterman1-1/+1
4 daysMerge pull request #1804 from ved-rivos/ssdbltrp_typoAndrew Waterman1-1/+1
4 daysfix error in reading right sstatusVed Shanbhogue1-1/+1
8 daysMerge pull request #1807 from riscv-software-src/remove-compile-flagsJerry Zhao7-53/+5
8 daysRemove leftover config.h includes in dasm/log-parserJerry Zhao2-2/+0
8 daysRemove --with-priv compile flagJerry Zhao5-25/+2
8 daysRemove --with-isa compile-time optionJerry Zhao6-26/+3
10 daysMerge pull request #1796 from cyyself/tmp_mcountinhibitAndrew Waterman4-4/+19
11 daysMerge pull request #1793 from rtwfroody/native_triggers2YenHaoChen5-26/+53
12 daysOnly implement one solution for native triggers.Tim Newsome2-15/+29
12 daystriggers: Move allow_action() into common_match()Tim Newsome2-23/+28
2024-09-05Make allow_action() take proc instead of stateTim Newsome2-6/+7
2024-09-05Work if tcontrol doesn't exist.Tim Newsome3-3/+10
2024-09-06add support for mcountinhibit CSRYangyu Chen4-4/+19
2024-09-02Merge pull request #1797 from YenHaoChen/pr-vectorAndrew Waterman1-20/+48
2024-09-03vector: disassemble: Let operand ordering be vd, [vf]s1, vs2 to vector wideni...YenHaoChen1-4/+4
2024-09-03vector: disassemble: Let operand ordering be vd, [vf]s1, vs2 to vector single...YenHaoChen1-8/+18
2024-09-03vector: disassemble: Let operand ordering be vd, [vr]s1, vs2 to vector wideni...YenHaoChen1-4/+6
2024-09-03vector: disassemble: Let operand ordering be vd, [vr]s1, vs2 to vector single...YenHaoChen1-4/+20
2024-09-02Merge pull request #1788 from riscv-software-src/support-larger-addressesAndrew Waterman4-43/+36
2024-08-30Merge pull request #1779 from rtwfroody/trigger_timingAndrew Waterman1-1/+8
2024-08-29Merge pull request #1791 from YenHaoChen/pr-pmAndrew Waterman1-1/+1
2024-08-29pointer masking: Always apply sstatus.MXR regardless of effective VYenHaoChen1-1/+1
2024-08-28Merge pull request #1789 from YenHaoChen/pr-pmAndrew Waterman1-1/+1
2024-08-28pointer masking: Consider effective v bit instead of current v bitYenHaoChen1-1/+1
2024-08-27Merge pull request #1787 from riscv-software-src/fix-cfg-privJerry Zhao1-1/+1
2024-08-27Lift restriction on physical-address sizeAndrew Waterman3-18/+4
2024-08-27Use create_mem_region for legacy -m argumentAndrew Waterman1-3/+3
2024-08-27Check size_t bounds overflow in create_mem_regionAndrew Waterman1-2/+4
2024-08-27Factor out create_mem_region from parse_mem_layoutAndrew Waterman1-36/+41
2024-08-27Merge pull request #1786 from YenHaoChen/pr-mcontrolAndrew Waterman2-6/+8
2024-08-27Use cmdline --priv flag when parsing proc configurations from DTBJerry Zhao1-1/+1
2024-08-27triggers: Let mcontrol.match be default (0/equal) if maskmax is 0YenHaoChen2-5/+6
2024-08-27triggers: mcontrol: refactor: Add mcontrol_t::maskmaxYenHaoChen2-1/+2
2024-08-26Merge pull request #1784 from YenHaoChen/pr-pmAndrew Waterman1-1/+1
2024-08-26pointer masking: Pointer masking does not apply when MXR=1 regardless of MPRV...YenHaoChen1-1/+1
2024-08-23Merge pull request #1783 from riscv-software-src/fix-1782Andrew Waterman4-25/+27
2024-08-23Fix exception priority for RV32E JAL/JALRAndrew Waterman3-0/+3
2024-08-23Fix exception priority for RV32E loads and AMOsAndrew Waterman1-1/+1
2024-08-23Refactor insn_template to be more DRYAndrew Waterman1-24/+23
2024-08-20For mcontrol6, default to BEFORE timing.Tim Newsome1-1/+8
2024-08-19Merge pull request #1771 from rtwfroody/match_maskAndrew Waterman1-4/+8
2024-08-19Fix mcontrol6 mask low/high operations.Tim Newsome1-4/+8
2024-08-18Merge pull request #1722 from ved-rivos/smdbltrpAndrew Waterman12-20/+95
2024-08-17Merge pull request #1776 from YenHaoChen/pr-pmAndrew Waterman1-4/+6
2024-08-18pointer masking: refactor: Use xlen to avoid sketchy, hardcoded number 64YenHaoChen1-1/+2
2024-08-16pointer masking: Fix: Let transformed_addr of fetching be unchangedYenHaoChen1-4/+5