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riscv-tests.git
attempt-travis-fix
ceasetest2
compliance_tests
cs152-sp18-lab3
debug
debug-0.13
debug-clear-satp
debug-delete-sim
debug_auth
debug_disassemble
disable_unavailable
dma-memcpy
eos20-bringup
hw_watchpoint
interrupts
master
misc
no_progbuf
priv
privchange-dontdeleteme
python3
rekall
resume_from_trigger
riscv-tests-sail
rtos
rvt-master
smi-demo
split-isa-tests
sqrt-171
tmp
trap_entry_align
trap_entry_align-1
travis-dev
trigger_priority
usb_error
xlen_fix
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Commit message
Author
Age
ceasetest2
Check basic debugging still works in CeaseMulti
Tim Newsome
23 months
debug
Add debug statement.
Tim Newsome
5 years
debug_disassemble
debug: On failure, disassemble close instructions.
Tim Newsome
2 years
disable_unavailable
debug: Disable Unavailable tests.
Tim Newsome
11 months
master
Merge pull request #581 from en-sc/en-sc/reserve-trigger-fix-propper
Evgeniy Naydanov
6 weeks
misc
Make newer version of pylint happy.
Tim Newsome
5 years
python3
Move to Python 3.
Tim Newsome
5 years
riscv-tests-sail
removed the env/ directory, which was a submodule dir. replaced at a higher l...
William McSpaddden
5 months
tmp
tmp
Andrew Waterman
5 years
trigger_priority
Remove ineffective tests.
Tim Newsome
2 years
[...]
Age
Commit message
Author
Files
Lines
2016-02-29
Separate M, and A from I. Allow disabling of M,A,F
travis-dev
Colin Schmidt
65
-21
/
+159
2016-02-29
if atomics are unavailable emulate them ala pk emu
Colin Schmidt
2
-12
/
+24
2016-02-28
Fix capitalization of XLEN variable
Andrew Waterman
1
-1
/
+1
2016-02-28
Strip big-endian tests
Andrew Waterman
4
-24
/
+0
2016-02-27
Merge pull request #10 from riscv/travis-dev
Palmer Dabbelt
5
-103
/
+302
2016-02-27
only build the rv32 bit tests if xlen is 32
Colin Schmidt
1
-0
/
+3
2016-02-27
remove malloc declaration from dhrystone
Colin Schmidt
1
-1
/
+0
2016-02-27
allow make variables to be overwritten update configure
Colin Schmidt
4
-102
/
+299
2016-02-23
make install rule copy the right things to the right places
Howard Mao
1
-4
/
+8
2016-02-23
fix install rule
Howard Mao
1
-0
/
+1
[...]