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2022-10-07debug: On failure, disassemble close instructions.debug_disassembleTim Newsome1-1/+1
2022-10-06Merge pull request #414 from YenHaoChen/pr-timestampTim Newsome1-2/+2
2022-10-05Update testlib.py; remove ANSI escape sequencesYenHaoChen1-1/+2
2022-10-05update gdbserver.py; release tolerance value of MemorySampleTest()YenHaoChen1-2/+2
2022-09-27rv64ui test misaligned load/store data (#410)John Ingalls2-0/+388
2022-09-27zicboz: comment # (#412)John Ingalls1-1/+1
2022-09-26zicbo test zero (#411)John Ingalls3-2/+49
2022-07-25Ignore `mip` and `time` in DisconnectTest. (#406)Tim Newsome1-1/+2
2022-07-22Fix string formatting in testlib.assertTrue()Tim Newsome1-1/+1
2022-07-14Pylint fix. (#405)Tim Newsome1-1/+2
2022-07-14Only run SemihostingFileio on single hart systems. (#404)Tim Newsome1-0/+11
2022-07-11Debug MemorySampleMixed: Disable 64-bit sampling on 32-bit targets (#402)Luke Wren1-2/+6
2022-07-08Fix SemihostingFileio (#403)Tim Newsome1-1/+2
2022-07-01Complete this pass of pylint changes. (#401)Tim Newsome2-149/+151
2022-06-23Another pylint upgrade. (#398)Tim Newsome3-173/+191
2022-06-21Update information about Makefile fragments (#399)Mehmet Oguz Derin1-4/+2
2022-06-09Test misaligned stores. (#397)Tim Newsome8-0/+158
2022-06-08Merge pull request #395 from riscv-software-src/misaligned_storeAndrew Waterman10-6/+164
2022-06-08Test semihosting_fileioTim Newsome2-4/+27
2022-06-07Test misaligned loads.Tim Newsome8-0/+160
2022-06-07Set TESTNUM before executing code.Tim Newsome3-6/+4
2022-06-06Revert unaligned tests.Tim Newsome3-51/+1
2022-06-06Test unaligned ld accesses.Tim Newsome1-0/+27
2022-06-06Add unaligned test cases for lwTim Newsome1-0/+23
2022-06-06Set TESTNUM before executing code.Tim Newsome1-1/+1
2022-05-31Address pylint warnings. (#385)Tim Newsome8-15/+16
2022-05-31Fix GdbTest.disable_pmp failing on systems which support NAPOT but not TOR re...Luke Wren1-2/+8
2022-05-28Permit mtval to be zero in misaligned address test, fixes #389 (#390)Luke Wren1-0/+2
2022-05-16V implies FD now. (#382)Tim Newsome1-3/+3
2022-04-25Add EbreakTest. (#380)Tim Newsome2-0/+62
2022-04-07Make download test data const. (#378)Tim Newsome1-2/+2
2022-03-08Add Zfh and Svnapot to Spike ISA stringAndrew Waterman1-2/+2
2022-03-03With new OpenOCD, gdb prints thread info differently (#373)Tim Newsome1-1/+2
2022-03-03Add assert to MemorySampleTest. (#370)Tim Newsome1-0/+1
2022-02-09Debug test to check that stepping doesn't inappropriately switch to Thread 1 ...Greg Savin1-0/+21
2022-01-06Add gdb.interact() for debug tests. (#367)Tim Newsome1-0/+18
2021-11-29Fix TranslateTests. (#365)Tim Newsome2-5/+7
2021-11-12Set `riscv resume_order reversed`. (#363)Tim Newsome1-0/+2
2021-11-12Create DisconnectTest. (#364)Tim Newsome2-32/+53
2021-11-12Add timing output to DebugTurboStep. (#362)Tim Newsome1-1/+5
2021-10-05Remove slen. (#360)Tim Newsome4-22/+16
2021-07-22Fix #352 (#353)Daniel Lustig1-2/+2
2021-07-21Move the Svnapot test to its own folder (#351)Daniel Lustig4-1/+10
2021-07-19Bump envAndrew Waterman1-20/+0
2021-07-19Add a test for Svnapot (#349)Daniel Lustig2-0/+173
2021-07-19Debug tests: catch write to nonexistent trigger registers in entry.S (#348)Luke Wren1-0/+7
2021-06-29Update README.md (#342)mymatin1-1/+1
2021-06-08Tweaks for multispike. (#339)Tim Newsome3-9/+19
2021-06-01Enable access to cycle counter before trying to write itAndrew Waterman1-0/+13
2021-06-01Test all four ways of reading a read-only CSRAndrew Waterman1-0/+8
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