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| author | Tim Newsome <tim@sifive.com> | 2022-05-27 12:57:03 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2022-05-27 12:57:03 -0700 |
| commit | e9de81960f81ea8ad9143f06b5f82efc7abd1b19 (patch) | |
| tree | 74cf1d6cf35ebc98ed759b34e89dbbfb931b72d3 | |
| parent | 57ce728f7db0c2b05d429471f94becf6302735c0 (diff) | |
| download | riscv-tests-trigger_priority.zip riscv-tests-trigger_priority.tar.gz riscv-tests-trigger_priority.tar.bz2 | |
Remove ineffective tests.trigger_priority
| -rw-r--r-- | isa/rv64mi/breakpoint.S | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/isa/rv64mi/breakpoint.S b/isa/rv64mi/breakpoint.S index 4cf51a4..c00ecae 100644 --- a/isa/rv64mi/breakpoint.S +++ b/isa/rv64mi/breakpoint.S @@ -130,7 +130,6 @@ RVTEST_CODE_BEGIN # Slow path because CSR was *just* written. (This is spike-specific.) sw x0, (a2) - beqz a2, fail # Normal aligned store, so that the next time we'll hit the fast path. li TESTNUM, 17 @@ -139,7 +138,6 @@ RVTEST_CODE_BEGIN # Fast path li TESTNUM, 18 sw x0, (a2) - beqz a2, fail 2: |