riscv-tests.git - Unnamed repository; edit this file 'description' to name the repository.

Branch	Commit message	Author	Age
ceasetest2	Check basic debugging still works in CeaseMulti	Tim Newsome	20 months
debug	Add debug statement.	Tim Newsome	4 years
debug_disassemble	debug: On failure, disassemble close instructions.	Tim Newsome	21 months
disable_unavailable	debug: Disable Unavailable tests.	Tim Newsome	8 months
master	README: add link to toolchain (#569)	Daniel Maslowski	2 weeks
misc	Make newer version of pylint happy.	Tim Newsome	5 years
python3	Move to Python 3.	Tim Newsome	5 years
riscv-tests-sail	removed the env/ directory, which was a submodule dir. replaced at a higher l...	William McSpaddden	7 weeks
tmp	tmp	Andrew Waterman	5 years
trigger_priority	Remove ineffective tests.	Tim Newsome	2 years
[...]


Age	Commit message	Author	Files	Lines
2017-05-25	Enable the RTOS when running tests on Spikertos	Palmer Dabbelt	1	-2/+2
2017-05-25	Merge pull request #53 from richardxia/fail-if-simulator-exits-early	Palmer Dabbelt	1	-0/+6
2017-05-23	Fail if simulator exits early.	Richard Xia	1	-0/+6
2017-05-22	minNum -> minimumNumber	Andrew Waterman	2	-4/+16
2017-05-18	Merge pull request #52 from riscv/vcs_sim_cmd	Megan Wachs	1	-1/+1
2017-05-18	debug: Correct the calling for a 32-bit simulation target	Megan Wachs	1	-1/+1
2017-05-17	Manually assemble bad shift amount, since assembler rejects	Andrew Waterman	1	-1/+1
2017-05-17	Shorten the debug tests	Palmer Dabbelt	1	-4/+4
2017-05-17	Merge pull request #49 from riscv/no_examine_target	Palmer Dabbelt	1	-1/+10
2017-05-17	Show the debug logs to stdout, to avoid travis timeouts	Palmer Dabbelt	1	-1/+1
[...]