riscv-tests.git - Unnamed repository; edit this file 'description' to name the repository.

Branch	Commit message	Author	Age
ceasetest2	Check basic debugging still works in CeaseMulti	Tim Newsome	20 months
debug	Add debug statement.	Tim Newsome	4 years
debug_disassemble	debug: On failure, disassemble close instructions.	Tim Newsome	21 months
disable_unavailable	debug: Disable Unavailable tests.	Tim Newsome	8 months
master	README: add link to toolchain (#569)	Daniel Maslowski	2 weeks
misc	Make newer version of pylint happy.	Tim Newsome	5 years
python3	Move to Python 3.	Tim Newsome	5 years
riscv-tests-sail	removed the env/ directory, which was a submodule dir. replaced at a higher l...	William McSpaddden	7 weeks
tmp	tmp	Andrew Waterman	5 years
trigger_priority	Remove ineffective tests.	Tim Newsome	2 years
[...]


Age	Commit message	Author	Files	Lines
2017-09-30	Resurrect priv tests.priv	Tim Newsome	1	-52/+51
2017-09-29	Make ExamineTarget multi-core aware.	Tim Newsome	1	-18/+23
2017-09-21	Add coverage for single-core non-rtos OpenOCD.	Tim Newsome	4	-3/+19
2017-09-19	Allow multiple reset vectors.	Tim Newsome	4	-3/+8
2017-09-19	Link against libm for fma()	Andrew Waterman	1	-1/+1
2017-09-19	Merge pull request #76 from riscv/multicore	Tim Newsome	3	-14/+28
2017-09-19	Forgot to commit this earlier.	Tim Newsome	1	-0/+20
2017-09-18	Add interrupts to MulticoreRunHaltStepiTest.	Tim Newsome	4	-16/+29
2017-09-15	Don't read entire log into RAM just to print it.	Tim Newsome	1	-2/+1
2017-09-14	misa is stored in the hart now, not the target	Tim Newsome	1	-6/+6
[...]