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BranchCommit messageAuthorAge
arrv-sc-arrv-sc/snippy-testsci: add testing with llvm-snippyAlexander Romanov5 months
dts_parsingSupport parsing procs fully from DTSJerry Zhao20 months
fetchSpeed up I$ refillAndrew Waterman12 days
fix-2206Don't write vstart in set_vlAndrew Waterman104 min.
masterMerge pull request #2239 from riscv-software-src/fix-2238Andrew Waterman25 hours
nolibfdtRemove in-tree libfdt, rely on system-installed libfdtJerry Zhao2 years
sanitizeseparate TLBsAndrew Waterman13 months
speed2Split off opcode_cache_entry_tJerry Zhao16 months
tmptmpAndrew Waterman3 months
zvmmImplement Zvbdot draftAndrew Waterman7 months
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TagDownloadAuthorAge
dummy-tag-for-ci-storageriscv-isa-sim-dummy-tag-for-ci-storage.zip  riscv-isa-sim-dummy-tag-for-ci-storage.tar.gz  riscv-isa-sim-dummy-tag-for-ci-storage.tar.bz2  Andrew Waterman3 years
v1.1.0riscv-isa-sim-1.1.0.zip  riscv-isa-sim-1.1.0.tar.gz  riscv-isa-sim-1.1.0.tar.bz2  Andrew Waterman4 years
v1.0.0riscv-isa-sim-1.0.0.zip  riscv-isa-sim-1.0.0.tar.gz  riscv-isa-sim-1.0.0.tar.bz2  Andrew Waterman7 years
 
AgeCommit messageAuthorFilesLines
12 daysSpeed up I$ refillfetchAndrew Waterman3-14/+36
2026-02-04Merge pull request #2227 from riscv-software-src/fix-2221Andrew Waterman1-4/+4
2026-02-04Raise correct trap in U-mode on indirect CSRs when !mstateen.csrindAndrew Waterman1-4/+4
2026-01-27Merge pull request #2221 from DymShanks/fix/vu-mode-siregAndrew Waterman1-0/+4
2026-01-26Fix: Enforce virtual_instruction trap for VU-mode indirect CSR accessDymShanks1-0/+4
2026-01-25Merge pull request #2223 from riscv-software-src/fix-depsAndrew Waterman5-423/+384
2026-01-25Have Zabha imply extensions rather than erroring if not presentAndrew Waterman1-12/+3
2026-01-25Have ZC* imply extensions rather than erroring if not presentAndrew Waterman1-5/+5
2026-01-25Have Zvfofp4min imply extensions rather than erroring if not presentAndrew Waterman1-8/+2
2026-01-25Clean up handling of ZcfAndrew Waterman2-12/+10
[...]