index
:
riscv-isa-sim.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
force-rtti
fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
no_progbuf
no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speedup-hacks
static-link
test
tmp
trigger_priority
tweak_debug_rom
whole-archive
sifive/rvv0.9-phase2
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2023-01-11
For NS16550 UART, poll stdin less often
tmp
Andrew Waterman
2
-1
/
+12
2023-01-11
Run Spike and HTIF in a single thread, rather than two
Andrew Waterman
2
-31
/
+14
2023-01-11
Merge pull request #1212 from riscv-software-src/debug_smoke
Andrew Waterman
4
-11
/
+84
2023-01-11
Automatically test that external debug still works.
Tim Newsome
1
-0
/
+64
2023-01-11
Use nproc or hw.ncpu instead of -j4 to build spike.
Tim Newsome
1
-1
/
+1
2023-01-11
Refactor build-spike out of test-spike.
Tim Newsome
3
-11
/
+20
2023-01-11
Merge pull request #1223 from riscv-software-src/readme
Andrew Waterman
1
-1
/
+2
2023-01-11
Fix supported debug version, use extension names
Tim Newsome
1
-1
/
+2
2023-01-10
Merge branch 'aap-sc-aap-sc/mem_cfg_corner_cases'
Andrew Waterman
4
-16
/
+53
2023-01-10
improve merge_mem_regions to handle memory region covering the whole 64-bit a...
Parshintsev Anatoly
1
-0
/
+24
2023-01-10
change mem_cfg_t to accept cases when (base + size) is at 64-bit address spac...
Parshintsev Anatoly
1
-1
/
+5
2023-01-09
simplify check_mem_overlap by utilizing get_inclusive_end of mem_cfg_t
Parshintsev Anatoly
1
-4
/
+1
2023-01-09
simplify merge_mem_regions by utilizing get_inclusive_end() of mem_cfg_t
Parshintsev Anatoly
1
-3
/
+3
2023-01-09
get_inclusive_end implementation for mem_cfg_t
Parshintsev Anatoly
2
-3
/
+6
2023-01-09
implement get_size() getter for mem_cfg_t object
Parshintsev Anatoly
3
-8
/
+13
2023-01-09
implement get_base() getter for mem_cfg_t object
Parshintsev Anatoly
3
-11
/
+15
2023-01-05
Merge pull request #1211 from riscv-software-src/speed-up-slow-path
Andrew Waterman
1
-2
/
+3
2023-01-05
Remove vestigial UNUSED annotation
Andrew Waterman
1
-1
/
+1
2023-01-05
Only update histogram when histogramming
Andrew Waterman
1
-1
/
+2
2023-01-04
Merge pull request #1210 from riscv-software-src/dynamic-dirty-enable
Andrew Waterman
9
-67
/
+46
2023-01-04
Remove --enable-dirty compile option
Jerry Zhao
3
-24
/
+0
2023-01-04
Respect --mmu-dirty flag instead of --enable-dirty
Jerry Zhao
2
-24
/
+19
2023-01-04
Add --mmu-dirty runtime flag
Jerry Zhao
1
-0
/
+2
2023-01-04
Add cfg_t field to enable PTE dirtying
Jerry Zhao
4
-0
/
+6
2023-01-04
Untabify ci-tests/testlib.c
Jerry Zhao
1
-19
/
+19
2023-01-04
Merge pull request #1209 from riscv-software-src/debugfix
Jerry Zhao
2
-5
/
+9
2023-01-04
Merge pull request #1207 from YenHaoChen/pr-trap-trigger-common
Scott Johnson
2
-33
/
+34
2023-01-03
Fix debug-mode regression introduced by 20e7f53
Jerry Zhao
2
-5
/
+9
2023-01-03
Merge pull request #1206 from riscv-software-src/always_misaligned
Andrew Waterman
12
-53
/
+42
2023-01-04
triggers: refactor: move mode_match() and textra_match() to private for prote...
YenHaoChen
1
-2
/
+2
2023-01-04
triggers: refactor: create trigger_t::common_match()
YenHaoChen
2
-3
/
+7
2023-01-04
triggers: refactor: move textra_match() to protected from public
YenHaoChen
1
-1
/
+1
2023-01-04
triggers: refactor: move textra_match() into detect_trap_match::detect_trap_m...
YenHaoChen
1
-2
/
+2
2023-01-04
triggers: refactor: move textra_match() into mcontrol_common_t::detect_memory...
YenHaoChen
1
-2
/
+3
2023-01-04
triggers: refactor: move detect_trap_match() to trap_common_t from itrigger_t...
YenHaoChen
2
-21
/
+3
2023-01-04
triggers: refactor: create virtual function trap_common_t::simple_match()
YenHaoChen
1
-2
/
+5
2023-01-04
triggers: refactor: move get_action() to trap_common_t from itrigger_t/etrigg...
YenHaoChen
1
-4
/
+1
2023-01-04
triggers: refactor: move get_dmode() to trap_common_t from itrigger_t/etrigger_t
YenHaoChen
1
-2
/
+3
2023-01-04
triggers: refactor: move action variable to trap_common_t from itrigger_t/etr...
YenHaoChen
1
-2
/
+1
2023-01-04
triggers: refactor: move hit variable to trap_common_t from itrigger_t/etrigg...
YenHaoChen
1
-2
/
+1
2023-01-04
triggers: refactor: move dmode variable to trap_common_t from itrigger_t/etri...
YenHaoChen
1
-2
/
+2
2023-01-04
triggers: refactor: add empty parent trap_common_t class for itrigger_t and e...
YenHaoChen
1
-2
/
+5
2023-01-03
Delete --enable-misaligned configure option
Andrew Waterman
3
-24
/
+0
2023-01-03
Respect --[no-]misaligned command-line flag
Andrew Waterman
2
-19
/
+13
2023-01-03
Add --[no-]misaligned command-line options
Andrew Waterman
4
-0
/
+8
2023-01-03
Pass cfg object to processor_t constructor
Andrew Waterman
4
-10
/
+21
2023-01-03
Merge pull request #1203 from riscv-software-src/misa-c-read-only
Andrew Waterman
2
-7
/
+3
2023-01-03
Merge pull request #1200 from riscv-software-src/mmio_pte
Andrew Waterman
2
-18
/
+54
2023-01-04
triggers: refactor: add bool etrigger_t::simple_match()
YenHaoChen
2
-1
/
+7
2023-01-04
triggers: refactor: add bool itrigger_t::simple_match()
YenHaoChen
2
-1
/
+7
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