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author | Jerry Zhao <jerryz123@berkeley.edu> | 2024-11-05 12:54:02 -0800 |
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committer | Jerry Zhao <jerryz123@berkeley.edu> | 2024-11-05 12:54:02 -0800 |
commit | 9fd52a71135cacde9ca1178637ca730cfd48e019 (patch) | |
tree | 76fb32b7be4bb98a70dda781bd547e8521a2175d | |
parent | d56f15e727b4bc8910651e647a96bef9804b5d5e (diff) | |
download | riscv-isa-sim-speed2.zip riscv-isa-sim-speed2.tar.gz riscv-isa-sim-speed2.tar.bz2 |
Split off opcode_cache_entry_tspeed2
-rw-r--r-- | riscv/processor.h | 23 |
1 files changed, 13 insertions, 10 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 3f8becc..bebeb47 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -204,6 +204,11 @@ struct state_t void csr_init(processor_t* const proc, reg_t max_isa); }; +struct opcode_cache_entry_t { + insn_bits_t bits; + const insn_desc_t* desc; +}; + class opcode_cache_set_t { public: opcode_cache_set_t() @@ -214,35 +219,33 @@ class opcode_cache_set_t { void reset() { for (size_t i = 0; i < associativity; i++) { - bits[i] = 0; - descs[i] = &insn_desc_t::illegal_instruction; + entries[i].bits = 0; + entries[i].desc = &insn_desc_t::illegal_instruction; } } void replace(insn_bits_t opcode, const insn_desc_t* desc) { for (size_t i = associativity - 1; i > 0; i--) { - bits[i] = bits[i-1]; - descs[i] = descs[i-1]; + entries[i] = entries[i-1]; } - bits[0] = opcode; - descs[0] = desc; + entries[0].bits = opcode; + entries[0].desc = desc; } std::tuple<bool, const insn_desc_t*> lookup(insn_bits_t opcode) { for (size_t i = 0; i < associativity; i++) - if (bits[i] == opcode) - return std::tuple(true, descs[i]); + if (entries[i].bits == opcode) + return std::tuple(true, entries[i].desc); return std::tuple(false, nullptr); } private: static const size_t associativity = 4; - insn_bits_t bits[associativity]; - const insn_desc_t* descs[associativity]; + opcode_cache_entry_t entries[associativity]; }; // this class represents one processor in a RISC-V machine. |