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Age	Commit message (Collapse)	Author	Files	Lines
2023-11-14	platform: generic: thead: separate implement of T-HEAD c9xx errata	Inochi Amaoto	1	-1/+3
	Separate the implement of T-HEAD c9xx errata to allow any platform with bug related to c9xx cores can use it. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-11-14	platform: generic: thead: separate implement of T-HEAD c9xx pmu	Inochi Amaoto	1	-0/+2
	Separate the implement of T-HEAD c9xx pmu to allow any platform with c9xx cores can use it. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-10-04	platform: generic: thead: fix stale TLB entries for th1520/sg2042	Inochi Amaoto	1	-0/+10
	The TLB entries remain functional all the time once added in T-HEAD th1520 and Sophgo sg2042 (even if the MMU is then disabled afterwards). If there are some stale TLB entries that contains the address of SBI, it will cause unexpected memory access and issue a illegal instruction error. To avoid this, a TLB flush is needed to drop these TLB entries before any memory access in the trap handler. To handle this workaroud, add a custom trap handler with executing TLB flush first in the T-HEAD platform to fix affected socs. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Reviewed-by: Anup Patel <anup@brainfault.org>