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6 daysplatform: generic: eyeq7h: enable ECC on L1 cacheHEADmasterVladimir Kondratiev1-0/+2
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-23-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: p8700: fix MIPS specific CSRsVladimir Kondratiev1-4/+20
P8700 has MIPS specific CSRs. Fix the list, adding few missing ones and remove few non-existing Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-22-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips eyeq7h: prohibit accessing memory beyond DRAMVladimir Kondratiev1-1/+36
SBI code arranges domain PMP regions in a way that last entry is all-inclusive "0..~0 RWX" and the rest of entries are not programmed. This causes a problem for the eyeq7h. CPU can issue speculative prefetches to non-existent addresses. If this access goes to the system NOC, it is mis-interpreted as an access violation and error is reported, forcing system reset. To prevent such a speculative transaction to leave a CPU cluster, block it using PMP, by restricting memory region to physically present memory. To achieve this, on early init: - update flags for the last all-inclusive "0..~0 RWX" entry to be inaccessible MMIO. MMIO serves to set up PMA attributes to uncached non-prefetchable, preventing transactions to reach system NOC - add an all-permissive entry matching DRAM. Resulting memory regions: Domain0 Region00 : 0x0000000800100000-0x000000080013ffff M: (F,R,X) S/U: () Domain0 Region01 : 0x0000000800100000-0x00000008001fffff M: (F,R,W) S/U: () Domain0 Region02 : 0x0000000048700000-0x000000004870ffff M: (I,R,W) S/U: () Domain0 Region03 : 0x0000000067480000-0x000000006748ffff M: (I,R,W) S/U: () Domain0 Region04 : 0x0000000067500000-0x000000006750ffff M: (I,R,W) S/U: () Domain0 Region05 : 0x0000000048740000-0x000000004875ffff M: (I,R,W) S/U: () Domain0 Region06 : 0x00000000674c0000-0x00000000674dffff M: (I,R,W) S/U: () Domain0 Region07 : 0x0000000067540000-0x000000006755ffff M: (I,R,W) S/U: () Domain0 Region08 : 0x0000000000000000-0x000000007fffffff M: (I,R,W) S/U: (R,W) Domain0 Region09 : 0x0000000800000000-0x00000008ffffffff M: () S/U: (R,W,X) Domain0 Region10 : 0x0000001000000000-0x0000001fffffffff M: (I) S/U: (R,W) Domain0 Region11 : 0x0000000000000000-0xffffffffffffffff M: (I) S/U: () Here Region09 covers DRAM, region 11 set to non-accessible uncached no-prefetch for the entire address range Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-21-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips p8700: dump MMIO regionsVladimir Kondratiev3-0/+65
Debug print MMIO regions Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-20-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips eyeq7h: fix NCORE registers access from clusters 1..2Vladimir Kondratiev2-0/+25
CPU clusters 1 and 2 cannot access NCORE registers through AUX ports. AUX ports of clusters 1 and 2 are connected to NCORE through east port. East port has no access to NCORE registers address space. Re-route NCORE registers range to MEM port by re-configuring MMIO regions in the GCR. REsulting map is as below. Mind a gap between regions [1] and [2]; this gap covering NCORE registers now routed to the default MEM port Cluster 0: 4 MMIO regions [0] : 0x0000000000000000-0x000000001fff0000 AUX0 UC|UCA [1] : 0x0000000020000000-0x00000000677f0000 AUX0 ANY [2] : 0x0000000080000000-0x0000001fffff0000 AUX0 UC|UCA [3] : --disabled-- Cluster 1: 4 MMIO regions [0] : 0x0000000000000000-0x000000001fff0000 AUX0 UC|UCA [1] : 0x0000000020000000-0x00000000677f0000 AUX0 ANY [2] : 0x0000000080000000-0x0000001fffff0000 AUX0 UC|UCA [3] : --disabled-- Cluster 2: 4 MMIO regions [0] : 0x0000000000000000-0x000000001fff0000 AUX0 UC|UCA [1] : 0x0000000020000000-0x00000000677f0000 AUX0 ANY [2] : 0x0000000080000000-0x0000001fffff0000 AUX0 UC|UCA [3] : --disabled-- Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-19-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips eyeq7h: synchronize timers across clustersVladimir Kondratiev3-0/+23
Use eyeq7 specific method to synchronously restart architectural mtimer and eyeq7h specific high-resolution timer with common hardware trigger. This ensures all timers are precisely in sync Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-18-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips p8700: synchronize hi-res timersVladimir Kondratiev3-1/+19
There's high-resolution (1GHz) timer found in the p8700 cluster. This timer used for precise time measurement by platform specific software. Synchronize this proprietary timers to reference in cluster 0. Procedure borrowed from the aclint mtimer. Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-17-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips p8700: use SBI bitfield manipulator macrosVladimir Kondratiev3-34/+21
Switch to GENMASK, EXTRACT_BITFIELD, INSERT_BITFIELD Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-16-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips p8700: CPU clusters memrangesVladimir Kondratiev4-44/+59
Reserve memory regions for CPU clusters according to P8700 cluster memory layout. There's a set of components in the CPU cluster according to [1] [1] https://mips.com/wp-content/uploads/2025/11/P8700-F_Programmers_Reference_Manual-TM.pdf Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-15-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips p8700: cache geometry detectionVladimir Kondratiev3-0/+126
P8700 has a read-only cache configuration registers. Provide a CPU specific function to extract cache information. Use this information in the eyeq7h board for informational message Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-14-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips eyeq7h: deassert accelerator cluster resetsVladimir Kondratiev1-0/+16
On the EyeQ7H board, there's cluster level resets found in the accelerator OLBs. These resets should be deasserted once on boot and never used after Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-13-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips eyeq7h: detect accelerators cluster presenceVladimir Kondratiev1-0/+44
In the design, accelerator clusters ACC[01] and XNN[01] presence indicated by the OLB_WEST register OLB_WEST_TSTCSR. In the simulation environments, part (or all) accelerators may be not instantiated Disable clusters not present in the model, updating the DTB Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-12-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips eyeq7h: power up clusters with OLBVladimir Kondratiev1-0/+42
In the eyeq7h platform, there's extra power control for the CPU clusters. To enable cluster, it should be powered up using this OLB registers prior to accessing any cluster management registers Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-11-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips: add P8700 based "eyeq7h" and "boston"Vladimir Kondratiev8-226/+523
Refactor MIPS P8700 support, convert P8700 into a "CPU" and add 2 platforms using this CPU: - "boston" - FPGA platform developed by MIPS - "eyeq7h" - automotive platform by Mobileye Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-10-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips p8700: access CM registers via match dataVladimir Kondratiev3-33/+19
Modify the coherence manager register accessors to use the global variable p8700_cm_info instead of the statically declared GLOBAL_CM_BASE array. Also use p8700_cm_info to get the number of coherence managers and their base addresses in mips_p8700_early_init() and mips_p8700_nascent_init(). Clean up the hard-coded values in mips/board.h, access to the coherence manager is now fully based on information provided by platform compatible from the device tree. Signed-off-by: Benoît Monin <benoit.monin@bootlin.com> Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-9-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips p8700: Add match data for CM infoBenoît Monin2-1/+32
Introduce a structure p8700_cm_info holding the number of coherence managers and their base addresses found in a particular SoC. Declare a global pointer to the structure that is set in mips_p8700_platform_init(), based on the match data of the platform compatible. For the match data of the MIPS P8700, a single coherence manager with a base address of 0x16100000 is declared, identical to what is found in mips/board.h. For now, access to the coherence manager register is still based on the hard-coded values defined in mips/board.h. Signed-off-by: Benoît Monin <benoit.monin@bootlin.com> Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-8-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips p8700: use global CM addressesVladimir Kondratiev3-64/+45
In the multi-cluster system each cluster has its own CM (Coherency Manager). Every CM has its "global" memory address where it is accessible from any bus master. Initially, all CMs accessible from the local cluster using same "local" address. Transactions by local address are not routed through system bus and thus are faster. Remap CM in every cluster to the local address matching its global address. Then, every CM is always accessed using same address, but when transaction initiated from the local cluster it is routed internally. This removes need for 2 PMP regions covering local address access. CM accessor functions simplified because there's no need to detect whether transaction is local or global Access timer always in cluster 0 Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-7-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips p8700: faster core bootVladimir Kondratiev1-23/+30
When powering up cores, wait for power up to complete using tight loop. This saves 10ms delay observed for every core Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-6-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips p8700: fix powering up other clusterVladimir Kondratiev1-19/+10
While powering up cluster, only indication is bit in cluster power control. It used to wait for CORE0 in that cluster reach U5 state (non-coherent execution), this won't happen when only CM powered up without booting any core Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-5-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips p8700: reserve memory for M-mode peripheralsVladimir Kondratiev1-37/+60
Reserve memory upfront in large well aligned chunks, to avoid problem with PMP granularity that is 64Kbytes for the p8700 CPU Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-4-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips p8700: improve CM access tracingVladimir Kondratiev1-2/+4
use function call like format; debug print returning value of the "read" accessor Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-3-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
11 dayslib: utils/serial: Add support for Altera JTAG UARTIcenowy Zheng1-0/+1
Altera provides a JTAG UART core that provides virtual UART over JTAG and can coexist with their virtual JTAG. [1] This core has already been supported by Linux and the programming interface has always been stable. Add support for it to OpenSBI to ease JTAG prototype bringing up. The driver follows the device tree binding in mainline Linux. [2] [1] https://docs.altera.com/r/docs/683130/25.3/embedded-peripherals-ip-user-guide/jtag-uart-core [2] https://github.com/torvalds/linux/blob/v6.19-rc1/Documentation/devicetree/bindings/serial/altr%2Cjuart-1.0.yaml Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260104065506.70182-1-zhengxingda@iscas.ac.cn Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-11lib: utils/suspend: add Andes ATCSMU suspend driverBen Zong-You Xie2-2/+9
Implement a system-wide suspend driver for the Andes AE350 platform. This driver supports Andes-specific deep sleep (suspend to RAM) and light sleep (suspend to standby) functionalities via the ATCSMU. The major differences between deep sleep and light sleep are: - Power Domain and Resume Path: Deep sleep powers down the core domain. Consequently, harts waking from deep sleep resume from the reset vector. Light sleep utilizes clock gating to the core domain; harts maintain state and resume execution at the instruction immediately following the WFI instruction. - Primary Hart Wakeup: In both modes, the primary hart is woken by UART or RTC alarm interrupts. In deep sleep, the primary hart is additionally responsible for re-enabling the Last Level Cache (LLC) and restoring Andes-specific CSRs. - Secondary Hart Wakeup: In light sleep, secondary harts are woken by an IPI sent from the primary hart. In deep sleep, they are woken by an ATCSMU hardware wake-up command. Furthermore, secondary harts must restore Andes-specific CSRs when returning from deep sleep. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-6-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-11lib: utils/cache: add Andes last level cache controllerBen Zong-You Xie1-0/+1
Introduce a FDT-based driver for the Andes Last Level Cache (LLC) controller to support cache maintenance operations. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-5-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-11platform: generic/andes: add CSR save and restore functions for AE350 platformBen Zong-You Xie2-1/+76
Implement a save and restore mechanism for Andes-specific CSRs to support hardware power-saving modes, such as CPU hotplug or suspend to RAM. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-3-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-11lib: utils/hsm: factor out ATCSMU code into an HSM driverBen Zong-You Xie6-176/+72
Refactor ATCSMU (System Management Unit) support by moving it from a system utility into a dedicated FDT-based HSM driver. Key changes include: - Moving the functions in lib/utils/sys/atcsmu.c into the new HSM driver - Moving hart start and stop operations on AE350 platform into the new HSM driver - Converting the assembly-based functions in sleep.S to C code for the readability - Updating the ATCWDT200 driver Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-2-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-21platform: generic: eswin: Add shutdown/reboot support for Hifive Premier P550Bo Gan5-0/+207
Hifive Premier P550[1] is a Mini-DTX form factor board with EIC7700X. It has a STM32F407VET6 onboard MCU acting as the BMC, controlling ATX power on/off while providing remote management features. The EIC7700X SoC/SoM communicates with the BMC via UART2, using ESWIN's protocol. The messages transmitted are fixed sizes (267 bytes), and depending on the type, can be directional or bi-directional. The shutdown and cold reboot requests are directional messages from SoC to BMC (NOTIFY type) with CMD_POWER_OFF or CMD_RESTART. The payload of shutdown/cold reboot requests should be empty and are ignored by the BMC at the moment. A HFP (Hifive Premier) specific reset device is registered in addition to the SoC reset device. For shutdown and cold reboot, the board-level reset takes precedence. The definitions of the SoC <-> BMC message protocol is taken from ESWIN's repo [2]. The only file used from that repo is `hf_common.h` It's disjunctively dual licensed as (GPL-2.0-only OR BSD-2-Clause), hence, compatible with the license of OpenSBI. It's heavily modified and renamed as platform/generic/include/eswin/hfp.h. The author and copyright in the original file are retained. Validated shutdown/cold reboot working on Hifive Premier P550. [1] https://www.sifive.com/boards/hifive-premier-p550#documentation [2] https://github.com/eswincomputing/hifive-premier-p550-mcu-patches.git Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251218104243.562667-8-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-21platform: generic: eswin: add EIC7700Bo Gan6-0/+527
Initial platform support for ESWIN Computing EIC7700 based on public SoC datasheet[1] and tested on HiFive Premier P550. Vendor U-boot/Linux boots fine, and I've tested Geekbench 6.5.0 Preview and got scores on par with the vendor OpenSBI. System shutdown/reboot for HiFive Premier P550 and other boards will be implemented in subsequent commits. At this point, only SoC-level warm reset is implemented. The files and functions are intentionally named as eic770x in many places for future enhancements to support the 2 die version of the same SoC, namely EIC7702, seen on DC-ROMA AI PC FML13V03 [2]. This patch set only deals with the single die version, and the assumption is we can be either die with id=0 or id=1, but there's only a single die in the system, or we are only using a single die out of 2. However, the way the SoC handles 2- die greatly affects how we configure it in a 1-die setup. EIC770X address map has die 0/1 memory regions interleaved (see comments in eic770x.c). If only 1 die is connected or active, it creates holes in the address map for those regions corresponding to the remote die. When speculative- execution or HW prefetcher touches data-cacheable regions that happen to fall into those holes, it can trigger bus error. Specifically: - Remote (non-existent) die L3 zero device - Remote (non-existent) die cached memory region - Other holes in Memory Port To make matters worse, EIC770X doesn't have cache coherent DMA, and due to the fact that the P550 core lacks Svpbmt, the SoC maps main memory twice as different regions, so it can bypass cache and fetch the data directly from memory. In address space, we have two memory regions, one as cached, the other as uncached. Thus, we also need an extra PMP entry to protect OpenSBI blob from the uncached window. To do this, platform code requires single_fw_region, otherwise, we'll run out of PMP entries. EIC770X also have several feature disable/enable CSRs accessible in M mode. By default many core features such as speculation and HW prefetch are disabled, and M mode software is responsible of enabling. Hence, introduce 4 new build time tunable parameters to Kconfig, which reflects the values get updated to those CSRs: - ESWIN_EIC770X_FEAT0_CFG - ESWIN_EIC770X_FEAT1_CFG - ESWIN_EIC770X_L1_HWPF_CFG - ESWIN_EIC770X_L2_HWPF_CFG The default values are somewhat optimal for generic workloads. They are dumped when running SiFive's vendor OpenSBI, and in addition, with my own tuning to address the perf regression reported by drmpeg [3] To build the firmware+u-boot blob, Use the following, and docs [4] for testing it with UART boot without flashing: make FW_TEXT_START=0x80000000 \ FW_PAYLOAD_OFFSET=0x200000 \ FW_PAYLOAD_PATH=u-boot-nodtb.bin \ FW_PAYLOAD_FDT_ADDR=0xf8000000 \ FW_FDT_PATH=u-boot.dtb [1] https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual [2] https://github.com/geerlingguy/sbc-reviews/issues/82 [3] https://forums.sifive.com/t/low-1-core-stream-bandwidth/7274/15 [4] https://github.com/ganboing/EIC770x-Docs/blob/main/p550/bootchain/UART-Boot.md Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251218104243.562667-6-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-16platform: generic: Keep some empty space in FDT passed to next stageAnup Patel2-0/+8
Leaving no empty space in the FDT passed to the next booting stage causes the following U-Boot crash on Ventana internal platforms: Unhandled exception: Load access fault EPC: 00000000fffa6372 RA: 00000000fffa7418 TVAL: 0001746174730068 EPC: 0000000080245372 RA: 0000000080246418 reloc adjusted SP: 00000000fef38440 GP: 00000000fef40e60 TP: 0000000000000000 T0: 00000000fef40a70 T1: 000000000000ff00 T2: 0000000000000000 S0: 00000000fffc17a8 S1: 00000000fef38d40 A0: 7375746174730068 A1: 00000000fffc17a8 A2: 0000000000000010 A3: 0000000000000010 A4: 0000000000000000 A5: 00000000fffc17b8 A6: 0000000000ff0000 A7: 000000000000b100 S2: 0000000000000000 S3: 0000000000000001 S4: 00000000fef38d40 S5: 7375746174730068 S6: 0000000000000000 S7: 00000000fef4eef0 S8: 00000000fef4ef90 S9: 0000000000000000 S10: 0000000000000000 S11: 00000000fef4efc0 T3: 00000000fef40ea8 T4: 0000000000ff0000 T5: 00000000fef40a60 T6: 00000000fef40a6c To address the above issue, keep some minimal empty space in the FDT instead of no empty space. Fixes: bbe9a23060e9 ("platform: generic: Pack the FDT after applying fixups") Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20251209053130.407935-1-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-08platform: generic: spacemit: add missing objects.mkJunhui Liu2-2/+8
Add the missing objects.mk for the SpacemiT platform, required for the K1 platform to be included in the build. Fixes: 1f84ec2a ("platform: generic: spacemit: add K1") Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Acked-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Link: https://lore.kernel.org/r/20251124-k1-fix-v1-1-8d7e7a29379e@pigmoral.tech Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-08lib: utils/cache: Add SiFive Extensible Cache (EC) driverNick Hu1-0/+1
Add support for SiFive Extensible Cache (EC) controller with multi-slice architecture. The driver implements cache maintenance operations through MMIO register interface. Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Co-developed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Co-developed-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-3-8423a721924c@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-08lib: utils/cache: Add SiFive PL2 controllerNick Hu1-0/+1
SiFive Private L2(PL2) cache is a private cache owned by each hart. Add this driver to support private cache flush operations via the MMIO registers. Co-developed-by: Eric Lin <eric.lin@sifive.com> Signed-off-by: Eric Lin <eric.lin@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Co-developed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-2-8423a721924c@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-01platform: openpiton: use generic early initManuel Hernández Méndez1-22/+3
Add code for using generic_early_init so that the uart parameters are parsed from dtb. Signed-off-by: Manuel Hernández Méndez <manuel.hernandez@openchip.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251107075429.1382-1-manuel.hernandez@openchip.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-01platform: ariane: parse dtb for getting some initial parametersManuel Hernández Méndez1-15/+24
Add code for getting some uart, clint and plic parameters from device tree. Signed-off-by: Manuel Hernández Méndez <manuel.hernandez@openchip.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251107075412.1350-1-manuel.hernandez@openchip.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-05platform: ariane: Move ariane platform from fpga to genericManuel Hernández Méndez4-0/+145
The Ariane framework has a generic PMU that is not used by OpenSBI. Due to OpenSBI’s build system we cannot directly reuse the generic platform functions, so move the Ariane platform to generic. Also due to the generic platform is where new features are added. Signed-off-by: Manuel Hernández Méndez <maherme.dev@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251023090347.30746-1-maherme.dev@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-04lib: utils: Add MPXY RPMI mailbox driver for performanceJoshua Yeong1-0/+1
Add MPXY RPMI mailbox driver for performance. Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com> Reviewed-by: Rahul Pathak <rpathak@ventanamicro.com> Link: https://lore.kernel.org/r/20251013153138.1574512-4-joshua.yeong@starfivetech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-04lib: utils: Add MPXY RPMI mailbox driver for device powerJoshua Yeong1-0/+1
Add MPXY RPMI mailbox driver for device power. Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com> Reviewed-by: Rahul Pathak <rpathak@ventanamicro.com> Link: https://lore.kernel.org/r/20251013153138.1574512-3-joshua.yeong@starfivetech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-04lib: utils: Add MPXY RPMI mailbox driver for voltageJoshua Yeong1-0/+1
Add voltage service group for RPMI/MPXY support Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com> Reviewed-by: Rahul Pathak <rpathak@ventanamicro.com> Link: https://lore.kernel.org/r/20251013153138.1574512-2-joshua.yeong@starfivetech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils/suspend: Add SiFive SMC0 driverNick Hu1-0/+1
The SiFive SMC0 controls the clock and power domain of the core complex on the SiFive platform. The core complex enters the low power state after the secondary cores enter the tile power gating and last core execute the `CEASE` instruction with the corresponding SMC0 configurations. The devices that inside both tile power domain and core complex power domain will be off, including caches and timer. Therefore we need to flush the last level cache before entering the core complex power gating and update the timer after waking up. Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-12-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils/hsm: Add SiFive TMC0 driverNick Hu1-0/+1
The SiFive TMC0 controls the tile power domains on SiFive platform. The CPU enters the low power state via the `CEASE` instruction after configuring the TMC0. Any devices that inside the tile power domain will be power gated, including the private cache. Therefore flushing the private cache before entering the low power state. Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-9-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: sbi: Extends sbi_ipi_raw_send() to use all available IPI devicesNick Hu1-1/+1
A platform may contain multiple IPI devices. In certain use cases, such as power management, it may be necessary to send an IPI through a specific device to wake up a CPU. For example, if an IMSIC is powered down and reset, the core cannot receive IPIs from it, so the wake-up must instead be triggered through the CLINT. Suggested-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-8-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils/cache: Add fdt cmo helpersNick Hu1-1/+2
Add the helpers to build up the cache hierarchy via FDT and provide some cmo functions for the user who want to flush the entire cache. Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-4-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28utils: cache: Add SiFive ccache controllerVincent Chen1-0/+1
SiFive Composable cache is a L3 share cache of the core complex. Add this driver to support the share cache maintenance operations via the MMIO registers. Co-developed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Co-developed-by: Nick Hu <nick.hu@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-3-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils: Add FDT cache libraryNick Hu1-0/+1
Add the FDT cache library so we can build up the cache topology via the 'next-level-cache' DT property. Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Co-developed-by: Andy Chiu <andy.chiu@sifive.com> Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-2-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-21lib: Allow custom CSRs in csr_read_num() and csr_write_num()Anup Patel2-155/+11
Some of the platforms use platform specific CSR access functions for configuring implementation specific CSRs (such as PMA registers). Extend the common csr_read_num() and csr_write_num() to allow custom CSRs so that platform specific CSR access functions are not needed. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20250930153216.89853-1-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-20platform: generic: Add SpacemiT K1 platform supportXianbin Zhu1-2/+3
Enable CONFIG_PLATFORM_SPACEMIT_K1 in the defconfig for SpacemiT K1 SoC. Co-authored-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Xianbin Zhu <xianbin.zhu@linux.spacemit.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250925-smt-k1-8-cores-v3-3-0885a8a70f8e@linux.spacemit.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-20platform: spacemit: Add HSM driverXianbin Zhu1-0/+1
Add code to bring up all 8 cores during OpenSBI initialization so that the Linux kernel can detect and use all cores properly. Co-authored-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Xianbin Zhu <xianbin.zhu@linux.spacemit.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250925-smt-k1-8-cores-v3-2-0885a8a70f8e@linux.spacemit.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-20platform: generic: spacemit: add K1Xianbin Zhu3-0/+215
Add initial platform support for the SpacemiT K1 SoC, including early/final init hooks, cold boot handling, and CCI-550 snoop/DVM enablement. Co-authored-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Xianbin Zhu <xianbin.zhu@linux.spacemit.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/all/15169E392597D319+aOcKujCl8mz4XK4L@kernel.org/ [1] Link: https://lore.kernel.org/r/20250925-smt-k1-8-cores-v3-1-0885a8a70f8e@linux.spacemit.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-30platform: starfive: jh7110: Add starfive,jh7110s compatibleHal Feng1-0/+1
Add support for VisionFive 2 Lite board. Link: https://github.com/hal-feng/opensbi/commit/b7e46979a4feb293070094835ba4058b5e55d707 Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250906053638.69671-1-heinrich.schuchardt@canonical.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-30platform: generic: Add Andes QiLai SoC supportBen Zong-You Xie6-0/+96
Extend generic platform to support Andes QiLai SoC. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250814104024.3374698-1-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
generated by cgit v1.1 at 2026-03-03 04:47:29 +0000