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5 dayslib: sbi_hsm: Use 64-bit CSR macro for menvcfgHEADmasterSamuel Holland1-16/+5
Simplify the code and remove preprocessor checks by treating menvcfg and menvcfgh together as one 64-bit value. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250908055646.2391370-3-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
5 dayslib: sbi_hart: Do not call delegate_traps() in the resume flowSamuel Holland1-4/+4
The only purpose of this function is to program the initial values of mideleg and medeleg. However, both of these CSRs are now saved/restored across non-retentive suspend, so the values from this function are always overwritten by the restored values. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250908055646.2391370-2-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
5 dayslib: sbi_hsm: Save mideleg across non-retentive suspendSamuel Holland1-0/+3
OpenSBI updates mideleg when registering or unregistering the PMU SSE event. The updated CSR value must be saved across non-retentive suspend, or PMU SSE events will not be delivered after the hart is resumed. Fixes: b31a0a24279d ("lib: sbi: pmu: Add SSE register/unregister() callbacks") Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250908055646.2391370-1-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
5 dayslib: utils/ipi: Convert IPI drivers as early driversAnup Patel7-63/+4
The fdt_ipi_init() is already called from generic_early_init() so let's convert IPI drivers as early drivers. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20250904052410.546818-4-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
5 daysinclude: sbi: Remove platform specific IPI initAnup Patel8-82/+49
The platform specfic IPI init is not need anymore because using IPI device rating multiple IPI devices can be registered in any order as part of the platform specific early init. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20250904052410.546818-3-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
5 dayslib: sbi: Introduce IPI device ratingAnup Patel6-14/+47
A platform can have multiple IPI devices (such as ACLINT MSWI, AIA IMSIC, etc). Currently, OpenSBI rely on platform calling the sbi_ipi_set_device() function in correct order and prefer the first avaiable IPI device which is fragile. Instead of the above, introduce IPI device rating and prefer the highest rated IPI device. This further allows extending the sbi_ipi_raw_clear() to clear all available IPI devices. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Tested-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20250904052410.546818-2-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
5 dayslib: utils/reset: Hang the hart after RPMI system reset messageRahul Pathak1-0/+3
RPMI system reset is a posted message which does not wait for acknowledgement after sending the RPMI message to PuC. Call the sbi_hart_hang() to hang the hart after performing the system reset via RPMI message. Fixes: 6a26726e08e4 ("lib/utils: reset: Add RPMI System Reset driver") Reported-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Link: https://lore.kernel.org/r/20250903144323.251270-1-rpathak@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-01lib: sbi_heap: Simplify allocation algorithmSamuel Holland1-32/+22
Now that the allocator cannot run out of nodes in the middle of an allocation, the code can be simplified greatly. First it moves bytes from the beginning and/or end of the node to new nodes in the free list as necessary. These new nodes are inserted into the free list in address order. Then it moves the original node to the used list. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Tested-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250617032306.1494528-4-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-01lib: sbi_heap: Allocate list nodes dynamicallySamuel Holland1-35/+48
Currently the heap has a fixed housekeeping factor of 16, which means 1/16 of the heap is reserved for list nodes. But this is not enough when there are many small allocations; in the worst case, 1/3 of the heap is needed for list nodes (32 byte heap_node for each 64 byte allocation). This has caused allocation failures on some platforms. Let's avoid trying to guess the best ratio. Instead, allocate more nodes as needed. To avoid recursion, the nodes are permanent allocations. So to minimize fragmentation, allocate them in small batches from the end of the last free space node. Bootstrap the free space list by embedding one node in the heap control struct. Some error paths are avoided because the nodes are allocated up front. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Tested-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250617032306.1494528-3-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-01lib: sbi_list: Add a helper for reverse list iterationSamuel Holland1-0/+11
Some use cases require iterating through a list in both directions. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Tested-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250617032306.1494528-2-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-08-28generic: mips: support harts to boot from mips_warm_bootChao-ying Fu3-1/+18
We program reset base for harts (other than hart 0) to boot at mips_warm_boot that jumps to _start_warm. This helps to skip some code sequence to speed up. Signed-off-by: Chao-ying Fu <cfu@mips.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250723204010.9927-1-cfu@mips.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-08-28dbtr: Fix sbi_dbtr_read_trig to read from CSRsJesse Taube1-0/+4
sbi_dbtr_read_trig returned the saved state of tdata{1-3}, when it should have returned the updated state read from CSRs. Update sbi_dbtr_read_trig to return updated state read from CSRs. Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Jesse Taube <jesse@rivosinc.com> Link: https://lore.kernel.org/r/20250811152947.851208-1-jesse@rivosinc.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-08-28dbtr: Add support for icount trigger typeJesse Taube2-0/+79
The linux kernel needs icount to implement hardware breakpoints. Signed-off-by: Jesse Taube <jesse@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250724183120.1822667-1-jesse@rivosinc.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-08-28Fix license to compatible BSD-2-ClauseXiang W5-5/+5
OpenSBI is a BSD project. We need to modify some codes to compatible with BSD-2-Clause license. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Ben Zong-You Xie <ben717@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250728074334.372355-1-wxjstz@126.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-08-28platform: generic: Pack the FDT after applying fixupsSamuel Holland1-0/+2
This minimizes the size that will be reserved by the OS for the FDT, and it prevents the FDT buffer from containing uninitialized memory, which can be important for some simulation platforms and for attestation. Closes: https://github.com/riscv-software-src/opensbi/issues/388 Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250722233923.1356605-1-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-08-26platform: openpiton: Move openpiton platform from fpga to genericManuel Hernández Méndez11-93/+44
The OpenPiton framework has a generic PMU that is not used by OpenSBI. Due to OpenSBI’s build system we cannot directly reuse the generic platform functions, so move the OpenPiton platform to generic. Also due to the generic platform is where new features are added. Signed-off-by: Manuel Hernández Méndez <maherme.dev@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250813104759.33276-1-maherme.dev@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-08-26lib: sbi: pmu: Improve loop in pmu_ctr_find_hwManuel Hernández Méndez1-0/+1
We do not need to iterate over all values in the loop, we can break the loop when we found a valid counter that is not started yet. Signed-off-by: Manuel Hernández Méndez <maherme.dev@gmail.com> Link: https://lore.kernel.org/r/20250721160712.8766-1-maherme.dev@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-07-23lib: utils: fdt: fix "ranges" translationMax Hsu1-11/+15
According to the Device Tree Spec, Chapter 2.3.8 "ranges" [1]: The parent address size will be determined from the #address-cells property of the node that defines the parent’s address space. In fdt_translate_address(), which considered the parent address size is the child address size, this commit fix the two address sizes and parsing the address independently. Signed-off-by: Max Hsu <max.hsu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250711-dev-maxh-master_fdt_helper-v2-1-9579e1f02ee1@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-07-22include: sbi: Remove unused (LOG_)REGBYTESJessica Clarke1-7/+0
These are no longer used, so remove them. Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250709232932.37622-3-jrtc27@jrtc27.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-07-22firmware: Replace sole uses of REGBYTES with __SIZEOF_LONG__Jessica Clarke1-3/+3
This code has nothing to do with the ISA's registers, it's about the format of ELF relocations. As such, __SIZEOF_LONG__, being a language / ABI-level property, is a more appropriate constant to use. This also makes it easier to support CHERI, where general-purpose registers are extended to be capabilities, not just integers, and so the register size is not the same as the machine word size. This also happens to make it more correct for RV64ILP32, where the registers are 64-bit integers but the ABI is 32-bit (both for long and for the ELF format), though properly supporting that ABI is not part of the motivation here, just a consequence of improving the code for CHERI. Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250709232932.37622-2-jrtc27@jrtc27.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-07-22include: sbi: Use array for struct sbi_trap_regs and GET/SET macrosJessica Clarke2-81/+92
Rather than hand-rolling scaled pointer arithmetic with casts and shifts, let the compiler do so by indexing an array of GPRs, taking advantage of the language's type system to scale based on whatever type the register happens to be. This makes it easier to support CHERI where the registers are capabilities, not plain integers, and so this pointer arithmetic would need to change (and currently REGBYTES is both the size of a register and the size of an integer word upstream). Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250709232932.37622-1-jrtc27@jrtc27.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-07-22platform: openpiton: fix uninitialized plic_data structManuel Hernández Méndez1-1/+1
The plic_data struct was uninitialized. This led to misfunction behavior since it was subsequently assigned to the global plic struct, and some struct fields, such as flags and irqchip, contained random values. The fix proposes to initialize the plic_data to the global plic struct, so, after parsing the fdt, the fields of the struct will be set to the default values set in global plic struct definition, or the parsed values in the fdt, or zero. Fixes: 4c37451 ("platform: openpiton: Read the device configurations from device tree") Signed-off-by: Manuel Hernández Méndez <maherme.dev@gmail.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250708180914.1131-1-maherme.dev@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-07-21firmware: Rename __rel_dyn_start/end to __rela_dyn_start/endJessica Clarke2-4/+4
We are using and expecting the RELA format, not the REL format, and this is the conventional linker-generated name for the start/end symbols, so use it rather than confusing things by making it look like we're accessing .rel.dyn, which would be in the REL format with no explicit addend. Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20250710002937.44307-1-jrtc27@jrtc27.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-07-21include: sbi: Don't use #pragma when preprocessing device tree sourcesJessica Clarke1-0/+2
Since this persists in the preprocessed output (so that it can affect the subsequent compilation), it ends up in the input to dtc and is a syntax error, breaking the k210 build. Ideally we wouldn't add the -include flag to DTSCPPFLAGS in the first place as this header is wholly pointless there, but that's a more invasive build system change compared to just making this header safe to include there. Fixes: 86c01a73ff9d ("lib: sbi: Avoid GOT indirection for global symbol references") Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Xiang W <wxjstz@126.com> Reviewed-by: Xiang W <wxjstz@126.com> Link: https://lore.kernel.org/r/20250709232840.37551-1-jrtc27@jrtc27.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-07-21firmware: payload: test: Add SBI shutdown call after test messageXiang W1-3/+9
Previously, 'make run' would hang in WFI after printing the test message. This commit adds an SBI ecall to ensure QEMU exits cleanly after the test payload runs. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Xiang W <wxjstz@126.com> Link: https://lore.kernel.org/r/20250721010807.460788-1-wxjstz@126.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-07-21lib: sbi: Only enable TM bit in scounterenAtish Patra1-2/+2
The S-mode should disable Cycle and instruction counter for user space to avoid side channel attacks. The Linux kernel already does this so that any random user space code shouldn't be able to monitor cycle/instruction without higher privilege mode involvement. Remove the CY/IR bits in scountern in OpenSBI. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20250513-fix_scounteren-v1-1-01018e0c0b0a@rivosinc.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-07-20include: sbi: fix swap errors with newer gcc -Werror=sequence-pointBen Dooks1-3/+7
The BSWAPxx() macros are now throwing the following warnings with newer gcc versions. This is due to throwing an argument in that may be evaluated more than one (I think) and therefore things like the example below should be avoided. Fix by making a set of BSWAPxx() wrappers which specifically only evaluate 'x' once. In file included lib/sbi/sbi_mpxy.c:21: lib/sbi/sbi_mpxy.c: In function ‘sbi_mpxy_write_attrs’: ib/sbi/sbi_mpxy.c:632:63: error: operation on ‘mem_idx’ may be undefined [-Werror=sequence-point] 632 | attr_val = le32_to_cpu(mem_ptr[mem_idx++]); | ~~~~~~~^~ Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by: Rahul Pathak <rahul@summations.net> Reviewed-by: Xiang W <wxjstz@126.com> Link: https://lore.kernel.org/r/20250704122938.897832-1-ben.dooks@codethink.co.uk Signed-off-by: Anup Patel <anup@brainfault.org>
2025-07-20firmware: Initial compiler built-in stack protector supportAlvin Chang4-0/+72
Add __stack_chk_fail() and __stack_chk_guard variable which are used by compiler built-in stack protector. This patch just try to support stack-protector so the value of the stack guard variable is simply fixed for now. It could be improved by deriving from a random number generator, such as Zkr extension or any platform-specific random number sources. Introduce three configurations for the stack protector: 1. CONFIG_STACK_PROTECTOR to enable the stack protector feature by providing "-fstack-protector" compiler flag 2. CONFIG_STACK_PROTECTOR_STRONG to provide "-fstack-protector-strong" 3. CONFIG_STACK_PROTECTOR_ALL to provide "-fstack-protector-all" Instead of fixing the compiler flag of stack-protector feature as "-fstack-protector", we derive it from the introduced Kconfig configurations. The compiler flag "stack-protector-cflags-y" is defined as Makefile "immediately expanded variables" with ":=". Thus, the stronger configuration of the stack protector can overwrite the preceding one. Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250703151957.2545958-3-alvinga@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-07-20lib: sbi: Remove redundant call to sbi_hart_expected_trap_addr()Alvin Chang4-11/+7
The variable "sbi_hart_expected_trap" has already been extern variable. Therefore, the program can directly refer to it instead of calling sbi_hart_expected_trap_addr(). Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250703151957.2545958-2-alvinga@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-07-20lib: sbi_list: add a helper for safe list iterationYong-Xuan Wang1-0/+13
Some use cases require iterating safe against removal of list entry. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250618025416.5331-1-yongxuan.wang@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-07-20lib: utils/serial: Clear LSR status and check RBR statusYi Pei1-4/+3
On some platforms, read RBR when it is empty may result in an error. Signed-off-by: Yi Pei <neopimail@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/CAFPVDjQZ1gpf8-u--RBbAL1Y0FfDN2vZ3g=wBw+Bp-8ppuz3HA@mail.gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-30include: Bump-up version to 1.7v1.7Anup Patel1-1/+1
Update the OpenSBI version to 1.7 as part of release preparation. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-24lib: rpmi: Make RPMI drivers as non-experimentalRahul Pathak7-7/+0
As RPMI v1.0 specification is frozen, disable the experimental tag for such RPMI drivers. Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250618053854.2577299-2-rpathak@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-24lib: utils: Add Implementation ID and Version as RPMI MPXY attributesRahul Pathak4-1/+30
The latest frozen RPMI spec has added Implementation ID and Implementation Version as message protocol specific mpxy attributes. Add support for these. Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250618053854.2577299-1-rpathak@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-17lib: sbi_platform: Add platform specific pmp_set() and pmp_disable()Chao-ying Fu4-0/+144
Allow platforms to implement platform specific PMP setup and PMP disable functions which are called before actual PMP CSRs are configured. Also, implement pmp_set() and pmp_disable() for MIPS P8700. Signed-off-by: Chao-ying Fu <cfu@mips.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250614172756.153902-1-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-16lib: sbi: dbtr: Fix update_triggers to match SBIJesse Taube3-16/+21
OpenSBI implements sbi_dbtr_update_trig as `sbi_dbtr_update_trig(unsigned long trig_idx_base, unsigned long trig_idx_mask)` yet SBI v3.0-rc7 Chapter 19. Debug Triggers Extension [0] declares it as `sbi_debug_update_triggers(unsigned long trig_count)` Change update_triggers to match SBI. [0] https://github.com/riscv-non-isa/riscv-sbi-doc/tree/v3.0-rc7/src/ext-debug-triggers.adoc Fixes: 97f234f15c96 ("lib: sbi: Introduce the SBI debug triggers extension support") Signed-off-by: Jesse Taube <jesse@rivosinc.com> Reviewed-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Tested-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Link: https://lore.kernel.org/r/20250528154604.571815-1-jesse@rivosinc.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-16lib: sbi: Optimize saddr mapping in sbi_dbtr.cXiang W1-7/+8
The original implementation mapped saddr individually for each entry. The updated code now maps saddr for all entries in a single operation. This change reduces the number of PMP (Physical Memory Protection) operations, improving efficiency and performance. Tested-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Reviewed-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Signed-off-by: Xiang W <wxjstz@126.com> Link: https://lore.kernel.org/r/20250514052422.575551-1-wxjstz@126.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-16lib: sbi: dbtr: Fix shared memory layoutJesse Taube2-4/+4
The existing sbi_dbtr_shmem_entry has a size of 5 * XLEN with the final entry being idx. This is in contrast to the SBI v3.0-rc7 Chapter 19. Debug Triggers Extension [0] where idx and trig_state share the same offset (0) in shared memory, with a total size of 4 * XLEN for all the SBI calls. Replace struct with union to match memory layout described in SBI. [0] https://github.com/riscv-non-isa/riscv-sbi-doc/tree/v3.0-rc7/src/ext-debug-triggers.adoc Fixes: 97f234f15c96 ("lib: sbi: Introduce the SBI debug triggers extension support") Signed-off-by: Jesse Taube <jesse@rivosinc.com> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Tested-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Tested-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Link: https://lore.kernel.org/r/20250604135225.842241-1-jesse@rivosinc.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-16lib: utils: Fix fdt_parse_aclint_node() for non-contiguous hartidAnup Patel1-3/+0
Currently, the fdt_parse_aclint_node() does not handle non-contiguous hartid correctly and returns incorrect first_hartid and hart_count. This is because the for-loop in fdt_parse_aclint_node() skips a hartid for which hartindex is not available (aka corresponding CPU DT node is disabled). For example, on a platform with 4 HARTs (hartid 0, 1, 2, and 3) where CPU DT nodes with hartid 0 and 2 are disabled, the fdt_parse_aclint_node() returns first_hartid = 1 and hart_count = 3 which is incorrect. To address the above issue, drop the sbi_hartid_to_hartindex() check from the for-loop of fdt_parse_aclint_node(). Fixes: 5e90e54a1a53 ("lib: utils:Check that hartid is valid") Reported-by: Maria Mbaye <MameMaria.Mbaye@microchip.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250606055810.237441-1-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-16lib: sbi: Revert entry_count before doing hsm stop in hsm wait loopAnup Patel3-1/+18
Using hsm stop in hsm wait loop causes secondary harts to be stuck forever in OpenSBI on RISC-V platforms where HSM hart hotplug is available and all harts come-up at the same time during system power-on. For example, lets say we have two harts A and B on a RISC-V platform with HSM hart hotplug which come-up at the same time during system power-on. The hart A enters OpenSBI before hart B hence it becomes the primary (or cold-boot) hart whereas hart B becomes the secondary (or warm-boot) hart. The hart A follows the OpenSBI cold-boot path and registers hsm device before hart B enters OpenSBI. The hart B eventually enters OpenSBI and follows the OpenSBI warm-boot path so it will increment it's own entry_count before entering hsm wait loop where it sees hsm device and stops itself. Later as part of the Linux boot-up sequence, hart A issues SBI HSM start call to bring-up hart B but OpenSBI sees entry_count != init_count for hart B in sbi_hsm_hart_start() hence hsm_device_hart_start() is not called for hart B resulting in hart B stuck forever in OpenSBI. To fix the above issue, revert entry_count before doing hsm stop in hsm wait loop. Fixes: d844deadec94 ("lib: sbi: Use hsm stop for hsm wait") Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20250527124821.2113467-1-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-16lib: utils/irqchip: always parse msi information for each aplic deviceInochi Amaoto1-69/+71
OpenSBI only parses MSI information of the first next level subdomain for now, which makes the root domain misconfigured in some case: 1. the msi is not enabled on the first subdomain of the root domain, but other subdomains enable MSI. 2. the root domain is set as direct mode, but its subdomains enable MSI. So it is needed to parse all child of the root domain, Otherwise, the some non-root domains are broken. As the specification says, it is safe to parse the MSI information of all its subdomain and write the msiaddrcfg register of the non root domain as they are read only. Parse the aplic MSI information recursively for all aplic device. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Link: https://lore.kernel.org/r/20250523085348.1690368-1-inochiama@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-15lib: sbi: fwft: Use only the provided PMLEN valueSamuel Holland1-18/+18
As of riscv-sbi-doc commit c7d3d1f7dcaa ("ext-fwft: use the provided value in fwft_set(POINTER_MASKING_PMLEN)"), the SBI implementation must use only the provided PMLEN value or else fail. It may not fall back to a larger PMLEN value. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Radim Krčmář <rkrcmar@ventanamicro.com> Link: https://lore.kernel.org/r/20250522013503.2556053-1-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-15lib: sbi: pmu: Remove MIP clearing from pmu_sse_enable()Clément Léger1-1/+0
Clearing MIP at that point means that we can probably lose a pending interrupt. This should not happen, remove MIP clearing from there. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20250519083950.739044-3-cleger@rivosinc.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-15lib: sbi: pmu: Add SSE register/unregister() callbacksClément Léger1-6/+18
As soon as the SSE event is registered, there is no reason not to delegate the interrupt. Split the PMU SSE enable/disable() callbacks by moving MIDELEG setting to register/unregister(). Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20250519083950.739044-2-cleger@rivosinc.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-15Makefile: Add flag for reprodubility compiler flagsKhem Raj1-0/+7
Provides mechanism to remove absolute paths from binaries using -ffile-prefix-map It will help distros (e.g. yocto based ones ) which want to ship the .elf files but need to scrub absolute paths in objects Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Khem Raj <raj.khem@gmail.com> Link: https://lore.kernel.org/r/20250515025931.3383142-1-raj.khem@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-14platform: generic: mips: add P8700Chao-ying Fu7-0/+517
Extend generic platform to support MIPS P8700. Signed-off-by: Chao-ying Fu <cfu@mips.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250522212141.3198-2-cfu@mips.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-14lib: utils: hsm: Do not fail on EALREADY in rpmi-hsm fixup.Ziang Wang1-1/+1
In case harts are divided into groups that use different rpmi-hsm channels in different mailboxes, the suspend state fixup function will return EALREADY on secondary entry, simply skip on this error. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Ziang Wang <wangziang.ok@bytedance.com> Link: https://lore.kernel.org/r/20250507074620.3162747-1-wangziang.ok@bytedance.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-14Makefile: Make $(LLVM) more flexibleCharlie Jenkins2-4/+22
Introduce a way for developers to easily switch between LLVM versions with LLVM=/path/to/llvm/ and LLVM=-version. This is a useful addition to the existing LLVM=1 variable which will select the first clang and llvm binutils available on the path. Reviewed-by: Anup Patel <anup@brainfault.org> Tested-by: Anup Patel <anup@brainfault.org> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Link: https://lore.kernel.org/r/20250430-improve_llvm_building-v1-1-caae96cc6be6@rivosinc.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-20lib: sbi: pmu: Return SBI_EINVAL if cidx_mask is 0James Raphael Tiovalen1-5/+10
Currently, when configuring a matching programmable HPM counter with Sscofpmf being present, cidx_base > 2, and cidx_mask == 0 to monitor either the CPU_CYCLES or INSTRUCTIONS hardware event, sbi_pmu_ctr_cfg_match will succeed but it will configure the corresponding fixed counter instead of the counter specified by the cidx_base parameter. During counter configuration, the following issues may arise: - If the SKIP_MATCH flag is set, an out-of-bounds memory read of the phs->active_events array would occur, which could lead to undefined behavior. - If the CLEAR_VALUE flag is set, the corresponding fixed counter will be reset, which could be considered unexpected behavior. - If the AUTO_START flag is set, pmu_ctr_start_hw will silently start the fixed counter, even though it has already started. From the supervisor's perspective, nothing has changed, which could be confusing. The supervisor will not see the SBI_ERR_ALREADY_STARTED error code since sbi_pmu_ctr_cfg_match does not return the error code of pmu_ctr_start_hw. The only way to detect these issues is to check the ctr_idx return value of sbi_pmu_ctr_cfg_match and compare it with cidx_base. Fix these issues by returning the SBI_ERR_INVALID_PARAM error code if the cidx_mask parameter value being passed in is 0 since an invalid parameter should not lead to a successful sbi_pmu_ctr_cfg_match but with unexpected side effects. Following a similar rationale, add the validation check to sbi_pmu_ctr_start and sbi_pmu_ctr_stop as well since sbi_fls is undefined when the mask is 0. This also aligns OpenSBI's behavior with KVM's. Signed-off-by: James Raphael Tiovalen <jamestiotio@gmail.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20250520132533.30974-1-jamestiotio@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-20include: sbi: Change SBI spec version to 3.0Anup Patel5-5/+1
Now that SBI v3.0 specification is frozen, change runtime SBI version implemented by OpenSBI to v3.0. Also, mark extensions defined by the SBI v3.0 specification as non-experimental. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20250516122844.113423-1-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
generated by cgit v1.1 at 2025-09-21 00:23:31 +0000