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2026-04-08lib: sbi_bitmap_test: add tests for bitmap_empty()HEADmasterYu-Chien Peter Lin1-0/+29
Add tests for bitmap_empty(), covers empty/non-empty bitmaps and edge case nbits=0. Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260311125116.1401002-2-peter.lin@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-04-08include: sbi_bitmap: add bitmap_empty() functionYu-Chien Peter Lin1-0/+16
Add bitmap_empty() to check if bitmap has no bits set. Unlike bitmap_weight() which calls sbi_popcount() on every word, bitmap_empty() uses simple non-zero comparisons with early exit. Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260311125116.1401002-1-peter.lin@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-04-06lib: utils: Add MPXY client driver for RPMI MM service groupRanbir Singh5-0/+161
Add necessary infra for implementing RPMI Management Mode service group on platform microcontroller. Co-authored-by: Sunil V L <sunilvl@oss.qualcomm.com> Signed-off-by: Ranbir Singh <ranbir.singh@oss.qualcomm.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260225061347.1396504-1-ranbir.singh@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-04-06lib: Fix sbi_strchr to correctly handle null terminator searchChen Pei1-6/+5
The original sbi_strchr implementation did not conform to the C standard behavior. According to the C standard and POSIX specification, strchr(s, 0) should return a pointer to the null terminator at the end of string s. The previous implementation used a while loop that would terminate when either reaching the end of string or finding the character, but it would return NULL when searching for the null terminator instead of returning a pointer to the null terminator itself. The fixed implementation uses a do-while loop that ensures even when searching for the null terminator, the function correctly returns a pointer to the null terminator position rather than NULL. This fix ensures sbi_strchr behavior aligns with standard library function semantics, making it more predictable and safe for users expecting standard C library behavior. Signed-off-by: Chen Pei <cp0613@linux.alibaba.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260306094425.1918-3-cp0613@linux.alibaba.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-04-06lib: tests: Add test for stringChen Pei2-0/+375
Added unit tests for various string operations using SBI unit test framework. Signed-off-by: Chen Pei <cp0613@linux.alibaba.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260306094425.1918-2-cp0613@linux.alibaba.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-04-06sifive_dev_platform: Set default MMIO region when SmePMP is enabledYu-Chien Peter Lin1-0/+50
Set a default MMIO region with a single SmePMP entry, which allows us to save entries for M-mode only devices. The default entry has M-/S-mode shared permission, so system-level resource protection, such as RISC-V World extension and WorldGuard checker, will be introduced to protect M-mode only region access from lower privilege modes. Reviewed-by: Greentime Hu <greentime.hu@sifive.com> Reviewed-by: Zong Li <zong.li@sifive.com> Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Link: https://lore.kernel.org/r/20260224031733.3817148-3-peter.lin@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-04-06platform: sifive: Add initial support for SiFive development platformYu-Chien Peter Lin4-0/+31
Add initial platform support for SiFive development platforms with the "sifive-dev" compatible string. Reviewed-by: Greentime Hu <greentime.hu@sifive.com> Reviewed-by: Zong Li <zong.li@sifive.com> Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Link: https://lore.kernel.org/r/20260224031733.3817148-1-peter.lin@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: sbi_init: Call hart init and timer init before platform early initYu-Chien Peter Lin1-14/+12
To allow the platform early drivers to use the sbi_timer_mdelay(), sbi_timer_udelay() and sbi_hart_has_extension() helpers, reorder the initialization sequence must call sbi_hart_init() and sbi_timer_init() prior to sbi_platform_early_init() during both cold and warm boot paths. Reviewed-by: Greentime Hu <greentime.hu@sifive.com> Reviewed-by: Zong Li <zong.li@sifive.com> Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Link: https://lore.kernel.org/r/20260224031733.3817148-2-peter.lin@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: sbi_irqchip: Allow registering interrupt handlersAnup Patel5-3/+267
To handle external interrupts in M-mode, the sbi_irqchip framework must allow registering interrupt handlers from device drivers. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-9-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: sbi_irqchip: Associate 32-bit unique ID for each irqchip deviceAnup Patel5-0/+24
Allow locating irqchip device instance using a unique 32-bit ID. This 32-bit unique ID can be set by the irqchip driver at the time of adding irqchip device. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-8-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: utils/irqchip: Add unique_id to plic, aplic, and imsic dataAnup Patel9-0/+11
Add a 32-bit unique ID to plic, aplic, and imsic data which can be used to differentiate multiple irqchip devices. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-7-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: sbi_irqchip: Support irqchip device targetting subset of hartsAnup Patel5-22/+73
It is possible to have platform where an irqchip device targets a subset of harts and there are multiple irqchip devices to cover all harts. To support this scenario: 1) Add target_harts hartmask to struct sbi_irqchip_device which represents the set of harts targetted by the irqchip device 2) Call warm_init() and process_hwirqs() callbacks of an irqchip device on a hart only if irqchip device targets that particular hart Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-6-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: utils/irqchip: Add IDC to hartindex map in struct aplic_dataAnup Patel2-1/+54
A platform can have multiple APLICs in direct-mode targetting different subset of harts. Add APLIC ID to hartindex map in struct aplic_data to capture the set of harts targeted by a given APLIC in direct-mode. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-5-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: utils/irqchip: Fix context_map init in irqchip_plic_update_context_map()Anup Patel1-0/+5
The context_map[][] elements should be initialized with negative value so that context_map does not point to anything for non-existent PLIC contexts. Fixes: 69448a079065 ("lib: utils/irqchip: plic: Provide a hartindex to context map") Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-4-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: sbi_irqchip: Rename irq_handle() callback to process_hwirqs()Anup Patel3-6/+6
The irq_handle() callback of irqchip device is meant to process hardware interrupt of the irqchip hence rename it accordingly. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-3-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: sbi_irqchip: Use chip as variable name for irqchip deviceAnup Patel2-10/+10
The irqchip device represents an interrupt controller so use chip as variable name instead of dev. This will avoid confusion as the sbi_irqchip framework grows. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-2-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-10lib: sbi: fix sse_event_inject() status settingCharlie Jenkins1-1/+1
sse_event_inject() currently sets all status bits to 1 except for SBI_SSE_ATTR_STATUS_PENDING_OFFSET which it sets to zero. Instead of overwriting all the values of the status bits, sse_event_inject() is only expected to clear SBI_SSE_ATTR_STATUS_PENDING_OFFSET. Fix sse_event_inject() to only do the clearing. Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260302-event_inject_fix-v1-1-e88952b03aa4@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-10lib: Use proper add opcode on RV32 with ZalrscMarti Alonso3-2/+7
The addw opcode is only defined in RV64, which produces 32-bit results. On RV32, the default add opcode already produces 32-bit results. Fixes: 995f226f3f33 ("lib: Emit lr and sc instructions based on -march flags") Signed-off-by: Marti Alonso <martialonso11@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260301205421.2074835-1-martialonso11@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-10platform: generic: mips boston: update "compatible"Vladimir Kondratiev1-1/+1
Use a platform-specific compatible to avoid clashing with CPU compatible Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20260301141332.2941601-1-vladimir.kondratiev@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-09lib: fdt_helper: Removed unnecessary dt parsing checkVictoriano Morales1-4/+4
The check for the address being different from 0 for the UART, PLIC, APLIC and IMSIC dt nodes is unnnecessary and could skip valid nodes. Signed-off-by: Victoriano Morales <victoriano.morales@openchip.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260219083423.30690-1-victoriano.morales@openchip.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-09lib: sbi: Fix undefined behavior in signed shifts in sbi_hart.cMarcos Oduardo2-2/+2
UBSan detected undefined behavior in sbi_hart.c and sbi_fwft.c (in the case of sbi_fwft.c, the bug comes from a macro call defined at sbi_ecall_interface.h) caused by shifting a signed integer into the sign bit (1 << 31) This can be fixed by using the 1UL literal, ensuring defined arithmetic. Please let me know if there’s any other most suitable solution for this bug. Signed-off-by: Marcos Oduardo <marcos.oduardo@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223001202.284612-1-marcos.oduardo@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-09include: sbi: Fix illegal shift in sbi_domain.hMarcos Oduardo1-2/+4
In sbi_domain.h, when checking if a memory region is a subset of another, an undefined behavior arithmetic operation was caught when sanitizing with UBSan (shift exponent __riscv_xlen). This patch adds a check to handle the case where the region order is __riscv_xlen, avoiding the illegal shift and ensuring the operation remains defined. Please let me know if there’s any other most suitable solution for this bug. Signed-off-by: Marcos Oduardo <marcos.oduardo@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260222235219.276432-1-marcos.oduardo@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-25platform: generic: eyeq7h: enable ECC on L1 cacheVladimir Kondratiev1-0/+2
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-23-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-25platform: generic: p8700: fix MIPS specific CSRsVladimir Kondratiev1-4/+20
P8700 has MIPS specific CSRs. Fix the list, adding few missing ones and remove few non-existing Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-22-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-25platform: generic: mips eyeq7h: prohibit accessing memory beyond DRAMVladimir Kondratiev1-1/+36
SBI code arranges domain PMP regions in a way that last entry is all-inclusive "0..~0 RWX" and the rest of entries are not programmed. This causes a problem for the eyeq7h. CPU can issue speculative prefetches to non-existent addresses. If this access goes to the system NOC, it is mis-interpreted as an access violation and error is reported, forcing system reset. To prevent such a speculative transaction to leave a CPU cluster, block it using PMP, by restricting memory region to physically present memory. To achieve this, on early init: - update flags for the last all-inclusive "0..~0 RWX" entry to be inaccessible MMIO. MMIO serves to set up PMA attributes to uncached non-prefetchable, preventing transactions to reach system NOC - add an all-permissive entry matching DRAM. Resulting memory regions: Domain0 Region00 : 0x0000000800100000-0x000000080013ffff M: (F,R,X) S/U: () Domain0 Region01 : 0x0000000800100000-0x00000008001fffff M: (F,R,W) S/U: () Domain0 Region02 : 0x0000000048700000-0x000000004870ffff M: (I,R,W) S/U: () Domain0 Region03 : 0x0000000067480000-0x000000006748ffff M: (I,R,W) S/U: () Domain0 Region04 : 0x0000000067500000-0x000000006750ffff M: (I,R,W) S/U: () Domain0 Region05 : 0x0000000048740000-0x000000004875ffff M: (I,R,W) S/U: () Domain0 Region06 : 0x00000000674c0000-0x00000000674dffff M: (I,R,W) S/U: () Domain0 Region07 : 0x0000000067540000-0x000000006755ffff M: (I,R,W) S/U: () Domain0 Region08 : 0x0000000000000000-0x000000007fffffff M: (I,R,W) S/U: (R,W) Domain0 Region09 : 0x0000000800000000-0x00000008ffffffff M: () S/U: (R,W,X) Domain0 Region10 : 0x0000001000000000-0x0000001fffffffff M: (I) S/U: (R,W) Domain0 Region11 : 0x0000000000000000-0xffffffffffffffff M: (I) S/U: () Here Region09 covers DRAM, region 11 set to non-accessible uncached no-prefetch for the entire address range Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-21-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-25platform: generic: mips p8700: dump MMIO regionsVladimir Kondratiev3-0/+65
Debug print MMIO regions Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-20-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-25platform: generic: mips eyeq7h: fix NCORE registers access from clusters 1..2Vladimir Kondratiev2-0/+25
CPU clusters 1 and 2 cannot access NCORE registers through AUX ports. AUX ports of clusters 1 and 2 are connected to NCORE through east port. East port has no access to NCORE registers address space. Re-route NCORE registers range to MEM port by re-configuring MMIO regions in the GCR. REsulting map is as below. Mind a gap between regions [1] and [2]; this gap covering NCORE registers now routed to the default MEM port Cluster 0: 4 MMIO regions [0] : 0x0000000000000000-0x000000001fff0000 AUX0 UC|UCA [1] : 0x0000000020000000-0x00000000677f0000 AUX0 ANY [2] : 0x0000000080000000-0x0000001fffff0000 AUX0 UC|UCA [3] : --disabled-- Cluster 1: 4 MMIO regions [0] : 0x0000000000000000-0x000000001fff0000 AUX0 UC|UCA [1] : 0x0000000020000000-0x00000000677f0000 AUX0 ANY [2] : 0x0000000080000000-0x0000001fffff0000 AUX0 UC|UCA [3] : --disabled-- Cluster 2: 4 MMIO regions [0] : 0x0000000000000000-0x000000001fff0000 AUX0 UC|UCA [1] : 0x0000000020000000-0x00000000677f0000 AUX0 ANY [2] : 0x0000000080000000-0x0000001fffff0000 AUX0 UC|UCA [3] : --disabled-- Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-19-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-25platform: generic: mips eyeq7h: synchronize timers across clustersVladimir Kondratiev3-0/+23
Use eyeq7 specific method to synchronously restart architectural mtimer and eyeq7h specific high-resolution timer with common hardware trigger. This ensures all timers are precisely in sync Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-18-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-25platform: generic: mips p8700: synchronize hi-res timersVladimir Kondratiev3-1/+19
There's high-resolution (1GHz) timer found in the p8700 cluster. This timer used for precise time measurement by platform specific software. Synchronize this proprietary timers to reference in cluster 0. Procedure borrowed from the aclint mtimer. Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-17-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-25platform: generic: mips p8700: use SBI bitfield manipulator macrosVladimir Kondratiev3-34/+21
Switch to GENMASK, EXTRACT_BITFIELD, INSERT_BITFIELD Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-16-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-25platform: generic: mips p8700: CPU clusters memrangesVladimir Kondratiev4-44/+59
Reserve memory regions for CPU clusters according to P8700 cluster memory layout. There's a set of components in the CPU cluster according to [1] [1] https://mips.com/wp-content/uploads/2025/11/P8700-F_Programmers_Reference_Manual-TM.pdf Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-15-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-25platform: generic: mips p8700: cache geometry detectionVladimir Kondratiev3-0/+126
P8700 has a read-only cache configuration registers. Provide a CPU specific function to extract cache information. Use this information in the eyeq7h board for informational message Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-14-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-25platform: generic: mips eyeq7h: deassert accelerator cluster resetsVladimir Kondratiev1-0/+16
On the EyeQ7H board, there's cluster level resets found in the accelerator OLBs. These resets should be deasserted once on boot and never used after Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-13-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-25platform: generic: mips eyeq7h: detect accelerators cluster presenceVladimir Kondratiev1-0/+44
In the design, accelerator clusters ACC[01] and XNN[01] presence indicated by the OLB_WEST register OLB_WEST_TSTCSR. In the simulation environments, part (or all) accelerators may be not instantiated Disable clusters not present in the model, updating the DTB Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-12-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-25platform: generic: mips eyeq7h: power up clusters with OLBVladimir Kondratiev1-0/+42
In the eyeq7h platform, there's extra power control for the CPU clusters. To enable cluster, it should be powered up using this OLB registers prior to accessing any cluster management registers Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-11-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-25platform: generic: mips: add P8700 based "eyeq7h" and "boston"Vladimir Kondratiev8-226/+523
Refactor MIPS P8700 support, convert P8700 into a "CPU" and add 2 platforms using this CPU: - "boston" - FPGA platform developed by MIPS - "eyeq7h" - automotive platform by Mobileye Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-10-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-25platform: generic: mips p8700: access CM registers via match dataVladimir Kondratiev3-33/+19
Modify the coherence manager register accessors to use the global variable p8700_cm_info instead of the statically declared GLOBAL_CM_BASE array. Also use p8700_cm_info to get the number of coherence managers and their base addresses in mips_p8700_early_init() and mips_p8700_nascent_init(). Clean up the hard-coded values in mips/board.h, access to the coherence manager is now fully based on information provided by platform compatible from the device tree. Signed-off-by: Benoît Monin <benoit.monin@bootlin.com> Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-9-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-25platform: generic: mips p8700: Add match data for CM infoBenoît Monin2-1/+32
Introduce a structure p8700_cm_info holding the number of coherence managers and their base addresses found in a particular SoC. Declare a global pointer to the structure that is set in mips_p8700_platform_init(), based on the match data of the platform compatible. For the match data of the MIPS P8700, a single coherence manager with a base address of 0x16100000 is declared, identical to what is found in mips/board.h. For now, access to the coherence manager register is still based on the hard-coded values defined in mips/board.h. Signed-off-by: Benoît Monin <benoit.monin@bootlin.com> Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-8-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-25platform: generic: mips p8700: use global CM addressesVladimir Kondratiev3-64/+45
In the multi-cluster system each cluster has its own CM (Coherency Manager). Every CM has its "global" memory address where it is accessible from any bus master. Initially, all CMs accessible from the local cluster using same "local" address. Transactions by local address are not routed through system bus and thus are faster. Remap CM in every cluster to the local address matching its global address. Then, every CM is always accessed using same address, but when transaction initiated from the local cluster it is routed internally. This removes need for 2 PMP regions covering local address access. CM accessor functions simplified because there's no need to detect whether transaction is local or global Access timer always in cluster 0 Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-7-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-25platform: generic: mips p8700: faster core bootVladimir Kondratiev1-23/+30
When powering up cores, wait for power up to complete using tight loop. This saves 10ms delay observed for every core Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-6-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-25platform: generic: mips p8700: fix powering up other clusterVladimir Kondratiev1-19/+10
While powering up cluster, only indication is bit in cluster power control. It used to wait for CORE0 in that cluster reach U5 state (non-coherent execution), this won't happen when only CM powered up without booting any core Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-5-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-25platform: generic: mips p8700: reserve memory for M-mode peripheralsVladimir Kondratiev1-37/+60
Reserve memory upfront in large well aligned chunks, to avoid problem with PMP granularity that is 64Kbytes for the p8700 CPU Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-4-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-25platform: generic: mips p8700: improve CM access tracingVladimir Kondratiev1-2/+4
use function call like format; debug print returning value of the "read" accessor Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-3-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-25lib: sbi_hart_pmp: disable unconfigured PMP entriesVladimir Kondratiev1-0/+6
Disable PMP entries not configured in domain. These entries may contain values configured by the boot loader; disabling it to be certain PMP configuration is exactly as configured by the openSBI Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-2-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-25lib: sbi: print hartid in hexVladimir Kondratiev1-1/+1
Hartid is better represented by hex number since it is likely a combination of bits representing various elements in the platform hierarchy Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-1-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-21lib: sbi_pmu: Add FW counter index validation when reading high bits on RV64James Raphael Tiovalen3-4/+12
Currently, when we attempt to read the upper 32 bits of a firmware counter on RV64 or higher, we just set `sbiret.value` to 0 without validating the counter index. The SBI specification requires us to set `sbiret.error` to `SBI_ERR_INVALID_PARAM` if the counter index points to a hardware counter or an invalid counter. Add a validation check to ensure compliance with the specification on RV64 or higher. Fixes: 51951d9e9af8 ("lib: sbi_pmu: Implement sbi_pmu_counter_fw_read_hi") Signed-off-by: James Raphael Tiovalen <jamestiotio@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260125090643.190748-1-jamestiotio@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-20lib: sbi_pmu: Fix multiple FW counter start operations with custom PMU deviceJames Raphael Tiovalen1-1/+5
Currently, we immediately return the result of `fw_counter_start` if the event code is 0xFFFF. However, this skips setting the bit in the `fw_counters_started` bitmap even if the platform-specific call succeeds. Restore the original behavior of returning early only on an error so that we still set the bit in the bitmap. This prevents multiple starts of the same FW counter. This also aligns the expectations of `pmu_ctr_start_fw` with `pmu_ctr_stop_fw` since we cannot assume that the platform-specific functions to start and stop FW counters will modify the bitmap state. Fixes: 57d3aa3b0dbd ("lib: sbi_pmu: Introduce fw_counter_write_value API") Signed-off-by: James Raphael Tiovalen <jamestiotio@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260116165304.180441-1-jamestiotio@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-20lib: utils/serial: Add support for Altera JTAG UARTIcenowy Zheng6-0/+145
Altera provides a JTAG UART core that provides virtual UART over JTAG and can coexist with their virtual JTAG. [1] This core has already been supported by Linux and the programming interface has always been stable. Add support for it to OpenSBI to ease JTAG prototype bringing up. The driver follows the device tree binding in mainline Linux. [2] [1] https://docs.altera.com/r/docs/683130/25.3/embedded-peripherals-ip-user-guide/jtag-uart-core [2] https://github.com/torvalds/linux/blob/v6.19-rc1/Documentation/devicetree/bindings/serial/altr%2Cjuart-1.0.yaml Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260104065506.70182-1-zhengxingda@iscas.ac.cn Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-20firmware: Initialize stack guard via ZkrXiang W2-0/+34
Try to initialize stack protection guard via the zkr extension. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260104051812.128496-1-wxjstz@126.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-11lib: utils/suspend: add Andes ATCSMU suspend driverBen Zong-You Xie7-10/+178
Implement a system-wide suspend driver for the Andes AE350 platform. This driver supports Andes-specific deep sleep (suspend to RAM) and light sleep (suspend to standby) functionalities via the ATCSMU. The major differences between deep sleep and light sleep are: - Power Domain and Resume Path: Deep sleep powers down the core domain. Consequently, harts waking from deep sleep resume from the reset vector. Light sleep utilizes clock gating to the core domain; harts maintain state and resume execution at the instruction immediately following the WFI instruction. - Primary Hart Wakeup: In both modes, the primary hart is woken by UART or RTC alarm interrupts. In deep sleep, the primary hart is additionally responsible for re-enabling the Last Level Cache (LLC) and restoring Andes-specific CSRs. - Secondary Hart Wakeup: In light sleep, secondary harts are woken by an IPI sent from the primary hart. In deep sleep, they are woken by an ATCSMU hardware wake-up command. Furthermore, secondary harts must restore Andes-specific CSRs when returning from deep sleep. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-6-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
generated by cgit v1.2.3 (git 2.39.1) at 2026-05-16 05:28:49 +0000