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2025-12-08platform: generic: spacemit: add missing objects.mkJunhui Liu2-2/+8
Add the missing objects.mk for the SpacemiT platform, required for the K1 platform to be included in the build. Fixes: 1f84ec2a ("platform: generic: spacemit: add K1") Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Acked-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Link: https://lore.kernel.org/r/20251124-k1-fix-v1-1-8d7e7a29379e@pigmoral.tech Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-08lib: utils/cache: Add SiFive Extensible Cache (EC) driverNick Hu1-0/+1
Add support for SiFive Extensible Cache (EC) controller with multi-slice architecture. The driver implements cache maintenance operations through MMIO register interface. Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Co-developed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Co-developed-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-3-8423a721924c@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-08lib: utils/cache: Add SiFive PL2 controllerNick Hu1-0/+1
SiFive Private L2(PL2) cache is a private cache owned by each hart. Add this driver to support private cache flush operations via the MMIO registers. Co-developed-by: Eric Lin <eric.lin@sifive.com> Signed-off-by: Eric Lin <eric.lin@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Co-developed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-2-8423a721924c@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-01platform: openpiton: use generic early initManuel Hernández Méndez1-22/+3
Add code for using generic_early_init so that the uart parameters are parsed from dtb. Signed-off-by: Manuel Hernández Méndez <manuel.hernandez@openchip.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251107075429.1382-1-manuel.hernandez@openchip.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-01platform: ariane: parse dtb for getting some initial parametersManuel Hernández Méndez1-15/+24
Add code for getting some uart, clint and plic parameters from device tree. Signed-off-by: Manuel Hernández Méndez <manuel.hernandez@openchip.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251107075412.1350-1-manuel.hernandez@openchip.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-05platform: ariane: Move ariane platform from fpga to genericManuel Hernández Méndez7-75/+25
The Ariane framework has a generic PMU that is not used by OpenSBI. Due to OpenSBI’s build system we cannot directly reuse the generic platform functions, so move the Ariane platform to generic. Also due to the generic platform is where new features are added. Signed-off-by: Manuel Hernández Méndez <maherme.dev@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251023090347.30746-1-maherme.dev@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-04lib: utils: Add MPXY RPMI mailbox driver for performanceJoshua Yeong1-0/+1
Add MPXY RPMI mailbox driver for performance. Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com> Reviewed-by: Rahul Pathak <rpathak@ventanamicro.com> Link: https://lore.kernel.org/r/20251013153138.1574512-4-joshua.yeong@starfivetech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-04lib: utils: Add MPXY RPMI mailbox driver for device powerJoshua Yeong1-0/+1
Add MPXY RPMI mailbox driver for device power. Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com> Reviewed-by: Rahul Pathak <rpathak@ventanamicro.com> Link: https://lore.kernel.org/r/20251013153138.1574512-3-joshua.yeong@starfivetech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-04lib: utils: Add MPXY RPMI mailbox driver for voltageJoshua Yeong1-0/+1
Add voltage service group for RPMI/MPXY support Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com> Reviewed-by: Rahul Pathak <rpathak@ventanamicro.com> Link: https://lore.kernel.org/r/20251013153138.1574512-2-joshua.yeong@starfivetech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils/suspend: Add SiFive SMC0 driverNick Hu1-0/+1
The SiFive SMC0 controls the clock and power domain of the core complex on the SiFive platform. The core complex enters the low power state after the secondary cores enter the tile power gating and last core execute the `CEASE` instruction with the corresponding SMC0 configurations. The devices that inside both tile power domain and core complex power domain will be off, including caches and timer. Therefore we need to flush the last level cache before entering the core complex power gating and update the timer after waking up. Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-12-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils/hsm: Add SiFive TMC0 driverNick Hu1-0/+1
The SiFive TMC0 controls the tile power domains on SiFive platform. The CPU enters the low power state via the `CEASE` instruction after configuring the TMC0. Any devices that inside the tile power domain will be power gated, including the private cache. Therefore flushing the private cache before entering the low power state. Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-9-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: sbi: Extends sbi_ipi_raw_send() to use all available IPI devicesNick Hu1-1/+1
A platform may contain multiple IPI devices. In certain use cases, such as power management, it may be necessary to send an IPI through a specific device to wake up a CPU. For example, if an IMSIC is powered down and reset, the core cannot receive IPIs from it, so the wake-up must instead be triggered through the CLINT. Suggested-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-8-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils/cache: Add fdt cmo helpersNick Hu1-1/+2
Add the helpers to build up the cache hierarchy via FDT and provide some cmo functions for the user who want to flush the entire cache. Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-4-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28utils: cache: Add SiFive ccache controllerVincent Chen1-0/+1
SiFive Composable cache is a L3 share cache of the core complex. Add this driver to support the share cache maintenance operations via the MMIO registers. Co-developed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Co-developed-by: Nick Hu <nick.hu@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-3-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils: Add FDT cache libraryNick Hu1-0/+1
Add the FDT cache library so we can build up the cache topology via the 'next-level-cache' DT property. Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Co-developed-by: Andy Chiu <andy.chiu@sifive.com> Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-2-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-21lib: Allow custom CSRs in csr_read_num() and csr_write_num()Anup Patel2-155/+11
Some of the platforms use platform specific CSR access functions for configuring implementation specific CSRs (such as PMA registers). Extend the common csr_read_num() and csr_write_num() to allow custom CSRs so that platform specific CSR access functions are not needed. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20250930153216.89853-1-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-20platform: generic: Add SpacemiT K1 platform supportXianbin Zhu1-2/+3
Enable CONFIG_PLATFORM_SPACEMIT_K1 in the defconfig for SpacemiT K1 SoC. Co-authored-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Xianbin Zhu <xianbin.zhu@linux.spacemit.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250925-smt-k1-8-cores-v3-3-0885a8a70f8e@linux.spacemit.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-20platform: spacemit: Add HSM driverXianbin Zhu1-0/+1
Add code to bring up all 8 cores during OpenSBI initialization so that the Linux kernel can detect and use all cores properly. Co-authored-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Xianbin Zhu <xianbin.zhu@linux.spacemit.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250925-smt-k1-8-cores-v3-2-0885a8a70f8e@linux.spacemit.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-20platform: generic: spacemit: add K1Xianbin Zhu3-0/+215
Add initial platform support for the SpacemiT K1 SoC, including early/final init hooks, cold boot handling, and CCI-550 snoop/DVM enablement. Co-authored-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Xianbin Zhu <xianbin.zhu@linux.spacemit.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/all/15169E392597D319+aOcKujCl8mz4XK4L@kernel.org/ [1] Link: https://lore.kernel.org/r/20250925-smt-k1-8-cores-v3-1-0885a8a70f8e@linux.spacemit.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-30platform: starfive: jh7110: Add starfive,jh7110s compatibleHal Feng1-0/+1
Add support for VisionFive 2 Lite board. Link: https://github.com/hal-feng/opensbi/commit/b7e46979a4feb293070094835ba4058b5e55d707 Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250906053638.69671-1-heinrich.schuchardt@canonical.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-30platform: generic: Add Andes QiLai SoC supportBen Zong-You Xie6-0/+96
Extend generic platform to support Andes QiLai SoC. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250814104024.3374698-1-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-16lib: utils/ipi: Convert IPI drivers as early driversAnup Patel1-5/+0
The fdt_ipi_init() is already called from generic_early_init() so let's convert IPI drivers as early drivers. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20250904052410.546818-4-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-16include: sbi: Remove platform specific IPI initAnup Patel6-60/+49
The platform specfic IPI init is not need anymore because using IPI device rating multiple IPI devices can be registered in any order as part of the platform specific early init. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20250904052410.546818-3-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-08-28generic: mips: support harts to boot from mips_warm_bootChao-ying Fu3-1/+18
We program reset base for harts (other than hart 0) to boot at mips_warm_boot that jumps to _start_warm. This helps to skip some code sequence to speed up. Signed-off-by: Chao-ying Fu <cfu@mips.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250723204010.9927-1-cfu@mips.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-08-28Fix license to compatible BSD-2-ClauseXiang W4-4/+4
OpenSBI is a BSD project. We need to modify some codes to compatible with BSD-2-Clause license. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Ben Zong-You Xie <ben717@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250728074334.372355-1-wxjstz@126.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-08-28platform: generic: Pack the FDT after applying fixupsSamuel Holland1-0/+2
This minimizes the size that will be reserved by the OS for the FDT, and it prevents the FDT buffer from containing uninitialized memory, which can be important for some simulation platforms and for attestation. Closes: https://github.com/riscv-software-src/opensbi/issues/388 Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250722233923.1356605-1-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-08-26platform: openpiton: Move openpiton platform from fpga to genericManuel Hernández Méndez7-84/+39
The OpenPiton framework has a generic PMU that is not used by OpenSBI. Due to OpenSBI’s build system we cannot directly reuse the generic platform functions, so move the OpenPiton platform to generic. Also due to the generic platform is where new features are added. Signed-off-by: Manuel Hernández Méndez <maherme.dev@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250813104759.33276-1-maherme.dev@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-07-22platform: openpiton: fix uninitialized plic_data structManuel Hernández Méndez1-1/+1
The plic_data struct was uninitialized. This led to misfunction behavior since it was subsequently assigned to the global plic struct, and some struct fields, such as flags and irqchip, contained random values. The fix proposes to initialize the plic_data to the global plic struct, so, after parsing the fdt, the fields of the struct will be set to the default values set in global plic struct definition, or the parsed values in the fdt, or zero. Fixes: 4c37451 ("platform: openpiton: Read the device configurations from device tree") Signed-off-by: Manuel Hernández Méndez <maherme.dev@gmail.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250708180914.1131-1-maherme.dev@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-17lib: sbi_platform: Add platform specific pmp_set() and pmp_disable()Chao-ying Fu1-0/+93
Allow platforms to implement platform specific PMP setup and PMP disable functions which are called before actual PMP CSRs are configured. Also, implement pmp_set() and pmp_disable() for MIPS P8700. Signed-off-by: Chao-ying Fu <cfu@mips.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250614172756.153902-1-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-14platform: generic: mips: add P8700Chao-ying Fu7-0/+517
Extend generic platform to support MIPS P8700. Signed-off-by: Chao-ying Fu <cfu@mips.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250522212141.3198-2-cfu@mips.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-20lib: utils: Fix fdt_mpxy_init() not returning error codeAlvin Chang1-2/+1
It seems that current implementation doesn't fail on fdt_mpxy_init(), because platforms might not have any MPXY devices. In fact, if there are no MPXY devices, fdt_driver_init_all() will return SBI_OK. More importantly, if there is any MPXY device which fails the initialization, OpenSBI must check the error code and stop the booting. Thus, this commit adds the return value for fdt_mpxy_init(). Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250430091007.3768180-1-alvinga@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-24lib: sbi: Set the scratch allocation to alignment to cacheline sizeRaj Vishwanathan1-0/+8
Set the scratch allocation alignment to cacheline size specified by riscv,cbom-block-size in the DTS file to avoid two atomic variables from the same cache line causing livelock on some platforms. If the cacheline is not specified, we set it a default value. Signed-off-by: Raj Vishwanathan <Raj.Vishwanathan@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20250423225045.267983-1-Raj.Vishwanathan@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-23lib: sbi_platform: Remove the vendor_ext_check hookSamuel Holland1-6/+0
Now that the generic platform only sets .vendor_ext_provider if the function is really implemented, there is no need for a separate hook to check if a vendor extension is implemented. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250325234342.711447-11-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-23platform: generic: Initialize overrides with fdt_driverSamuel Holland1-26/+1
In addition to deduplicating the code, this also improves the match selection logic to respect the priority order of the compatible strings, as implemented in commit 0ffe265fd969 ("lib: utils/fdt: Respect compatible string fallback priority"). Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250325234342.711447-9-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-23platform: generic: Remove platform override hooksSamuel Holland11-116/+16
Now that all of the overrides are modifying generic_platform_ops directly, remove the unused hooks and forwarding functions. The remaining members of struct platform_override match struct fdt_driver, so use that type instead. This allows a future commit to reuse the fdt_driver-based init function. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250325234342.711447-8-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-23platform: generic: Modify platform ops instead of using hooksSamuel Holland12-80/+160
Switch all existing platform overrides to use the helper pattern instead of the platform hooks. After this commit, only the .match_table and .init members of struct platform_override are used. There are two minor behavioral differences: - For Allwinner D1, fdt_add_cpu_idle_states() is now called before the body of generic_final_init(). This should have no functional impact. - For StarFive JH7110, if the /chosen/starfive,boot-hart-id property is missing, the code now falls back to using generic_coldboot_harts, instead of accepting any hart. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250325234342.711447-7-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-23platform: generic: Allow replacing platform operationsSamuel Holland2-20/+38
Currently the generic platform follows the middleware pattern: it implements the sbi_platform hooks, while providing its own set of hooks for further customization. This has a few disadvantages: each location where customization is needed requires a separate platform_override hook, including places where the generic function does nothing except forward to a platform_override hook, and the extra layer of function pointers adds runtime overhead. Let's restructure the generic platform to follow the helper pattern. Allow platform overrides to treat the generic platform as a template, adding or replacing the sbi_platform_operations as needed. Export the generic implementations, so they can be called as helpers from inside the override functions. With this pattern, the platform_override function pointers are replaced by direct calls, and the forwarding functions can be removed. The forwarding functions are not exported, since there is no reason for an override to call them. generic_vendor_ext_check() must be rewritten, since now there is a new way to override vendor_ext_provider. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250325234342.711447-6-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-23platform: generic: Add an init hook matching fdt_driverSamuel Holland3-7/+14
In preparation for reusing the fdt_driver code to match platform overrides, add a new .init hook matching the type signature from fdt_driver. This hook replaces the existing .fw_init hook, since it is called at roughly the same place in the init process. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250325234342.711447-5-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-23platform: generic: thead: Avoid casting away constSamuel Holland1-4/+4
struct fdt_match expects match data to be const. Follow this expectation so that no type casting is needed. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250325234342.711447-4-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-23platform: rzfive: Call andes_pma_setup_regions() only during cold bootSamuel Holland1-2/+10
This function accesses the FDT blob, which means it is only valid to call during cold boot, before a lower privilege level has an opportunity to clobber that memory. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250325234342.711447-3-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-23platform: generic: andes: Remove inline definitionsSamuel Holland1-16/+0
The addresses of these functions are used to set function pointers in struct platform_override, so it is not valid for them to be inline. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250325234342.711447-2-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-03-27lib: utils/serial: Add PXA UARTs supportJunhui Liu3-3/+7
The PXA variant of the uart8250 adds the UART Unit Enable bit (UUE) that needs to be set to enable the XScale PXA UART. And it is required for some RISC-V SoCs like the Spacemit K1 that implement the PXA UART. This introduces the "intel,xscale-uart" compatible to handle setting the UUE bit. Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250327-pxa-uart-support-v2-1-c4400c1fcd0b@pigmoral.tech Signed-off-by: Anup Patel <anup@brainfault.org>
2025-03-24lib: sbi: Use sbi_hart_count() and sbi_for_each_hartindex()Samuel Holland1-1/+1
Simplify the code and improve consistency by using the new macros where possible. sbi_hart_count() obsoletes sbi_scratch_last_hartindex(). Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2025-02-13lib: utils: Add MPXY RPMI mailbox driver for System MSI service groupAnup Patel1-0/+1
The supervisor software can directly receive most of the system MSIs except P2A doorbell and MSIs preferred to be handled in M-mode. Add MPXY RPMI mailbox client driver for the System MSI service group. Signed-off-by: Anup Patel <apatel@ventanamicro.com>
2025-02-13lib: utils: Split the FDT MPXY RPMI mailbox client into two partsAnup Patel1-0/+1
Instead of having one common FDT MPXY RPMI mailbox client drivers for various RPMI service groups, split this driver into two parts: 1) Common MPXY RPMI mailbox client library 2) MPXY driver for RPMI clock service group The above split enables having a separate MPXY driver for each RPMI clock service group and #1 (above) will allow code sharing between various MPXY RPMI drivers. Signed-off-by: Anup Patel <apatel@ventanamicro.com>
2025-02-12lib: utils: Initialize miscellaneous drivers in one passSamuel Holland3-14/+8
For driver subsystems that are not tightly integrated into the OpenSBI init sequence, it is not important that the drivers are initialized in any particular order. By putting all of these drivers in one array, they can all be initialized with a single pass through the devicetree. This saves about 10 ms of boot time on HiFive Unmatched. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2025-02-12platform: generic: thead: add Sophgo SG2044Inochi Amaoto1-10/+7
The Sophgo SG2044 is a new version of C920, although it supports sscofpmf, it still needs this pmu quirks its cores. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2025-02-12lib: utils:Check that hartid is validRaj Vishwanathan1-2/+2
It is possible that hartid may not be sequential and it should not be validated against SBI_HARTMASK_MAX_BITS. Instead we should check the index of the hartid, hart index, against SBI_HARTMASK_MAX_BITS. Signed-off-by: Raj Vishwanathan <Raj.Vishwanathan@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2025-01-30lib: sbi: pmu: fix usage of sbi_pmu_irq_bit()Clément Léger2-2/+1
While sbi_pmu_irq_bit() was used to delegate irq to S-mode, LCOFIP usage was still hardcoded in various places. This led to change the returned value of sbi_pmu_irq_bit() to be a bit number rather than a bit mask since it returns an 'int' and we need to obtain the bit number itself to handle it in the IRQs handlers. Add a similar function to return the irq mask which can also be used where the mask is required rather than the bit itself. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2024-12-21include: sbi: Fix compiling with C23 enabled compilersMichael Neuling1-1/+1
C23 pre-defines bool so we need to gate our defines. Signed-off-by: Michael Neuling <michaelneuling@tenstorrent.com> Reviewed-by: Anup Patel <anup@brainfault.org>
generated by cgit v1.1 at 2026-01-04 09:08:13 +0000