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6 daysplatform: generic: eyeq7h: enable ECC on L1 cacheHEADmasterVladimir Kondratiev1-0/+2
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-23-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips eyeq7h: prohibit accessing memory beyond DRAMVladimir Kondratiev1-1/+36
SBI code arranges domain PMP regions in a way that last entry is all-inclusive "0..~0 RWX" and the rest of entries are not programmed. This causes a problem for the eyeq7h. CPU can issue speculative prefetches to non-existent addresses. If this access goes to the system NOC, it is mis-interpreted as an access violation and error is reported, forcing system reset. To prevent such a speculative transaction to leave a CPU cluster, block it using PMP, by restricting memory region to physically present memory. To achieve this, on early init: - update flags for the last all-inclusive "0..~0 RWX" entry to be inaccessible MMIO. MMIO serves to set up PMA attributes to uncached non-prefetchable, preventing transactions to reach system NOC - add an all-permissive entry matching DRAM. Resulting memory regions: Domain0 Region00 : 0x0000000800100000-0x000000080013ffff M: (F,R,X) S/U: () Domain0 Region01 : 0x0000000800100000-0x00000008001fffff M: (F,R,W) S/U: () Domain0 Region02 : 0x0000000048700000-0x000000004870ffff M: (I,R,W) S/U: () Domain0 Region03 : 0x0000000067480000-0x000000006748ffff M: (I,R,W) S/U: () Domain0 Region04 : 0x0000000067500000-0x000000006750ffff M: (I,R,W) S/U: () Domain0 Region05 : 0x0000000048740000-0x000000004875ffff M: (I,R,W) S/U: () Domain0 Region06 : 0x00000000674c0000-0x00000000674dffff M: (I,R,W) S/U: () Domain0 Region07 : 0x0000000067540000-0x000000006755ffff M: (I,R,W) S/U: () Domain0 Region08 : 0x0000000000000000-0x000000007fffffff M: (I,R,W) S/U: (R,W) Domain0 Region09 : 0x0000000800000000-0x00000008ffffffff M: () S/U: (R,W,X) Domain0 Region10 : 0x0000001000000000-0x0000001fffffffff M: (I) S/U: (R,W) Domain0 Region11 : 0x0000000000000000-0xffffffffffffffff M: (I) S/U: () Here Region09 covers DRAM, region 11 set to non-accessible uncached no-prefetch for the entire address range Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-21-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips p8700: dump MMIO regionsVladimir Kondratiev2-0/+64
Debug print MMIO regions Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-20-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips eyeq7h: fix NCORE registers access from clusters 1..2Vladimir Kondratiev1-0/+7
CPU clusters 1 and 2 cannot access NCORE registers through AUX ports. AUX ports of clusters 1 and 2 are connected to NCORE through east port. East port has no access to NCORE registers address space. Re-route NCORE registers range to MEM port by re-configuring MMIO regions in the GCR. REsulting map is as below. Mind a gap between regions [1] and [2]; this gap covering NCORE registers now routed to the default MEM port Cluster 0: 4 MMIO regions [0] : 0x0000000000000000-0x000000001fff0000 AUX0 UC|UCA [1] : 0x0000000020000000-0x00000000677f0000 AUX0 ANY [2] : 0x0000000080000000-0x0000001fffff0000 AUX0 UC|UCA [3] : --disabled-- Cluster 1: 4 MMIO regions [0] : 0x0000000000000000-0x000000001fff0000 AUX0 UC|UCA [1] : 0x0000000020000000-0x00000000677f0000 AUX0 ANY [2] : 0x0000000080000000-0x0000001fffff0000 AUX0 UC|UCA [3] : --disabled-- Cluster 2: 4 MMIO regions [0] : 0x0000000000000000-0x000000001fff0000 AUX0 UC|UCA [1] : 0x0000000020000000-0x00000000677f0000 AUX0 ANY [2] : 0x0000000080000000-0x0000001fffff0000 AUX0 UC|UCA [3] : --disabled-- Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-19-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips eyeq7h: synchronize timers across clustersVladimir Kondratiev1-0/+17
Use eyeq7 specific method to synchronously restart architectural mtimer and eyeq7h specific high-resolution timer with common hardware trigger. This ensures all timers are precisely in sync Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-18-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips p8700: synchronize hi-res timersVladimir Kondratiev1-1/+17
There's high-resolution (1GHz) timer found in the p8700 cluster. This timer used for precise time measurement by platform specific software. Synchronize this proprietary timers to reference in cluster 0. Procedure borrowed from the aclint mtimer. Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-17-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips p8700: use SBI bitfield manipulator macrosVladimir Kondratiev2-3/+3
Switch to GENMASK, EXTRACT_BITFIELD, INSERT_BITFIELD Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-16-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips p8700: CPU clusters memrangesVladimir Kondratiev3-44/+58
Reserve memory regions for CPU clusters according to P8700 cluster memory layout. There's a set of components in the CPU cluster according to [1] [1] https://mips.com/wp-content/uploads/2025/11/P8700-F_Programmers_Reference_Manual-TM.pdf Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-15-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips p8700: cache geometry detectionVladimir Kondratiev2-0/+72
P8700 has a read-only cache configuration registers. Provide a CPU specific function to extract cache information. Use this information in the eyeq7h board for informational message Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-14-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips eyeq7h: deassert accelerator cluster resetsVladimir Kondratiev1-0/+16
On the EyeQ7H board, there's cluster level resets found in the accelerator OLBs. These resets should be deasserted once on boot and never used after Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-13-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips eyeq7h: detect accelerators cluster presenceVladimir Kondratiev1-0/+44
In the design, accelerator clusters ACC[01] and XNN[01] presence indicated by the OLB_WEST register OLB_WEST_TSTCSR. In the simulation environments, part (or all) accelerators may be not instantiated Disable clusters not present in the model, updating the DTB Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-12-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips eyeq7h: power up clusters with OLBVladimir Kondratiev1-0/+42
In the eyeq7h platform, there's extra power control for the CPU clusters. To enable cluster, it should be powered up using this OLB registers prior to accessing any cluster management registers Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-11-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips: add P8700 based "eyeq7h" and "boston"Vladimir Kondratiev4-201/+488
Refactor MIPS P8700 support, convert P8700 into a "CPU" and add 2 platforms using this CPU: - "boston" - FPGA platform developed by MIPS - "eyeq7h" - automotive platform by Mobileye Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-10-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips p8700: access CM registers via match dataVladimir Kondratiev1-13/+15
Modify the coherence manager register accessors to use the global variable p8700_cm_info instead of the statically declared GLOBAL_CM_BASE array. Also use p8700_cm_info to get the number of coherence managers and their base addresses in mips_p8700_early_init() and mips_p8700_nascent_init(). Clean up the hard-coded values in mips/board.h, access to the coherence manager is now fully based on information provided by platform compatible from the device tree. Signed-off-by: Benoît Monin <benoit.monin@bootlin.com> Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-9-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips p8700: Add match data for CM infoBenoît Monin1-1/+20
Introduce a structure p8700_cm_info holding the number of coherence managers and their base addresses found in a particular SoC. Declare a global pointer to the structure that is set in mips_p8700_platform_init(), based on the match data of the platform compatible. For the match data of the MIPS P8700, a single coherence manager with a base address of 0x16100000 is declared, identical to what is found in mips/board.h. For now, access to the coherence manager register is still based on the hard-coded values defined in mips/board.h. Signed-off-by: Benoît Monin <benoit.monin@bootlin.com> Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-8-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips p8700: use global CM addressesVladimir Kondratiev1-35/+24
In the multi-cluster system each cluster has its own CM (Coherency Manager). Every CM has its "global" memory address where it is accessible from any bus master. Initially, all CMs accessible from the local cluster using same "local" address. Transactions by local address are not routed through system bus and thus are faster. Remap CM in every cluster to the local address matching its global address. Then, every CM is always accessed using same address, but when transaction initiated from the local cluster it is routed internally. This removes need for 2 PMP regions covering local address access. CM accessor functions simplified because there's no need to detect whether transaction is local or global Access timer always in cluster 0 Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-7-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips p8700: faster core bootVladimir Kondratiev1-23/+30
When powering up cores, wait for power up to complete using tight loop. This saves 10ms delay observed for every core Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-6-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips p8700: fix powering up other clusterVladimir Kondratiev1-19/+10
While powering up cluster, only indication is bit in cluster power control. It used to wait for CORE0 in that cluster reach U5 state (non-coherent execution), this won't happen when only CM powered up without booting any core Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-5-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
6 daysplatform: generic: mips p8700: reserve memory for M-mode peripheralsVladimir Kondratiev1-37/+60
Reserve memory upfront in large well aligned chunks, to avoid problem with PMP granularity that is 64Kbytes for the p8700 CPU Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-4-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-21lib: Allow custom CSRs in csr_read_num() and csr_write_num()Anup Patel1-74/+2
Some of the platforms use platform specific CSR access functions for configuring implementation specific CSRs (such as PMA registers). Extend the common csr_read_num() and csr_write_num() to allow custom CSRs so that platform specific CSR access functions are not needed. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20250930153216.89853-1-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-08-28generic: mips: support harts to boot from mips_warm_bootChao-ying Fu3-1/+18
We program reset base for harts (other than hart 0) to boot at mips_warm_boot that jumps to _start_warm. This helps to skip some code sequence to speed up. Signed-off-by: Chao-ying Fu <cfu@mips.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250723204010.9927-1-cfu@mips.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-17lib: sbi_platform: Add platform specific pmp_set() and pmp_disable()Chao-ying Fu1-0/+93
Allow platforms to implement platform specific PMP setup and PMP disable functions which are called before actual PMP CSRs are configured. Also, implement pmp_set() and pmp_disable() for MIPS P8700. Signed-off-by: Chao-ying Fu <cfu@mips.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250614172756.153902-1-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-14platform: generic: mips: add P8700Chao-ying Fu2-0/+278
Extend generic platform to support MIPS P8700. Signed-off-by: Chao-ying Fu <cfu@mips.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250522212141.3198-2-cfu@mips.com Signed-off-by: Anup Patel <anup@brainfault.org>
generated by cgit v1.1 at 2026-03-03 12:02:24 +0000