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3 dayslib: utils/suspend: add Andes ATCSMU suspend driverHEADmasterBen Zong-You Xie1-0/+1
Implement a system-wide suspend driver for the Andes AE350 platform. This driver supports Andes-specific deep sleep (suspend to RAM) and light sleep (suspend to standby) functionalities via the ATCSMU. The major differences between deep sleep and light sleep are: - Power Domain and Resume Path: Deep sleep powers down the core domain. Consequently, harts waking from deep sleep resume from the reset vector. Light sleep utilizes clock gating to the core domain; harts maintain state and resume execution at the instruction immediately following the WFI instruction. - Primary Hart Wakeup: In both modes, the primary hart is woken by UART or RTC alarm interrupts. In deep sleep, the primary hart is additionally responsible for re-enabling the Last Level Cache (LLC) and restoring Andes-specific CSRs. - Secondary Hart Wakeup: In light sleep, secondary harts are woken by an IPI sent from the primary hart. In deep sleep, they are woken by an ATCSMU hardware wake-up command. Furthermore, secondary harts must restore Andes-specific CSRs when returning from deep sleep. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-6-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
3 dayslib: utils/cache: add Andes last level cache controllerBen Zong-You Xie1-0/+15
Introduce a FDT-based driver for the Andes Last Level Cache (LLC) controller to support cache maintenance operations. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-5-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
3 dayslib: utils/cache: add cache enable functionBen Zong-You Xie2-0/+24
Add functions to enable/disable the cache. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-4-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
3 dayslib: utils/hsm: factor out ATCSMU code into an HSM driverBen Zong-You Xie2-59/+49
Refactor ATCSMU (System Management Unit) support by moving it from a system utility into a dedicated FDT-based HSM driver. Key changes include: - Moving the functions in lib/utils/sys/atcsmu.c into the new HSM driver - Moving hart start and stop operations on AE350 platform into the new HSM driver - Converting the assembly-based functions in sleep.S to C code for the readability - Updating the ATCWDT200 driver Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-2-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-01-08include: sbi_scratch: fix typo sbi_scratch -> HART idLeo Yu-Chi Liang1-1/+1
Fix "sbi_scratch" to "HART id" to better reflect its purpose. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260107032602.1143819-1-ycliang@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-29include: Bump-up version to 1.8v1.8Anup Patel1-1/+1
Update the OpenSBI version to 1.8 as part of release preparation. Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-28include: Fix LLVM compile error in sbi_utils/hsm/fdt_hsm_sifive_inst.hAnup Patel1-2/+2
Currently, OpenSBI fails to compile for LLVM=1 using 2025.11.27 riscv-gnu-toolchain with the following error: In file included from opensbi/lib/utils/suspend/fdt_suspend_sifive_smc0.c:20: opensbi/include/sbi_utils/hsm/fdt_hsm_sifive_inst.h:17:23: error: expected instruction format 17 | __asm__ __volatile__(".insn 0xfc000073" ::: "memory"); | ^ <inline asm>:1:8: note: instantiated into assembly here 1 | .insn 0xfc000073 | ^ In file included from opensbi/lib/utils/suspend/fdt_suspend_sifive_smc0.c:20: opensbi/include/sbi_utils/hsm/fdt_hsm_sifive_inst.h:12:23: error: expected instruction format 12 | __asm__ __volatile__(".insn 0x30500073" ::: "memory"); | ^ <inline asm>:1:8: note: instantiated into assembly here 1 | .insn 0x30500073 | ^ 2 errors generated. To fix this compile error, use ".word" in-place ".insn". Fixes: 1514a327306b ("lib: utils/hsm: Add SiFive TMC0 driver") Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251227100916.327524-1-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-27include: riscv_asm: Optimize csr_xyz() macros to reduce stack usageBo Gan1-6/+6
When using debug builds, aka., DEBUG=1, csr_write_num() function can trigger stack overflow. This is caused by the large amount of macro expansion of csr_write(...), which, under debug builds, will generate massive amount of stack variables (tested with GCC 13.2.0). The issue is masked previously as we didn't have too many csr_write()'s before commit 55296fd27c0c, but now, it does overflow the default 4KB stack. The csr_read(relaxed) macros already use the "register" modifier to optimize stack usage (perhaps unknowingly?), so this patch just follows suit. Fixes: 55296fd27c0c ("lib: Allow custom CSRs in csr_read_num() and csr_write_num()") Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251216052528.18896-1-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-21lib: utils/serial: Support multiple UART8250 devicesBo Gan1-0/+16
Previously we assume only 1 UART8250 instance can be used. Now we support multiple instances by introducing counterpart functions to putc/getc/init which take an extra *dev parameter, and name them as uart8250_device_xyz() The original functions without the *dev parameter will operate on the default instance exactly the same as before, so no changes on the caller is required. Note: uart8250_device_init only does device initialization without the console registration logic. Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251218104243.562667-7-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-21lib: sbi: give platform choice of using single memregion to cover OpenSBIBo Gan1-0/+21
By default the OpenSBI itself is covered by 2 memregions for RX/RW sections. This is required by platforms with Smepmp to enforce proper permissions in M mode. Note: M-mode only regions can't have RWX permissions with Smepmp. Platforms with traditional PMPs won't be able to benefit from it, as both regions are effectively RWX in M mode, but usually it's harmless to so. Now we provide these platforms with an option to disable this logic. It saves 1 PMP entry. For platforms really in short of PMPs, it does make a difference. Note: Platform requesting single OpenSBI memregion must be using traditional (old) PMP. We expect the platform code to do the right thing. Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251218104243.562667-5-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-21lib: sbi_domain: make is_region_subset publicBo Gan1-0/+22
The helper function is renamed as sbi_domain_memregion_is_subset, and made public in header file. Also add a convenient helper of sbi_domain_for_each_memregion_idx. Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251218104243.562667-4-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-21lib: sbi_domain: add sbi_domain_get_oldpmp_flagsBo Gan1-0/+7
Factor out logic in `sbi_hart_oldpmp_configure` into function `sbi_domain_get_oldpmp_flags`, analogous to `sbi_domain_get_smepmp_flags`. Platform specific hart-protection implementation can now leverage it. Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251218104243.562667-3-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-21lib: sbi_hart_pmp: make sbi_hart_pmp_fence publicBo Gan1-0/+1
sbi_hart_pmp_fence can now be utilized by other hart-protection implementation. Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251218104243.562667-2-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-16lib: sbi: Expose __sbi_sfence_vma_all() functionAndrew Waterman1-0/+2
The __sbi_sfence_vma_all() can be shared by different parts of OpenSBI so rename __tlb_flush_all() to __sbi_sfence_vma_all() and make it global function. Signed-off-by: Andrew Waterman <andrew@sifive.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20251127112121.334023-2-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-16lib: sbi: Factor-out PMP programming into separate sourcesAnup Patel2-19/+23
The PMP programming is a significant part of sbi_hart.c so factor-out this into separate sources sbi_hart_pmp.c and sbi_hart_pmp.h for better maintainability. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20251209135235.423391-6-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-16lib: sbi: Replace sbi_hart_pmp_xyz() and sbi_hart_map/unmap_addr()Anup Patel1-6/+2
The sbi_hart_pmp_xyz() and sbi_hart_map/unmap_addr() functions can now be replaced by various sbi_hart_protection_xyz() functions. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20251209135235.423391-5-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-16lib: sbi: Introduce hart protection abstractionAnup Patel1-0/+100
Currently, PMP and ePMP are the only hart protection mechanisms available in OpenSBI but new protection mechanisms (such as Smmpt) will be added in the near future. To allow multiple hart protection mechanisms, introduce hart protection abstraction and related APIs. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20251209135235.423391-3-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-16lib: sbi: Introduce sbi_hart_pmp_unconfigure() functionAnup Patel1-0/+1
Currently, the unconfiguring PMP is implemented directly inside switch_to_next_domain_context() whereas rest of the PMP programming is done via functions implemented in sbi_hart.c. Introduce a separate sbi_hart_pmp_unconfigure() function so that all PMP programming is in one place. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20251209135235.423391-2-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-15include: sbi: Ignore rs1 and rd fields in FENCE.TSO.Benedikt Freisen1-1/+1
While FENCE.TSO is only specified with them set to zero, it is a special case of FENCE, which needs to ignore these otherwise reserved fields, but in some implementations, namely XuanTie C906 and C910, apparently does not. See the RISCVuzz paper by Thomas et al. for details. Signed-off-by: Benedikt Freisen <b.freisen@gmx.net> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251114203842.13396-5-b.freisen@gmx.net Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-15include: sbi: Fix tab alignment.Benedikt Freisen1-15/+15
A previous editor or formatter script appears to have been confused by a diff view, where the prepended + or - changes the way tabs are displayed. Since it is the file itself that matters, adjust that accordingly. Signed-off-by: Benedikt Freisen <b.freisen@gmx.net> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251114203842.13396-4-b.freisen@gmx.net Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-15include: sbi: Make "s8" actually signed.Benedikt Freisen1-1/+1
Since plain "char" is implicitly unsigned on RISC-V, "s8" should be an alias for "signed char". Signed-off-by: Benedikt Freisen <b.freisen@gmx.net> Reviewed-by: Radim Krčmář <rkrcmar@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251114203842.13396-2-b.freisen@gmx.net Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-08lib: sbi: Enable Ssqosid Ext using mstateen0Chen Pei2-0/+7
The QoS Identifiers extension (Ssqosid) introduces the srmcfg register, which configures a hart with two identifiers: a Resource Control ID (RCID) and a Monitoring Counter ID (MCID). These identifiers accompany each request issued by the hart to shared resource controllers. If extension Smstateen is implemented together with Ssqosid, then Ssqosid also requires the SRMCFG bit in mstateen0 to be implemented. If mstateen0.SRMCFG is 0, attempts to access srmcfg in privilege modes less privileged than M-mode raise an illegal-instruction exception. If mstateen0.SRMCFG is 1 or if extension Smstateen is not implemented, attempts to access srmcfg when V=1 raise a virtual-instruction exception. This extension can be found in the RISC-V Instruction Set Manual: https://github.com/riscv/riscv-isa-manual Changes in v5: - Remove SBI_HART_EXT_SSQOSID dependency SBI_HART_PRIV_VER_1_12 Changes in v4: - Remove extraneous parentheses around SMSTATEEN0_SRMCFG Changes in v3: - Check SBI_HART_EXT_SSQOSID when swapping SRMCFG Changes in v2: - Remove trap-n-detect - Context switch CSR_SRMCFG Signed-off-by: Chen Pei <cp0613@linux.alibaba.com> Reviewed-by: Radim Krčmář <rkrcmar@ventanamicro.com> Link: https://lore.kernel.org/r/20251114115722.1831-1-cp0613@linux.alibaba.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-01lib: sbi_pmu: Fix xINH bits configuringShifrin Dmitry1-0/+9
Before this patch sbi_pmu_ctr_start() ignores flags received in sbi_pmu_ctr_cfg_match() including inhibit ones. To prevent it, save flags together with event_data and use them both in sbi_pmu_ctr_start(). Fixes: 1db95da2997b ("lib: sbi: sbi_pmu: fixed hw counters start for hart") Signed-off-by: Shifrin Dmitry <dmitry.shifrin@syntacore.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251110113140.80561-1-dmitry.shifrin@syntacore.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-04lib: utils: Add MPXY RPMI mailbox driver for performanceJoshua Yeong1-0/+118
Add MPXY RPMI mailbox driver for performance. Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com> Reviewed-by: Rahul Pathak <rpathak@ventanamicro.com> Link: https://lore.kernel.org/r/20251013153138.1574512-4-joshua.yeong@starfivetech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-04lib: utils: Add MPXY RPMI mailbox driver for device powerJoshua Yeong1-0/+45
Add MPXY RPMI mailbox driver for device power. Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com> Reviewed-by: Rahul Pathak <rpathak@ventanamicro.com> Link: https://lore.kernel.org/r/20251013153138.1574512-3-joshua.yeong@starfivetech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-04lib: utils: Add MPXY RPMI mailbox driver for voltageJoshua Yeong1-0/+81
Add voltage service group for RPMI/MPXY support Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com> Reviewed-by: Rahul Pathak <rpathak@ventanamicro.com> Link: https://lore.kernel.org/r/20251013153138.1574512-2-joshua.yeong@starfivetech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-02lib: sbi: sbi_hart: track firmware PMP entries for SmePMPYu-Chien Peter Lin1-0/+1
Add fw_smepmp_ids bitmap to track PMP entries that protect firmware regions. Allow us to preserve these critical entries across domain transitions and check inconsistent firmware entry allocation. Also add sbi_hart_smepmp_is_fw_region() helper function to query whether a given SmePMP entry protects firmware regions. Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251008084444.3525615-8-peter.lin@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-02lib: sbi_domain: ensure consistent firmware PMP entriesYu-Chien Peter Lin1-0/+3
During domain context switches, all PMP entries are reconfigured which can clear firmware access permissions, causing M-mode access faults under SmePMP. Sort domain regions to place firmware regions first, ensuring consistent firmware PMP entries so they won't be revoked during domain context switches. Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251008084444.3525615-7-peter.lin@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-02lib: sbi_domain: add SBI_DOMAIN_MEMREGION_FW memregion flagYu-Chien Peter Lin1-0/+1
Add a new memregion flag, SBI_DOMAIN_MEMREGION_FW and mark the OpenSBI code and data regions. Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251008084444.3525615-6-peter.lin@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-02lib: sbi_hart: move sbi_hart_get_smepmp_flags() to sbi_domainYu-Chien Peter Lin1-0/+7
Move sbi_hart_get_smepmp_flags() from sbi_hart.c to sbi_domain.c and rename it to sbi_domain_get_smepmp_flags() to better reflect its purpose of converting domain memory region flags to PMP configuration. Also removes unused parameters (scratch and dom). Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251008084444.3525615-2-peter.lin@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils/suspend: Add SiFive SMC0 driverNick Hu1-0/+14
The SiFive SMC0 controls the clock and power domain of the core complex on the SiFive platform. The core complex enters the low power state after the secondary cores enter the tile power gating and last core execute the `CEASE` instruction with the corresponding SMC0 configurations. The devices that inside both tile power domain and core complex power domain will be off, including caches and timer. Therefore we need to flush the last level cache before entering the core complex power gating and update the timer after waking up. Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-12-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: sbi: Add system_resume callback for restoring the systemNick Hu1-0/+7
The last core who performs the system suspend is responsible for restoring the system after waking up. Add the system_resume callback for restoring the system from suspend. Suggested-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-11-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils/timer: Expose timer update functionNick Hu1-0/+5
Exposing the ACLINT timer update APIs so the user can update the mtimer after waking up from the non-retentive suspend. Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-10-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils/hsm: Add SiFive TMC0 driverNick Hu1-0/+20
The SiFive TMC0 controls the tile power domains on SiFive platform. The CPU enters the low power state via the `CEASE` instruction after configuring the TMC0. Any devices that inside the tile power domain will be power gated, including the private cache. Therefore flushing the private cache before entering the low power state. Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-9-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: sbi: Extends sbi_ipi_raw_send() to use all available IPI devicesNick Hu1-1/+1
A platform may contain multiple IPI devices. In certain use cases, such as power management, it may be necessary to send an IPI through a specific device to wake up a CPU. For example, if an IMSIC is powered down and reset, the core cannot receive IPIs from it, so the wake-up must instead be triggered through the CLINT. Suggested-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-8-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils/irqchip: Add APLIC restore functionNick Hu1-0/+3
Since the APLIC may enter a reset state upon system wake-up from a platform low power state, adding a restore function to reinitialize the APLIC. Reviewed-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-7-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: sbi: Add SiFive proprietary xsfceaseNick Hu1-0/+2
Using ISA string "xsfcease" to detect the support of the custom instruction "CEASE". Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-6-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: sbi: Add SiFive proprietary xsfcflushdloneNick Hu1-0/+2
Using ISA string "xsfcflushdlone" to detect the support of the SiFive L1D cache flush custom instruction. Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-5-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils/cache: Add fdt cmo helpersNick Hu1-0/+40
Add the helpers to build up the cache hierarchy via FDT and provide some cmo functions for the user who want to flush the entire cache. Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-4-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils: Add FDT cache libraryNick Hu1-0/+34
Add the FDT cache library so we can build up the cache topology via the 'next-level-cache' DT property. Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Co-developed-by: Andy Chiu <andy.chiu@sifive.com> Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-2-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils: Add cache flush libraryNick Hu1-0/+69
The current RISC-V CMO only defines how to flush a cache block. However, certain use cases, such as power management, may require flushing the entire cache. Therefore, a framework is being introduced to allow vendors to flush the entire cache using their own methods. Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-1-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-21lib: Allow custom CSRs in csr_read_num() and csr_write_num()Anup Patel1-0/+34
Some of the platforms use platform specific CSR access functions for configuring implementation specific CSRs (such as PMA registers). Extend the common csr_read_num() and csr_write_num() to allow custom CSRs so that platform specific CSR access functions are not needed. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20250930153216.89853-1-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-16lib: utils/ipi: Convert IPI drivers as early driversAnup Patel1-26/+0
The fdt_ipi_init() is already called from generic_early_init() so let's convert IPI drivers as early drivers. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20250904052410.546818-4-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-16include: sbi: Remove platform specific IPI initAnup Patel1-17/+0
The platform specfic IPI init is not need anymore because using IPI device rating multiple IPI devices can be registered in any order as part of the platform specific early init. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20250904052410.546818-3-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-16lib: sbi: Introduce IPI device ratingAnup Patel1-2/+5
A platform can have multiple IPI devices (such as ACLINT MSWI, AIA IMSIC, etc). Currently, OpenSBI rely on platform calling the sbi_ipi_set_device() function in correct order and prefer the first avaiable IPI device which is fragile. Instead of the above, introduce IPI device rating and prefer the highest rated IPI device. This further allows extending the sbi_ipi_raw_clear() to clear all available IPI devices. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Tested-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20250904052410.546818-2-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-01lib: sbi_list: Add a helper for reverse list iterationSamuel Holland1-0/+11
Some use cases require iterating through a list in both directions. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Tested-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250617032306.1494528-2-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-08-28dbtr: Add support for icount trigger typeJesse Taube1-0/+44
The linux kernel needs icount to implement hardware breakpoints. Signed-off-by: Jesse Taube <jesse@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250724183120.1822667-1-jesse@rivosinc.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-07-22include: sbi: Remove unused (LOG_)REGBYTESJessica Clarke1-7/+0
These are no longer used, so remove them. Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250709232932.37622-3-jrtc27@jrtc27.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-07-22include: sbi: Use array for struct sbi_trap_regs and GET/SET macrosJessica Clarke2-81/+92
Rather than hand-rolling scaled pointer arithmetic with casts and shifts, let the compiler do so by indexing an array of GPRs, taking advantage of the language's type system to scale based on whatever type the register happens to be. This makes it easier to support CHERI where the registers are capabilities, not plain integers, and so this pointer arithmetic would need to change (and currently REGBYTES is both the size of a register and the size of an integer word upstream). Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250709232932.37622-1-jrtc27@jrtc27.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-07-21include: sbi: Don't use #pragma when preprocessing device tree sourcesJessica Clarke1-0/+2
Since this persists in the preprocessed output (so that it can affect the subsequent compilation), it ends up in the input to dtc and is a syntax error, breaking the k210 build. Ideally we wouldn't add the -include flag to DTSCPPFLAGS in the first place as this header is wholly pointless there, but that's a more invasive build system change compared to just making this header safe to include there. Fixes: 86c01a73ff9d ("lib: sbi: Avoid GOT indirection for global symbol references") Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Xiang W <wxjstz@126.com> Reviewed-by: Xiang W <wxjstz@126.com> Link: https://lore.kernel.org/r/20250709232840.37551-1-jrtc27@jrtc27.com Signed-off-by: Anup Patel <anup@brainfault.org>
generated by cgit v1.1 at 2026-02-14 05:40:56 +0000