aboutsummaryrefslogtreecommitdiff
path: root/include
AgeCommit message (Collapse)AuthorFilesLines
2026-04-08include: sbi_bitmap: add bitmap_empty() functionYu-Chien Peter Lin1-0/+16
Add bitmap_empty() to check if bitmap has no bits set. Unlike bitmap_weight() which calls sbi_popcount() on every word, bitmap_empty() uses simple non-zero comparisons with early exit. Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260311125116.1401002-1-peter.lin@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-04-06lib: utils: Add MPXY client driver for RPMI MM service groupRanbir Singh1-0/+37
Add necessary infra for implementing RPMI Management Mode service group on platform microcontroller. Co-authored-by: Sunil V L <sunilvl@oss.qualcomm.com> Signed-off-by: Ranbir Singh <ranbir.singh@oss.qualcomm.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260225061347.1396504-1-ranbir.singh@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: sbi_irqchip: Allow registering interrupt handlersAnup Patel1-1/+55
To handle external interrupts in M-mode, the sbi_irqchip framework must allow registering interrupt handlers from device drivers. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-9-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: sbi_irqchip: Associate 32-bit unique ID for each irqchip deviceAnup Patel1-0/+6
Allow locating irqchip device instance using a unique 32-bit ID. This 32-bit unique ID can be set by the irqchip driver at the time of adding irqchip device. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-8-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: utils/irqchip: Add unique_id to plic, aplic, and imsic dataAnup Patel3-0/+3
Add a 32-bit unique ID to plic, aplic, and imsic data which can be used to differentiate multiple irqchip devices. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-7-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: sbi_irqchip: Support irqchip device targetting subset of hartsAnup Patel1-2/+6
It is possible to have platform where an irqchip device targets a subset of harts and there are multiple irqchip devices to cover all harts. To support this scenario: 1) Add target_harts hartmask to struct sbi_irqchip_device which represents the set of harts targetted by the irqchip device 2) Call warm_init() and process_hwirqs() callbacks of an irqchip device on a hart only if irqchip device targets that particular hart Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-6-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: utils/irqchip: Add IDC to hartindex map in struct aplic_dataAnup Patel1-0/+1
A platform can have multiple APLICs in direct-mode targetting different subset of harts. Add APLIC ID to hartindex map in struct aplic_data to capture the set of harts targeted by a given APLIC in direct-mode. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-5-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: sbi_irqchip: Rename irq_handle() callback to process_hwirqs()Anup Patel1-2/+2
The irq_handle() callback of irqchip device is meant to process hardware interrupt of the irqchip hence rename it accordingly. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-3-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: sbi_irqchip: Use chip as variable name for irqchip deviceAnup Patel1-2/+2
The irqchip device represents an interrupt controller so use chip as variable name instead of dev. This will avoid confusion as the sbi_irqchip framework grows. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-2-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-09lib: sbi: Fix undefined behavior in signed shifts in sbi_hart.cMarcos Oduardo1-1/+1
UBSan detected undefined behavior in sbi_hart.c and sbi_fwft.c (in the case of sbi_fwft.c, the bug comes from a macro call defined at sbi_ecall_interface.h) caused by shifting a signed integer into the sign bit (1 << 31) This can be fixed by using the 1UL literal, ensuring defined arithmetic. Please let me know if there’s any other most suitable solution for this bug. Signed-off-by: Marcos Oduardo <marcos.oduardo@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223001202.284612-1-marcos.oduardo@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-09include: sbi: Fix illegal shift in sbi_domain.hMarcos Oduardo1-2/+4
In sbi_domain.h, when checking if a memory region is a subset of another, an undefined behavior arithmetic operation was caught when sanitizing with UBSan (shift exponent __riscv_xlen). This patch adds a check to handle the case where the region order is __riscv_xlen, avoiding the illegal shift and ensuring the operation remains defined. Please let me know if there’s any other most suitable solution for this bug. Signed-off-by: Marcos Oduardo <marcos.oduardo@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260222235219.276432-1-marcos.oduardo@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-21lib: sbi_pmu: Add FW counter index validation when reading high bits on RV64James Raphael Tiovalen1-1/+1
Currently, when we attempt to read the upper 32 bits of a firmware counter on RV64 or higher, we just set `sbiret.value` to 0 without validating the counter index. The SBI specification requires us to set `sbiret.error` to `SBI_ERR_INVALID_PARAM` if the counter index points to a hardware counter or an invalid counter. Add a validation check to ensure compliance with the specification on RV64 or higher. Fixes: 51951d9e9af8 ("lib: sbi_pmu: Implement sbi_pmu_counter_fw_read_hi") Signed-off-by: James Raphael Tiovalen <jamestiotio@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260125090643.190748-1-jamestiotio@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-20lib: utils/serial: Add support for Altera JTAG UARTIcenowy Zheng1-0/+17
Altera provides a JTAG UART core that provides virtual UART over JTAG and can coexist with their virtual JTAG. [1] This core has already been supported by Linux and the programming interface has always been stable. Add support for it to OpenSBI to ease JTAG prototype bringing up. The driver follows the device tree binding in mainline Linux. [2] [1] https://docs.altera.com/r/docs/683130/25.3/embedded-peripherals-ip-user-guide/jtag-uart-core [2] https://github.com/torvalds/linux/blob/v6.19-rc1/Documentation/devicetree/bindings/serial/altr%2Cjuart-1.0.yaml Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260104065506.70182-1-zhengxingda@iscas.ac.cn Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-20firmware: Initialize stack guard via ZkrXiang W1-0/+10
Try to initialize stack protection guard via the zkr extension. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260104051812.128496-1-wxjstz@126.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-11lib: utils/suspend: add Andes ATCSMU suspend driverBen Zong-You Xie1-0/+1
Implement a system-wide suspend driver for the Andes AE350 platform. This driver supports Andes-specific deep sleep (suspend to RAM) and light sleep (suspend to standby) functionalities via the ATCSMU. The major differences between deep sleep and light sleep are: - Power Domain and Resume Path: Deep sleep powers down the core domain. Consequently, harts waking from deep sleep resume from the reset vector. Light sleep utilizes clock gating to the core domain; harts maintain state and resume execution at the instruction immediately following the WFI instruction. - Primary Hart Wakeup: In both modes, the primary hart is woken by UART or RTC alarm interrupts. In deep sleep, the primary hart is additionally responsible for re-enabling the Last Level Cache (LLC) and restoring Andes-specific CSRs. - Secondary Hart Wakeup: In light sleep, secondary harts are woken by an IPI sent from the primary hart. In deep sleep, they are woken by an ATCSMU hardware wake-up command. Furthermore, secondary harts must restore Andes-specific CSRs when returning from deep sleep. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-6-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-11lib: utils/cache: add Andes last level cache controllerBen Zong-You Xie1-0/+15
Introduce a FDT-based driver for the Andes Last Level Cache (LLC) controller to support cache maintenance operations. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-5-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-11lib: utils/cache: add cache enable functionBen Zong-You Xie2-0/+24
Add functions to enable/disable the cache. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-4-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-11lib: utils/hsm: factor out ATCSMU code into an HSM driverBen Zong-You Xie2-59/+49
Refactor ATCSMU (System Management Unit) support by moving it from a system utility into a dedicated FDT-based HSM driver. Key changes include: - Moving the functions in lib/utils/sys/atcsmu.c into the new HSM driver - Moving hart start and stop operations on AE350 platform into the new HSM driver - Converting the assembly-based functions in sleep.S to C code for the readability - Updating the ATCWDT200 driver Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-2-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-01-08include: sbi_scratch: fix typo sbi_scratch -> HART idLeo Yu-Chi Liang1-1/+1
Fix "sbi_scratch" to "HART id" to better reflect its purpose. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260107032602.1143819-1-ycliang@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-29include: Bump-up version to 1.8v1.8Anup Patel1-1/+1
Update the OpenSBI version to 1.8 as part of release preparation. Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-28include: Fix LLVM compile error in sbi_utils/hsm/fdt_hsm_sifive_inst.hAnup Patel1-2/+2
Currently, OpenSBI fails to compile for LLVM=1 using 2025.11.27 riscv-gnu-toolchain with the following error: In file included from opensbi/lib/utils/suspend/fdt_suspend_sifive_smc0.c:20: opensbi/include/sbi_utils/hsm/fdt_hsm_sifive_inst.h:17:23: error: expected instruction format 17 | __asm__ __volatile__(".insn 0xfc000073" ::: "memory"); | ^ <inline asm>:1:8: note: instantiated into assembly here 1 | .insn 0xfc000073 | ^ In file included from opensbi/lib/utils/suspend/fdt_suspend_sifive_smc0.c:20: opensbi/include/sbi_utils/hsm/fdt_hsm_sifive_inst.h:12:23: error: expected instruction format 12 | __asm__ __volatile__(".insn 0x30500073" ::: "memory"); | ^ <inline asm>:1:8: note: instantiated into assembly here 1 | .insn 0x30500073 | ^ 2 errors generated. To fix this compile error, use ".word" in-place ".insn". Fixes: 1514a327306b ("lib: utils/hsm: Add SiFive TMC0 driver") Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251227100916.327524-1-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-27include: riscv_asm: Optimize csr_xyz() macros to reduce stack usageBo Gan1-6/+6
When using debug builds, aka., DEBUG=1, csr_write_num() function can trigger stack overflow. This is caused by the large amount of macro expansion of csr_write(...), which, under debug builds, will generate massive amount of stack variables (tested with GCC 13.2.0). The issue is masked previously as we didn't have too many csr_write()'s before commit 55296fd27c0c, but now, it does overflow the default 4KB stack. The csr_read(relaxed) macros already use the "register" modifier to optimize stack usage (perhaps unknowingly?), so this patch just follows suit. Fixes: 55296fd27c0c ("lib: Allow custom CSRs in csr_read_num() and csr_write_num()") Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251216052528.18896-1-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-21lib: utils/serial: Support multiple UART8250 devicesBo Gan1-0/+16
Previously we assume only 1 UART8250 instance can be used. Now we support multiple instances by introducing counterpart functions to putc/getc/init which take an extra *dev parameter, and name them as uart8250_device_xyz() The original functions without the *dev parameter will operate on the default instance exactly the same as before, so no changes on the caller is required. Note: uart8250_device_init only does device initialization without the console registration logic. Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251218104243.562667-7-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-21lib: sbi: give platform choice of using single memregion to cover OpenSBIBo Gan1-0/+21
By default the OpenSBI itself is covered by 2 memregions for RX/RW sections. This is required by platforms with Smepmp to enforce proper permissions in M mode. Note: M-mode only regions can't have RWX permissions with Smepmp. Platforms with traditional PMPs won't be able to benefit from it, as both regions are effectively RWX in M mode, but usually it's harmless to so. Now we provide these platforms with an option to disable this logic. It saves 1 PMP entry. For platforms really in short of PMPs, it does make a difference. Note: Platform requesting single OpenSBI memregion must be using traditional (old) PMP. We expect the platform code to do the right thing. Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251218104243.562667-5-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-21lib: sbi_domain: make is_region_subset publicBo Gan1-0/+22
The helper function is renamed as sbi_domain_memregion_is_subset, and made public in header file. Also add a convenient helper of sbi_domain_for_each_memregion_idx. Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251218104243.562667-4-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-21lib: sbi_domain: add sbi_domain_get_oldpmp_flagsBo Gan1-0/+7
Factor out logic in `sbi_hart_oldpmp_configure` into function `sbi_domain_get_oldpmp_flags`, analogous to `sbi_domain_get_smepmp_flags`. Platform specific hart-protection implementation can now leverage it. Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251218104243.562667-3-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-21lib: sbi_hart_pmp: make sbi_hart_pmp_fence publicBo Gan1-0/+1
sbi_hart_pmp_fence can now be utilized by other hart-protection implementation. Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251218104243.562667-2-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-16lib: sbi: Expose __sbi_sfence_vma_all() functionAndrew Waterman1-0/+2
The __sbi_sfence_vma_all() can be shared by different parts of OpenSBI so rename __tlb_flush_all() to __sbi_sfence_vma_all() and make it global function. Signed-off-by: Andrew Waterman <andrew@sifive.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20251127112121.334023-2-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-16lib: sbi: Factor-out PMP programming into separate sourcesAnup Patel2-19/+23
The PMP programming is a significant part of sbi_hart.c so factor-out this into separate sources sbi_hart_pmp.c and sbi_hart_pmp.h for better maintainability. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20251209135235.423391-6-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-16lib: sbi: Replace sbi_hart_pmp_xyz() and sbi_hart_map/unmap_addr()Anup Patel1-6/+2
The sbi_hart_pmp_xyz() and sbi_hart_map/unmap_addr() functions can now be replaced by various sbi_hart_protection_xyz() functions. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20251209135235.423391-5-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-16lib: sbi: Introduce hart protection abstractionAnup Patel1-0/+100
Currently, PMP and ePMP are the only hart protection mechanisms available in OpenSBI but new protection mechanisms (such as Smmpt) will be added in the near future. To allow multiple hart protection mechanisms, introduce hart protection abstraction and related APIs. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20251209135235.423391-3-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-16lib: sbi: Introduce sbi_hart_pmp_unconfigure() functionAnup Patel1-0/+1
Currently, the unconfiguring PMP is implemented directly inside switch_to_next_domain_context() whereas rest of the PMP programming is done via functions implemented in sbi_hart.c. Introduce a separate sbi_hart_pmp_unconfigure() function so that all PMP programming is in one place. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20251209135235.423391-2-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-15include: sbi: Ignore rs1 and rd fields in FENCE.TSO.Benedikt Freisen1-1/+1
While FENCE.TSO is only specified with them set to zero, it is a special case of FENCE, which needs to ignore these otherwise reserved fields, but in some implementations, namely XuanTie C906 and C910, apparently does not. See the RISCVuzz paper by Thomas et al. for details. Signed-off-by: Benedikt Freisen <b.freisen@gmx.net> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251114203842.13396-5-b.freisen@gmx.net Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-15include: sbi: Fix tab alignment.Benedikt Freisen1-15/+15
A previous editor or formatter script appears to have been confused by a diff view, where the prepended + or - changes the way tabs are displayed. Since it is the file itself that matters, adjust that accordingly. Signed-off-by: Benedikt Freisen <b.freisen@gmx.net> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251114203842.13396-4-b.freisen@gmx.net Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-15include: sbi: Make "s8" actually signed.Benedikt Freisen1-1/+1
Since plain "char" is implicitly unsigned on RISC-V, "s8" should be an alias for "signed char". Signed-off-by: Benedikt Freisen <b.freisen@gmx.net> Reviewed-by: Radim Krčmář <rkrcmar@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251114203842.13396-2-b.freisen@gmx.net Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-08lib: sbi: Enable Ssqosid Ext using mstateen0Chen Pei2-0/+7
The QoS Identifiers extension (Ssqosid) introduces the srmcfg register, which configures a hart with two identifiers: a Resource Control ID (RCID) and a Monitoring Counter ID (MCID). These identifiers accompany each request issued by the hart to shared resource controllers. If extension Smstateen is implemented together with Ssqosid, then Ssqosid also requires the SRMCFG bit in mstateen0 to be implemented. If mstateen0.SRMCFG is 0, attempts to access srmcfg in privilege modes less privileged than M-mode raise an illegal-instruction exception. If mstateen0.SRMCFG is 1 or if extension Smstateen is not implemented, attempts to access srmcfg when V=1 raise a virtual-instruction exception. This extension can be found in the RISC-V Instruction Set Manual: https://github.com/riscv/riscv-isa-manual Changes in v5: - Remove SBI_HART_EXT_SSQOSID dependency SBI_HART_PRIV_VER_1_12 Changes in v4: - Remove extraneous parentheses around SMSTATEEN0_SRMCFG Changes in v3: - Check SBI_HART_EXT_SSQOSID when swapping SRMCFG Changes in v2: - Remove trap-n-detect - Context switch CSR_SRMCFG Signed-off-by: Chen Pei <cp0613@linux.alibaba.com> Reviewed-by: Radim Krčmář <rkrcmar@ventanamicro.com> Link: https://lore.kernel.org/r/20251114115722.1831-1-cp0613@linux.alibaba.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-01lib: sbi_pmu: Fix xINH bits configuringShifrin Dmitry1-0/+9
Before this patch sbi_pmu_ctr_start() ignores flags received in sbi_pmu_ctr_cfg_match() including inhibit ones. To prevent it, save flags together with event_data and use them both in sbi_pmu_ctr_start(). Fixes: 1db95da2997b ("lib: sbi: sbi_pmu: fixed hw counters start for hart") Signed-off-by: Shifrin Dmitry <dmitry.shifrin@syntacore.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251110113140.80561-1-dmitry.shifrin@syntacore.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-04lib: utils: Add MPXY RPMI mailbox driver for performanceJoshua Yeong1-0/+118
Add MPXY RPMI mailbox driver for performance. Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com> Reviewed-by: Rahul Pathak <rpathak@ventanamicro.com> Link: https://lore.kernel.org/r/20251013153138.1574512-4-joshua.yeong@starfivetech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-04lib: utils: Add MPXY RPMI mailbox driver for device powerJoshua Yeong1-0/+45
Add MPXY RPMI mailbox driver for device power. Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com> Reviewed-by: Rahul Pathak <rpathak@ventanamicro.com> Link: https://lore.kernel.org/r/20251013153138.1574512-3-joshua.yeong@starfivetech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-04lib: utils: Add MPXY RPMI mailbox driver for voltageJoshua Yeong1-0/+81
Add voltage service group for RPMI/MPXY support Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com> Reviewed-by: Rahul Pathak <rpathak@ventanamicro.com> Link: https://lore.kernel.org/r/20251013153138.1574512-2-joshua.yeong@starfivetech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-02lib: sbi: sbi_hart: track firmware PMP entries for SmePMPYu-Chien Peter Lin1-0/+1
Add fw_smepmp_ids bitmap to track PMP entries that protect firmware regions. Allow us to preserve these critical entries across domain transitions and check inconsistent firmware entry allocation. Also add sbi_hart_smepmp_is_fw_region() helper function to query whether a given SmePMP entry protects firmware regions. Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251008084444.3525615-8-peter.lin@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-02lib: sbi_domain: ensure consistent firmware PMP entriesYu-Chien Peter Lin1-0/+3
During domain context switches, all PMP entries are reconfigured which can clear firmware access permissions, causing M-mode access faults under SmePMP. Sort domain regions to place firmware regions first, ensuring consistent firmware PMP entries so they won't be revoked during domain context switches. Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251008084444.3525615-7-peter.lin@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-02lib: sbi_domain: add SBI_DOMAIN_MEMREGION_FW memregion flagYu-Chien Peter Lin1-0/+1
Add a new memregion flag, SBI_DOMAIN_MEMREGION_FW and mark the OpenSBI code and data regions. Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251008084444.3525615-6-peter.lin@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-02lib: sbi_hart: move sbi_hart_get_smepmp_flags() to sbi_domainYu-Chien Peter Lin1-0/+7
Move sbi_hart_get_smepmp_flags() from sbi_hart.c to sbi_domain.c and rename it to sbi_domain_get_smepmp_flags() to better reflect its purpose of converting domain memory region flags to PMP configuration. Also removes unused parameters (scratch and dom). Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251008084444.3525615-2-peter.lin@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils/suspend: Add SiFive SMC0 driverNick Hu1-0/+14
The SiFive SMC0 controls the clock and power domain of the core complex on the SiFive platform. The core complex enters the low power state after the secondary cores enter the tile power gating and last core execute the `CEASE` instruction with the corresponding SMC0 configurations. The devices that inside both tile power domain and core complex power domain will be off, including caches and timer. Therefore we need to flush the last level cache before entering the core complex power gating and update the timer after waking up. Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-12-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: sbi: Add system_resume callback for restoring the systemNick Hu1-0/+7
The last core who performs the system suspend is responsible for restoring the system after waking up. Add the system_resume callback for restoring the system from suspend. Suggested-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-11-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils/timer: Expose timer update functionNick Hu1-0/+5
Exposing the ACLINT timer update APIs so the user can update the mtimer after waking up from the non-retentive suspend. Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-10-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils/hsm: Add SiFive TMC0 driverNick Hu1-0/+20
The SiFive TMC0 controls the tile power domains on SiFive platform. The CPU enters the low power state via the `CEASE` instruction after configuring the TMC0. Any devices that inside the tile power domain will be power gated, including the private cache. Therefore flushing the private cache before entering the low power state. Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-9-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: sbi: Extends sbi_ipi_raw_send() to use all available IPI devicesNick Hu1-1/+1
A platform may contain multiple IPI devices. In certain use cases, such as power management, it may be necessary to send an IPI through a specific device to wake up a CPU. For example, if an IMSIC is powered down and reset, the core cannot receive IPIs from it, so the wake-up must instead be triggered through the CLINT. Suggested-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-8-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils/irqchip: Add APLIC restore functionNick Hu1-0/+3
Since the APLIC may enter a reset state upon system wake-up from a platform low power state, adding a restore function to reinitialize the APLIC. Reviewed-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-7-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
generated by cgit v1.2.3 (git 2.39.1) at 2026-05-16 18:35:32 +0000