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| author | Anup Patel <apatel@ventanamicro.com> | 2025-09-30 21:02:16 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2025-10-21 19:34:09 +0530 |
| commit | 55296fd27c0ce12a2024c7eacfdbab2dfd39476b (patch) | |
| tree | 72269ea871f87953572423025a26b0954edeafb0 /include | |
| parent | 3990c8ee07de1bdce87f43cd6e5d2d8181a2d9c2 (diff) | |
| download | opensbi-55296fd27c0ce12a2024c7eacfdbab2dfd39476b.zip opensbi-55296fd27c0ce12a2024c7eacfdbab2dfd39476b.tar.gz opensbi-55296fd27c0ce12a2024c7eacfdbab2dfd39476b.tar.bz2 | |
lib: Allow custom CSRs in csr_read_num() and csr_write_num()
Some of the platforms use platform specific CSR access functions for
configuring implementation specific CSRs (such as PMA registers).
Extend the common csr_read_num() and csr_write_num() to allow custom
CSRs so that platform specific CSR access functions are not needed.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Link: https://lore.kernel.org/r/20250930153216.89853-1-apatel@ventanamicro.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/sbi/riscv_encoding.h | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h index 40a854e..61e4b63 100644 --- a/include/sbi/riscv_encoding.h +++ b/include/sbi/riscv_encoding.h @@ -783,6 +783,40 @@ #define CSR_VTYPE 0xc21 #define CSR_VLENB 0xc22 +/* Custom CSR ranges */ +#define CSR_CUSTOM0_U_RW_BASE 0x800 +#define CSR_CUSTOM0_U_RW_COUNT 0x100 + +#define CSR_CUSTOM1_U_RO_BASE 0xCC0 +#define CSR_CUSTOM1_U_RO_COUNT 0x040 + +#define CSR_CUSTOM2_S_RW_BASE 0x5C0 +#define CSR_CUSTOM2_S_RW_COUNT 0x040 + +#define CSR_CUSTOM3_S_RW_BASE 0x9C0 +#define CSR_CUSTOM3_S_RW_COUNT 0x040 + +#define CSR_CUSTOM4_S_RO_BASE 0xDC0 +#define CSR_CUSTOM4_S_RO_COUNT 0x040 + +#define CSR_CUSTOM5_HS_RW_BASE 0x6C0 +#define CSR_CUSTOM5_HS_RW_COUNT 0x040 + +#define CSR_CUSTOM6_HS_RW_BASE 0xAC0 +#define CSR_CUSTOM6_HS_RW_COUNT 0x040 + +#define CSR_CUSTOM7_HS_RO_BASE 0xEC0 +#define CSR_CUSTOM7_HS_RO_COUNT 0x040 + +#define CSR_CUSTOM8_M_RW_BASE 0x7C0 +#define CSR_CUSTOM8_M_RW_COUNT 0x040 + +#define CSR_CUSTOM9_M_RW_BASE 0xBC0 +#define CSR_CUSTOM9_M_RW_COUNT 0x040 + +#define CSR_CUSTOM10_M_RO_BASE 0xFC0 +#define CSR_CUSTOM10_M_RO_COUNT 0x040 + /* ===== Trap/Exception Causes ===== */ #define CAUSE_MISALIGNED_FETCH 0x0 |