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| author | Ben Zong-You Xie <ben717@andestech.com> | 2025-12-29 15:19:13 +0800 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2026-02-11 12:13:01 +0530 |
| commit | 82b0961821e45768a91139b8ec5d7784586aa7f9 (patch) | |
| tree | 35a635661eb8e7c35b0fb9a8f4611939766014c5 /include | |
| parent | 6d26b43c477a7616d1f030261430127fa6c61d27 (diff) | |
| download | opensbi-82b0961821e45768a91139b8ec5d7784586aa7f9.tar.gz opensbi-82b0961821e45768a91139b8ec5d7784586aa7f9.tar.bz2 opensbi-82b0961821e45768a91139b8ec5d7784586aa7f9.zip | |
lib: utils/cache: add Andes last level cache controller
Introduce a FDT-based driver for the Andes Last Level Cache (LLC)
controller to support cache maintenance operations.
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Link: https://lore.kernel.org/r/20251229071914.1451587-5-ben717@andestech.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/sbi_utils/hsm/fdt_hsm_andes_atcsmu.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/include/sbi_utils/hsm/fdt_hsm_andes_atcsmu.h b/include/sbi_utils/hsm/fdt_hsm_andes_atcsmu.h index 881d8b21..ef851b75 100644 --- a/include/sbi_utils/hsm/fdt_hsm_andes_atcsmu.h +++ b/include/sbi_utils/hsm/fdt_hsm_andes_atcsmu.h @@ -11,6 +11,8 @@ /* clang-format off */ +#define SCRATCH_PAD_OFFSET 0x40 + #define RESET_VEC_LO_OFFSET 0x50 #define RESET_VEC_HI_OFFSET 0x60 #define RESET_VEC_8CORE_OFFSET 0x1a0 @@ -31,6 +33,9 @@ #define PCS0_WE_OFFSET 0x90 #define PCSm_WE_OFFSET(i) ((i + 3) * 0x20 + PCS0_WE_OFFSET) +#define PCS_WAKEUP_RTC_ALARM_MASK BIT(2) +#define PCS_WAKEUP_UART2_MASK BIT(9) +#define PCS_WAKEUP_MSIP_MASK BIT(29) #define PCS0_CTL_OFFSET 0x94 #define PCSm_CTL_OFFSET(i) ((i + 3) * 0x20 + PCS0_CTL_OFFSET) @@ -38,6 +43,14 @@ #define WAKEUP_CMD 0x8 #define DEEP_SLEEP_CMD 0xb +#define PCS0_STATUS_OFFSET 0x98 +#define PCSm_STATUS_OFFSET(i) ((i + 3) * 0x20 + PCS0_STATUS_OFFSET) +#define PD_TYPE_MASK GENMASK(2, 0) +#define PD_TYPE_SLEEP 2 +#define PD_STATUS_MASK GENMASK(7, 3) +#define PD_STATUS_LIGHT_SLEEP 0 +#define PD_STATUS_DEEP_SLEEP 0x10 + /* clang-format on */ void atcsmu_set_wakeup_events(u32 events, u32 hartid); @@ -45,5 +58,7 @@ bool atcsmu_support_sleep_mode(u32 sleep_type, u32 hartid); void atcsmu_set_command(u32 pcs_ctl, u32 hartid); int atcsmu_set_reset_vector(u64 wakeup_addr, u32 hartid); u32 atcsmu_get_sleep_type(u32 hartid); +void atcsmu_write_scratch(u32 value); +u32 atcsmu_read_scratch(void); #endif |