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2023-10-11hdata: Use existing define for PCIA signature checkNicholas Piggin1-1/+1
Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-10-11hdata: make for_each_pcia take spiras as an argumentNicholas Piggin4-4/+4
Have for_each_pcia take spiras as an argument rather than use the global variable. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-10-11hdata: Remove legacy SPIRA structureNicholas Piggin12-267/+92
skiboot only supports POWER8 > DD1 now, all supported platforms should use the new SPIRA-S/H structure. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-10-11hdata: split idata accessor functionNicholas Piggin1-7/+17
Add HDIF_idata that returns the idata pointer structure, not a pointer to the data itself. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-10-11hdata: Make hdata child accessors check the headerNicholas Piggin1-0/+12
Like other (idata) accessors already do, check the common header in hdata child accessor calls. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-10-11hdata: Use common code for HDIF header checkNicholas Piggin2-4/+8
Make the HDIF header check use a common function. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-10-11hdata: Add POWER10 Rainier testsNicholas Piggin3-0/+4237
Grab a SPIRA-S from a booted Rainier system and plug it in. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2022-06-13core: detect LPAR-per-core mode and report in dtNicholas Piggin2-0/+4
Some firmware configurations boot in LPAR-per-core mode, which is not compatible with KVM on POWER9 and later machines. Detect which LPAR mode the boot core is in (all others will be set the same way), and if booted in LPAR-per-core mode then print a warning and add a device-tree entry that the OS can test for. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2022-02-04Fix compilation waning "Missing #interrupt-cells"Abhishek Singh Tomar3-0/+27
Resolve : "Missing #interrupt-cells" warning duriing dts(device tree source) compilation hdata/test/p81-811.spira.dts:1434.37-1442.4: Warning (interrupt_provider): /interrupt-controller@3ffff80030000: Missing #interrupt-cells in interrupt provider An #interrupt-cells added to both reference dts for testing and source code to generate dtb from hdata. Signed-off-by: Abhishek Singh Tomar <abhishek@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-04Fix array-bound compilation warningsAbhishek Singh Tomar2-2/+2
Resolves : the warray bounds warning during compilation /build/libc/include/string.h:34:16: warning: '__builtin_memset' offset [0, 2097151] is out of the bounds [0, 0] [-Warray-bounds] 34 | #define memset __builtin_memset hw/fsp/fsp.c:1855:9: note: in expansion of macro 'memset' 1855 | memset(fsp_tce_table, 0, PSI_TCE_TABLE_SIZE); use volatile pointer to avoid optimization introduced with gcc-11 on constant address assignment to pointer. Signed-off-by: Abhishek Singh Tomar <abhishek@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-11-10hdata: add mmu-pid-bits and mmu-lpid-bits for POWER10 CPUsNicholas Piggin1-0/+4
This adds ibm,mmu-pid-bits and a new ibm,mmu-lpid-bits to POWER10 CPUs. POWER9 Linux has some workarounds for processors bugs that means it's probably safer to not add the entries there. Linux already hard codes these values correctly on these processors, but this allows more flexibility to change things. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-19pau: introduce supportChristophe Lombard2-8/+25
OpenCapi for P10 is included in the P10 chip. This requires OCAPI capable PHYs, Datalink Layer Logic and Transaction Layer Logic to be included. The PHYs are the physical connection to the OCAPI interconnect. The Datalink Layer provides link training. The Transaction Layer executes the cache coherent and data movement commands on the P10 chip. The PAU provides the Transaction Layer functionality for the OCAPI link(s) on the P10 chip. The P10 PAU supports two OCAPI links. Six accelerator units PAUs are instantiated on the P10 chip for a total of twelve OCAPI links. This patch adds PAU opencapi structure for supporting OpenCapi5. hw/pau.c file contains main of PAU management functions. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06platform: Add Denali platform supportVasant Hegde2-0/+5
Denali is P10 system. But FSP interaction (MBOX protocol) is same as ZZ. Hence add denali platform detection code inside zz.c for now. We can think of adding separate platform later. Also enable : - P10 TCE mapping support - Detect PHBs Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hdata/iohub: Read PCI Gen5 equalization settings for P10Frederic Barrat2-10/+25
HDAT spec added fields to define the equalization settings for PCI Gen5 link. Format is the same as PCI Gen4, so we just need to add extra fields in the "ibm,lane-eq" in the device tree. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06phys/P10: Use topology index to get phys mappingVasant Hegde3-1/+32
This fixes multipchip rainier boot issue. for Rainer: chip0: ibm,primary-topology-index = < 0x0>; chip1: ibm,primary-topology-index = < 0x4>; chip2: ibm,primary-topology-index = < 0x8>; chip3: ibm,primary-topology-index = < 0xc>; for Denali: node0: chip0: ibm,primary-topology-index = < 0x0>; chip1: ibm,primary-topology-index = < 0x1>; chip2: ibm,primary-topology-index = < 0x2>; chip3: ibm,primary-topology-index = < 0x3>; node1: chip0: ibm,primary-topology-index = < 0x4>; chip1: ibm,primary-topology-index = < 0x5>; chip2: ibm,primary-topology-index = < 0x6>; chip3: ibm,primary-topology-index = < 0x7>; Note that bmc_create_node() gets called very early in the boot process. Hence we have to traverse through HDAT ntuple to get right topology index. May be we can optimize pcid_to_topology_idx() function as its pretty much duplicate of pcid_to_chip_id(). But for now lets keep it as separate function. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Ryan Grimm <grimm@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hdata/P10: Fix xscom address and ibm, chip-id propertyVasant Hegde4-12/+28
`xscom_id` is deprecated in P10. Instead we should use topology ID's ("Primary topology table index") to calculate xscom address. Also use ("Processor fabric topology id") for "ibm,chip-id" property. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hdat/spira: Add ibm, power10-vas-x string to VAS compatible propertyHaren Myneni1-9/+16
VAS SCOM base address and paste address format are changed on P10. This patch adds ibm,power10-vas-x string to compatible property per each VAS node. This compatible string is used to define the paste base address later during VAS initialization. Also enables NX on P10 without adding any compatible string since the NX SCOM base address is not changed. Signed-off-by: Haren Myneni <haren@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hdat/spira: Define ibm, primary-topology-index property per chipHaren Myneni2-1/+16
HDAT provides Topology ID table and the primary topology location on P10. This primary location points to primary topology entry in ID table which contains the primary topology index and this index is used to define the paste base address per chip. This patch reads Topology ID table and the primary topology location from hdata and retrieves the primary topology index in the ID table. Make this primaty topology index value available with ibm,primary-topology-index property per chip. VAS reads this property to setup paste base address for each chip. Signed-off-by: Haren Myneni <haren@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hdata: Add POWER10 supportVasant Hegde8-30/+148
Initial P10 support - LPC : This contains two useful information: LPC MCTP Memory Window Base Address Second vUART console details - Enable memory-buffer mmio - Fix ipmi sensors IPMI sensors are deprecated in P10. Hence do not parse ipmi sensors. - I2C support - Detect PHB5 - Create p10 xscom, xive, chiptod nodes - Set pa-features bit for 2nd DAWR Availability of 2nd DAWR depends on 0th bit of 64th byte of ibm,pa-features property. Set it for p10. Co-authored-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Co-authored-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Co-authored-by: Reza Arbab <arbab@linux.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Co-authored-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com> Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-06-30hdat/i2c: Rework i2c device creationOliver O'Halloran1-62/+109
We've got functions to instantiate I2C buses at various places inside of the skiboot code base (in hdat, firenze-pci, and in witherspoon). The HDAT ones are the most generic so re-work those a bit and export the functions used to add DT nodes for I2C masters and the ports below them. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-06-30hdata/vpd: Add new FRU part number keywordVasant Hegde1-0/+1
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-02-04hdata/i2c: Use inclusive language, replace the word 'whitelist'Philippe Mathieu-Daudé1-3/+3
Follow the inclusive terminology from the "Conscious Language in your Open Source Projects" guidelines [*] and replace the word "whitelist" appropriately. [*] https://github.com/conscious-lang/conscious-lang-docs/blob/main/faq.md Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2020-12-15hw/ocmb: Clear top bit from offset before searching addr rangeVasant Hegde1-6/+0
Looks like HBRT sets top bit in pcbaddress before making OCMB SCOM request. We have to clear that bit so that we can find proper address range for SCOM operation. Sample failure: [ 2578.156011925,3] OCMB: no matching address range! [ 2578.156044481,3] scom_read: to 80000028 off: 8006430d4008c000 rc = -26 Also move HRMOR_BIT macro to common include file (hdata/spira.h -> skiboot.h). Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2020-12-15hdata: assert if we fail to add xscom nodesVasant Hegde1-2/+1
If we have duplicate xscom nodes then it will fail to attach xscom node to device tree and we will fail eventully. Better to call assert() and fail here. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2020-12-15hdata: Replace hardcoded string with macroVasant Hegde1-1/+1
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Reviewed-by: Dan Horák <dan@danny.cz> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2020-12-15hdata: Update ipmi sensors structureVasant Hegde1-1/+2
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Reviewed-by: Dan Horák <dan@danny.cz> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2020-10-01hdata/spira: add physical presence flagsNayna Jain2-1/+17
This patch reads the hdata bits to check for physical presence assertion, and creates device tree entries to be consumed later in the boot. Signed-off-by: Nayna Jain <nayna@linux.ibm.com> Signed-off-by: Eric Richter <erichte@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-08-07Add basic P9 fused core supportRyan Grimm1-1/+8
P9 cores can be configured into fused core mode where two core chiplets function as an 8-threaded, single core. So, bump four to eight in boot_entry when in fused core mode and cpu_thread_count in init_boot_cpu. The HID, AMOR, TSCR, RPR require the first active thread on that core chiplet to load the copy for that core chiplet. So, send thread 1 of a fused core to init_shared_sprs in boot_entry. The code checks for fused core mode in the core thead state register and puts a field in struct cpu_thread. This flag is checked when updating the HID and in XIVE code when setting the special bar. For XSCOM, the core ID is the non-fused EX. So, create macros to arrange the bits. It's fairly verbose but somewhat readable. This was tested on a P9 ZZ with 16 fused cores and ran HTX for over 24 hours. Signed-off-by: Ryan Grimm <grimm@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-08-07hdata: Add new "smp-cable-connector" VPD keywordKlaus Heinrich Kiwi1-0/+1
Recent FSP versions are defining a new VPD keyword 'SN' that brings SMP Cable Connector FRU info. Signed-off-by: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-08-07hdata: Ensure the prd-label hbrt-code-image is prefixedOliver O'Halloran1-0/+9
Older versions of opal-prd (i.e. most of them shipped by distros) expect the HBRT image to have the PRD label of "ibm,hbrt-code-image". Commit c3bfa3209559 ("hdata: Fix reserved node label search") made opal-prd check for both strings, but since opal-prd itself is the only component interested in locating the hbrt-code-image we might as well just add the prefix in firmware. Cc: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30dt: Set new property length in dt_resize_property()Thiago Jung Bauermann1-1/+0
All callers of dt_resize_property() need to set the new property length after calling it. append_chip_id() wasn't doing it, which caused this assert when booting my machine: [ 136.387213258,3] Unable to use memory range 0 from MSAREA 0 [ 136.387356677,3] Unable to use memory range 0 from MSAREA 2 [ 136.387408390,3] *********************************************** [ 136.387454272,3] < assert failed at core/device.c:605 > [ 136.387493225,3] . [ 136.387512799,3] . [ 136.387534056,3] . [ 136.387550294,3] OO__) [ 136.387579530,3] <"__/ [ 136.387605086,3] ^ ^ [ 136.387719329,3] Fatal TRAP at 0000000030028a18 .dt_property_set_cell+0x34 MSR 9000000000021002 [ 136.387801707,3] CFAR : 00000000300bfd3c MSR : 9000000000001000 [ 136.387847032,3] SRR0 : 0000000030028a18 SRR1 : 9000000000021002 [ 136.387893119,3] HSRR0: 0000000030012524 HSRR1: 9000000000001000 [ 136.387936830,3] DSISR: 40000000 DAR : 00000002019df000 [ 136.387983570,3] LR : 00000000300bfd40 CTR : 0000000000000000 [ 136.388046031,3] CR : 20004202 XER : 00000000 [ 136.388094553,3] GPR00: 00000000300bfd40 GPR16: 0000000000000001 [ 136.388139862,3] GPR01: 0000000031e536e0 GPR17: 00000000300ca3c9 [ 136.388181131,3] GPR02: 0000000030121200 GPR18: 0000000030103e1c [ 136.388224105,3] GPR03: 000000003053fc60 GPR19: 0000000000000008 [ 136.388270356,3] GPR04: 0000000000000001 GPR20: 000000003053fba0 [ 136.388313950,3] GPR05: 0000000000000008 GPR21: 0000000000000001 [ 136.388363021,3] GPR06: 0000000031e50060 GPR22: 0000000000000001 [ 136.388416754,3] GPR07: 0000000000000000 GPR23: 0000000000000000 [ 136.388465729,3] GPR08: 0000000000000000 GPR24: 0000000000000000 [ 136.388508156,3] GPR09: 0000000000000004 GPR25: 0000000031204060 [ 136.388556203,3] GPR10: 0000000000000008 GPR26: 000000003120402c [ 136.388599076,3] GPR11: 0000000000000000 GPR27: 0000000030010000 [ 136.388642108,3] GPR12: 0000000040004204 GPR28: 0000000000000002 [ 136.388694064,3] GPR13: 0000000031e50000 GPR29: 0000000031203ee0 [ 136.388743298,3] GPR14: 00000000300cbf03 GPR30: 0000000031202e80 [ 136.388797131,3] GPR15: 00000000300cc01c GPR31: 0000000030103a33 CPU 0048 Backtrace: S: 0000000031e539e0 R: 0000000030028874 .dt_resize_property+0x28 S: 0000000031e53a60 R: 00000000300bfd40 .memory_parse+0xd84 S: 0000000031e53c40 R: 00000000300bc4d8 .parse_hdat+0xed0 S: 0000000031e53e30 R: 000000003001504c .main_cpu_entry+0x1ac S: 0000000031e53f00 R: 0000000030002760 boot_entry+0x1b0 Avoid further appearances of the unidentified animal of doom by making dt_resize_property() do the length updating itself, freeing its callers from that need. Suggested-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Thiago Jung Bauermann <bauerman@linux.ibm.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-11hdata: MS AREA endian fixNicholas Piggin1-3/+3
Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [oliver: fix up drift] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-05-26hdata/memory.c: Fix "Inconsistent MSAREA" warningsKlaus Heinrich Kiwi1-0/+3
add_memory_buffer_mmio() should be exclusive to P9P (AXONE). Running it on non P9P systems resulted in warnings such as: MS AREA: Inconsistent MSAREA version 40 for P9P system So check for PVR and quietly return if not P9P. Fixes: 38b5c3179 (Add support for memory-buffer mmio) Cc: skiboot-stable@lists.ozlabs.org Cc: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-04-15ZZ: Fix System Attention Indicator location codeVasant Hegde1-1/+5
We are using SAI indicator location from SLCA to represent System Attention Indicator location code. In P9, this is mapped to op-panel location code. op-panel has identify and fault LEDs as well. Our SPCN command lists op-panel location code as well. Hence we get below OPAL warning. OPAL msglog: FSPLED: duplicate location code U78D3.001.WT0004T-D1 Because of above issue we are not creating device tree node for D1 identify/fault indicators. We have System Attention Indicator at enclosure level as well.. which is replica of attention indicator in op-panel. Hence use System VPD location code to represent attention indicator. Note that we have dedicated MBOX command to read/update System Attention Indicator which doesn't need location code. Hence we are fine with this change. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-04-08hdata/memory: Add support for memory-buffer mmioOliver O'Halloran1-14/+125
HDAT now allows associating a set of MMIO address ranges with an MSAREA. This is to allow for exporting the MMIO register space associated with a memory-buffer chip to the hypervisor so we can wire up access to that for PRD. The DT format is similar to the old centaur memory-buffer@<addr> nodes that we had on P8 OpenPower systems. The biggest difference is that the HDAT format allows for multiple memory ranges on each "chip" and each of these ranges may have a different register size. Cc: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-03-12Re-license IBM written files as Apache 2.0 OR GPLv2+Stewart Smith21-20/+21
SPDX makes it a simpler diff. I have audited the commit history of each file to ensure that they are exclusively authored by IBM and thus we have the right to relicense. The motivation behind this is twofold: 1) We want to enable experiments with coreboot, which is GPLv2 licensed 2) An upcoming firmware component wants to incorporate code from skiboot and code from the Linux kernel, which is GPLv2 licensed. I have gone through the IBM internal way of gaining approval for this. The following files are not exclusively authored by IBM, so are *not* included in this update (I will be seeking approval from contributors): core/direct-controls.c core/flash.c core/pcie-slot.c external/common/arch_flash_unknown.c external/common/rules.mk external/gard/Makefile external/gard/rules.mk external/opal-prd/Makefile external/pflash/Makefile external/xscom-utils/Makefile hdata/vpd.c hw/dts.c hw/ipmi/ipmi-watchdog.c hw/phb4.c include/cpu.h include/phb4.h include/platform.h libflash/libffs.c libstb/mbedtls/sha512.c libstb/mbedtls/sha512.h platforms/astbmc/barreleye.c platforms/astbmc/garrison.c platforms/astbmc/mihawk.c platforms/astbmc/nicole.c platforms/astbmc/p8dnu.c platforms/astbmc/p8dtu.c platforms/astbmc/p9dsu.c platforms/astbmc/vesnin.c platforms/rhesus/ec/config.h platforms/rhesus/ec/gpio.h platforms/rhesus/gpio.c platforms/rhesus/rhesus.c platforms/astbmc/talos.c platforms/astbmc/romulus.c Signed-off-by: Stewart Smith <stewart@linux.ibm.com> [oliver: fixed up the drift] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-02-12hdata: Fix SP attention area addressVasant Hegde1-1/+2
SP attention area is aligned. We were sending wrong address. Hence `attn` on FSP based system is failing. Align SP attention area so that FSP can locate attention data. Fixes: 518e554 (spira: fix endian conversions in spira data structures) CC: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-01-29hdata: Update MPIPL support IPL parameterVasant Hegde1-1/+1
We used bit 4 of `sys_attributes` attribute for MPIPL supported flag. Unfortunately we forgot to update HDAT spec. Now bit 4 is used for different purpose. Hence use bit 5 for MPIPL. Fortunately we don't have any released firmware with MPIPL supported yet. Hence its safe to make this change. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-01-29npu2, npu3: Remove ibm, phb-index property from the NPU dt nodeFrederic Barrat2-6/+2
The 'ibm,phb-index' property of the NPU node is now useless, as we can have multiple PHBs associated to the same NPU on P9. Let's remove it to avoid confusion. Reviewed-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-12-16fix simple sparse warningsNicholas Piggin1-1/+1
Should be no real code change, these mostly update type declarations that sparse complains about. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-12-16add more sparse endian annotationsNicholas Piggin3-6/+6
This fixes quite a few sparse endian annotations across the tree. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-12-16dt: assorted cleanupsNicholas Piggin2-19/+9
This replaces several instances dt accesses with higher level primitives throughout the tree. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-12-16naca: move naca definition from asm to CNicholas Piggin6-9/+92
This results in the same layout and location of the naca and hv data structures. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-12-16hdata: endian conversionsNicholas Piggin2-4/+5
Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-12-16spira: fix endian conversions in spira data structuresNicholas Piggin2-22/+40
Labels can't be used for static initialisers that require endian conversion. Use constants for these. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-12-16cpu: use dt accessor device tree accessNicholas Piggin5-45/+55
In several cases the make test reference .dts files were incorrectly byteswapped, these are fixed here too. Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-14tests: Squash __attrconst related warningsOliver O'Halloran1-4/+2
Currently we get a warning because in some of the test stub functions: [ HOSTCC ] hw/test/phys-map-test.c In file included from hw/test/phys-map-test.c:8: hw/test/../../core/test/stubs.c:78:1: warning: ‘const’ attribute on function returning ‘void’ [-Wattributes] 78 | { | ^ I'm pretty sure we added that __attrconst to squash a warning with an earlier GCC, then they went an added a warning for the "fix." I love compilers. Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-14hdata/test: Remove all temp filesOliver O'Halloran1-1/+1
mktemp generates a random file name and creates a blank file with that name in /tmp. dtdiff_wrap.sh doesn't remove the blank file, or the re-parsed DTB file so you end up with a lot of them in /tmp. Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-11Remove dead POWER7 codeNicholas Piggin9-441/+39
There are a number of proc_gen branches removed that are trivially dead code and comments that refer to P7. As well as those: - Oliver points out that add_xics_icps() must be unused on POWER8 because it asserts if number of threads > 4, so remove it. - Change 16b7ae641 ("Remove POWER7 and POWER7+ support") removed all references to opal_boot_trampoline, so remove that. - It also removed the only non-trival choose_bus implementation, so that is removed and its caller simplified. - Remove the paca code, later CPUs use pcia. Cc: Stewart Smith <stewart@flamingspork.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-11hdata/test/hdata_to_dt.c: use P8E PVR when -8E is givenNicholas Piggin3-27/+27
Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
generated by cgit v1.1 at 2024-07-10 02:44:24 +0000