Remove dead POWER7 code

There are a number of proc_gen branches removed that are trivially
dead code and comments that refer to P7. As well as those:

- Oliver points out that add_xics_icps() must be unused on POWER8
  because it asserts if number of threads > 4, so remove it.

- Change 16b7ae641 ("Remove POWER7 and POWER7+ support") removed all
  references to opal_boot_trampoline, so remove that.

- It also removed the only non-trival choose_bus implementation, so
  that is removed and its caller simplified.

- Remove the paca code, later CPUs use pcia.

Cc: Stewart Smith <stewart@flamingspork.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>

9 files changed, 39 insertions, 441 deletions

diff --git a/hdata/Makefile.inc b/hdata/Makefile.inc
index 6f47314..2d52f76 100644
--- a/hdata/Makefile.inc
+++ b/hdata/Makefile.inc
@@ -1,7 +1,7 @@
 # -*-Makefile-*-
 
 SUBDIRS += hdata
-HDATA_OBJS = spira.o paca.o pcia.o hdif.o memory.o fsp.o iohub.o vpd.o slca.o
+HDATA_OBJS = spira.o pcia.o hdif.o memory.o fsp.o iohub.o vpd.o slca.o
 HDATA_OBJS += cpu-common.o vpd-common.o hostservices.o i2c.o tpmrel.o
 DEVSRC_OBJ = hdata/built-in.a
 
diff --git a/hdata/cpu-common.c b/hdata/cpu-common.c
index 55a663f..b229f64 100644
--- a/hdata/cpu-common.c
+++ b/hdata/cpu-common.c
@@ -11,7 +11,7 @@
 
 struct dt_node * add_core_common(struct dt_node *cpus,
 				 const struct sppcia_cpu_cache *cache,
-				 const struct sppaca_cpu_timebase *tb,
+				 const struct sppcia_cpu_timebase *tb,
 				 uint32_t int_server, bool okay)
 {
 	const char *name;
@@ -107,7 +107,7 @@ struct dt_node * add_core_common(struct dt_node *cpus,
 		dt_add_property_cells(cpu, "ibm,processor-radix-AP-encodings",
 			0x0000000c, 0xa0000010, 0x20000015, 0x4000001e);
 
-	/* Page size encodings appear to be the same for P7 and P8 */
+	/* HPT segment page size encodings, common to all supported CPUs */
 	dt_add_property_cells(cpu, "ibm,segment-page-sizes",
 		0x0c, 0x000, 3, 0x0c, 0x0000,  /*  4K seg  4k pages */
 		                0x10, 0x0007,  /*  4K seg 64k pages */
diff --git a/hdata/hdata.h b/hdata/hdata.h
index f778471..7504b1e 100644
--- a/hdata/hdata.h
+++ b/hdata/hdata.h
@@ -9,7 +9,6 @@
 struct dt_node;
 
 extern void memory_parse(void);
-extern int paca_parse(void);
 extern bool pcia_parse(void);
 extern void fsp_parse(void);
 extern void bmc_parse(void);
@@ -25,8 +24,8 @@ extern struct dt_node *find_xscom_for_chip(uint32_t chip_id);
 extern uint32_t pcid_to_chip_id(uint32_t proc_chip_id);
 
 extern struct dt_node *add_core_common(struct dt_node *cpus,
-				       const struct sppaca_cpu_cache *cache,
-				       const struct sppaca_cpu_timebase *tb,
+				       const struct sppcia_cpu_cache *cache,
+				       const struct sppcia_cpu_timebase *tb,
 				       uint32_t int_server, bool okay);
 extern void add_core_attr(struct dt_node *cpu, uint32_t attr);
 extern uint32_t add_core_cache_info(struct dt_node *cpus,
diff --git a/hdata/paca.c b/hdata/paca.c
deleted file mode 100644
index 28025b0..0000000
--- a/hdata/paca.c
+++ /dev/null
@@ -1,331 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-/* Copyright 2013-2017 IBM Corp. */
-
-#include <skiboot.h>
-#include "spira.h"
-#include <cpu.h>
-#include <fsp.h>
-#include <opal.h>
-#include <ccan/str/str.h>
-#include <device.h>
-#include <types.h>
-
-#include "hdata.h"
-
-#define PACA_MAX_THREADS 4
-
-static unsigned int paca_index(const struct HDIF_common_hdr *paca)
-{
-	void *start = get_hdif(&spira.ntuples.paca, PACA_HDIF_SIG);
-	return ((void *)paca - start)
-		/ be32_to_cpu(spira.ntuples.paca.alloc_len);
-}
-
-static struct dt_node *add_cpu_node(struct dt_node *cpus,
-				    const struct HDIF_common_hdr *paca,
-				    const struct sppaca_cpu_id *id,
-				    bool okay)
-{
-	const struct sppaca_cpu_timebase *timebase;
-	const struct sppaca_cpu_cache *cache;
-	const struct sppaca_cpu_attr *attr;
-	struct dt_node *cpu;
-	u32 no, size, ve_flags, l2_phandle, chip_id;
-
-	/* We use the process_interrupt_line as the res id */
-	no = be32_to_cpu(id->process_interrupt_line);
-
-	ve_flags = be32_to_cpu(id->verify_exists_flags);
-	prlog(PR_INFO, "CPU[%i]: PIR=%i RES=%i %s %s(%u threads)\n",
-	       paca_index(paca), be32_to_cpu(id->pir), no,
-	       ve_flags & CPU_ID_PACA_RESERVED
-	       ? "**RESERVED**" : cpu_state(ve_flags),
-	       ve_flags & CPU_ID_SECONDARY_THREAD
-	       ? "[secondary] " : 
-	       (be32_to_cpu(id->pir) == boot_cpu->pir ? "[boot] " : ""),
-	       ((ve_flags & CPU_ID_NUM_SECONDARY_THREAD_MASK)
-		>> CPU_ID_NUM_SECONDARY_THREAD_SHIFT) + 1);
-
-	timebase = HDIF_get_idata(paca, SPPACA_IDATA_TIMEBASE, &size);
-	if (!timebase || size < sizeof(*timebase)) {
-		prerror("CPU[%i]: bad timebase size %u @ %p\n",
-			paca_index(paca), size, timebase);
-		return NULL;
-	}
-
-	cache = HDIF_get_idata(paca, SPPACA_IDATA_CACHE_SIZE, &size);
-	if (!cache || size < sizeof(*cache)) {
-		prerror("CPU[%i]: bad cache size %u @ %p\n",
-			paca_index(paca), size, cache);
-		return NULL;
-	}
-
-	cpu = add_core_common(cpus, cache, timebase, no, okay);
-
-	/* Core attributes */
-	attr = HDIF_get_idata(paca, SPPACA_IDATA_CPU_ATTR, &size);
-	if (attr)
-		add_core_attr(cpu, be32_to_cpu(attr->attr));
-
-	/* Add cache info */
-	l2_phandle = add_core_cache_info(cpus, cache, no, okay);
-	dt_add_property_cells(cpu, "l2-cache", l2_phandle);
-
-	/* We append the secondary cpus in __cpu_parse */
-	dt_add_property_cells(cpu, "ibm,ppc-interrupt-server#s", no);
-
-	dt_add_property_cells(cpu, DT_PRIVATE "hw_proc_id",
-			      be32_to_cpu(id->hardware_proc_id));
-	dt_add_property_cells(cpu, "ibm,pir", be32_to_cpu(id->pir));
-
-	chip_id = pcid_to_chip_id(be32_to_cpu(id->processor_chip_id));
-	dt_add_property_cells(cpu, "ibm,chip-id", chip_id);
-
-	return cpu;
-}
-
-static struct dt_node *find_cpu_by_hardware_proc_id(struct dt_node *root,
-						    u32 hw_proc_id)
-{
-	struct dt_node *i;
-
-	dt_for_each_node(root, i) {
-		const struct dt_property *prop;
-
-		if (!dt_has_node_property(i, "device_type", "cpu"))
-			continue;
-
-		prop = dt_find_property(i, DT_PRIVATE "hw_proc_id");
-		if (!prop)
-			return NULL;
-
-		if (be32_to_cpu(*(be32 *)prop->prop) == hw_proc_id)
-			return i;
-	}
-	return NULL;
-}
-
-/* Note that numbers are small. */
-static void add_be32_sorted(__be32 arr[], __be32 new, unsigned num)
-{
-	unsigned int i;
-
-	/* Walk until we find where we belong (insertion sort). */
-	for (i = 0; i < num; i++) {
-		if (be32_to_cpu(new) < be32_to_cpu(arr[i])) {
-			__be32 tmp = arr[i];
-			arr[i] = new;
-			new = tmp;
-		}
-	}
-	arr[i] = new;
-}
-
-static void add_xics_icps(void)
-{
-	struct dt_node *cpu;
-	unsigned int i;
-	u64 reg[PACA_MAX_THREADS * 2];
-	struct dt_node *icp;
-
-	dt_for_each_node(dt_root, cpu) {
-		u32 irange[2], size, pir;
-		const struct dt_property *intsrv;
-		const struct HDIF_common_hdr *paca;
-		u64 ibase;
-		unsigned int num_threads;
-		bool found = false;
-
-		if (!dt_has_node_property(cpu, "device_type", "cpu"))
-			continue;
-
-		intsrv = dt_find_property(cpu, "ibm,ppc-interrupt-server#s");
-		if (!intsrv)
-			continue;
-
-		pir = dt_prop_get_u32(cpu, "ibm,pir");
-
-		/* Get ibase address */
-		paca = get_hdif(&spira.ntuples.paca, PACA_HDIF_SIG);
-		for_each_paca(paca) {
-			const struct sppaca_cpu_id *id;
-			id = HDIF_get_idata(paca, SPPACA_IDATA_CPU_ID, &size);
-
-			if (!CHECK_SPPTR(id))
-				continue;
-
-			if (pir != be32_to_cpu(id->pir))
-				continue;
-			ibase = cleanup_addr(be64_to_cpu(id->ibase));
-			found = true;
-			break;
-		}
-		if (!found)
-			return;
-
-		num_threads = intsrv->len / sizeof(u32);
-		assert(num_threads <= PACA_MAX_THREADS);
-
-		icp = dt_new_addr(dt_root, "interrupt-controller", ibase);
-		if (!icp)
-			continue;
-
-		dt_add_property_strings(icp, "compatible",
-					"IBM,ppc-xicp",
-					"IBM,power7-xicp");
-
-		irange[0] = dt_property_get_cell(intsrv, 0); /* Index */
-		irange[1] = num_threads;		     /* num servers */
-		dt_add_property(icp, "ibm,interrupt-server-ranges",
-				irange, sizeof(irange));
-		dt_add_property(icp, "interrupt-controller", NULL, 0);
-		dt_add_property_cells(icp, "#address-cells", 0);
-		dt_add_property_string(icp, "device_type",
-				   "PowerPC-External-Interrupt-Presentation");
-		for (i = 0; i < num_threads*2; i += 2) {
-			reg[i] = ibase;
-			/* One page is enough for a handful of regs. */
-			reg[i+1] = 4096;
-			ibase += reg[i+1];
-		}
-		dt_add_property(icp, "reg", reg, sizeof(reg));	
-	}
-}
-
-static bool __paca_parse(void)
-{
-	const struct HDIF_common_hdr *paca;
-	struct dt_node *cpus;
-
-	paca = get_hdif(&spira.ntuples.paca, PACA_HDIF_SIG);
-	if (!paca) {
-		prerror("Invalid PACA (PCIA = %p)\n",
-			ntuple_addr(&spira.ntuples.pcia));
-		return false;
-	}
-
-	if (be32_to_cpu(spira.ntuples.paca.act_len) < sizeof(*paca)) {
-		prerror("PACA: invalid size %u\n",
-			be32_to_cpu(spira.ntuples.paca.act_len));
-		return false;
-	}
-
-	cpus = dt_new(dt_root, "cpus");
-	dt_add_property_cells(cpus, "#address-cells", 1);
-	dt_add_property_cells(cpus, "#size-cells", 0);
-
-	for_each_paca(paca) {
-		const struct sppaca_cpu_id *id;
-		u32 size, ve_flags;
-		bool okay;
-
-		id = HDIF_get_idata(paca, SPPACA_IDATA_CPU_ID, &size);
-
-		/* The ID structure on Blade314 is only 0x54 long. We can
-		 * cope with it as we don't use all the additional fields.
-		 * The minimum size we support is  0x40
-		 */
-		if (!id || size < SPIRA_CPU_ID_MIN_SIZE) {
-			prerror("CPU[%i]: bad id size %u @ %p\n",
-				paca_index(paca), size, id);
-			return false;
-		}
-
-		ve_flags = be32_to_cpu(id->verify_exists_flags);
-		switch ((ve_flags&CPU_ID_VERIFY_MASK) >> CPU_ID_VERIFY_SHIFT) {
-		case CPU_ID_VERIFY_USABLE_NO_FAILURES:
-		case CPU_ID_VERIFY_USABLE_FAILURES:
-			okay = true;
-			break;
-		default:
-			okay = false;
-		}
-
-		prlog(PR_INFO, "CPU[%i]: PIR=%i RES=%i %s\n",
-		       paca_index(paca), be32_to_cpu(id->pir),
-		       be32_to_cpu(id->process_interrupt_line),
-		       okay ? "OK" : "UNAVAILABLE");
-
-		/* Secondary threads don't get their own node. */
-		if (ve_flags & CPU_ID_SECONDARY_THREAD)
-			continue;
-
-		if (!add_cpu_node(cpus, paca, id, okay))
-			return false;
-	}
-
-	/* Now account for secondaries. */
-	for_each_paca(paca) {
-		const struct dt_property *prop;
-		const struct sppaca_cpu_id *id;
-		u32 size, state, num, ve_flags;
-		struct dt_node *cpu;
-		__be32 *new_prop;
-
-		id = HDIF_get_idata(paca, 2, &size);
-		if (!CHECK_SPPTR(id))
-			continue;
-
-		ve_flags = be32_to_cpu(id->verify_exists_flags);
-		state = (ve_flags & CPU_ID_VERIFY_MASK) >> CPU_ID_VERIFY_SHIFT;
-		switch (state) {
-		case CPU_ID_VERIFY_USABLE_NO_FAILURES:
-		case CPU_ID_VERIFY_USABLE_FAILURES:
-			break;
-		default:
-			continue;
-		}
-
-		/* Only interested in secondary threads. */
-		if (!(ve_flags & CPU_ID_SECONDARY_THREAD))
-			continue;
-
-		cpu = find_cpu_by_hardware_proc_id(cpus,
-				   be32_to_cpu(id->hardware_proc_id));
-		if (!cpu) {
-			prerror("CPU[%i]: could not find primary hwid %i\n",
-				paca_index(paca),
-				be32_to_cpu(id->hardware_proc_id));
-			return false;
-		}
-
-		/* Add the cpu #. */
-		prop = dt_find_property(cpu, "ibm,ppc-interrupt-server#s");
-		if (!prop) {
-			prerror("CPU[%i]: could not find mapping information\n",
-				paca_index(paca));
-			return false;
-		}
-		num = prop->len / sizeof(u32);
-		new_prop = malloc((num + 1) * sizeof(u32));
-		if (!new_prop) {
-			prerror("Property allocation length %zu failed\n",
-				(num + 1) * sizeof(u32));
-			return false;
-		}
-		memcpy(new_prop, prop->prop, prop->len);
-		add_be32_sorted(new_prop, id->process_interrupt_line, num);
-		dt_del_property(cpu, (struct dt_property *)prop);
-		dt_add_property(cpu, "ibm,ppc-interrupt-server#s",
-				new_prop, (num + 1) * sizeof(__be32));
-		free(new_prop);
-	}
-
-	/*
-	 * P7 and P8 use the XICS interrupt controller which has a per-core
-	 * interrupt controller node.
-	 */
-	if (proc_gen <= proc_gen_p8)
-		add_xics_icps();
-
-	return true;
-}
-
-int paca_parse(void)
-{
-	if (!__paca_parse()) {
-		prerror("CPU: Initial CPU parsing failed\n");
-		return -1;
-	}
-	return 0;
-}
diff --git a/hdata/pcia.c b/hdata/pcia.c
index ff645ab..8e3b961 100644
--- a/hdata/pcia.c
+++ b/hdata/pcia.c
@@ -114,7 +114,7 @@ static struct dt_node *add_core_node(struct dt_node *cpus,
 
 	prlog(PR_INFO, "CORE[%i]: PIR=%.8x %s %s(%u threads)\n",
 	      pcia_index(pcia), be32_to_cpu(t->pir),
-	      ve_flags & CPU_ID_PACA_RESERVED
+	      ve_flags & CPU_ID_PCIA_RESERVED
 	      ? "**RESERVED**" : cpu_state(ve_flags),
 	      be32_to_cpu(t->pir) == boot_cpu->pir ? "[boot] " : "", threads);
 
@@ -168,7 +168,7 @@ static struct dt_node *add_core_node(struct dt_node *cpus,
 	dt_add_property(cpu, "ibm,ppc-interrupt-server#s", iserv, 4 * threads);
 
 	/* Add the ICP node for this CPU for P8 */
-	if (proc_gen <= proc_gen_p8)
+	if (proc_gen == proc_gen_p8)
 		add_xics_icp(pcia, threads, icp_compat);
 
 	return cpu;
@@ -179,7 +179,6 @@ bool pcia_parse(void)
 	const void *pcia;
 	struct dt_node *cpus;
 
-	/* Check PCIA exists... if not, maybe we are getting a PACA ? */
 	pcia = get_hdif(&spira.ntuples.pcia, "SPPCIA");
 	if (!pcia)
 		return false;
diff --git a/hdata/spira.c b/hdata/spira.c
index 8b4e3cb..6e4da3c 100644
--- a/hdata/spira.c
+++ b/hdata/spira.c
@@ -847,7 +847,7 @@ static void add_nx_node(u32 gcid)
 					"ibm,power8-nx");
 		break;
 	case proc_gen_p9:
-		/* POWER9 NX is not software compatible with P7/P8 NX */
+		/* POWER9 NX is not software compatible with P8 NX */
 		dt_add_property_strings(nx, "compatible", "ibm,power9-nx");
 		break;
 	default:
@@ -1295,10 +1295,6 @@ static void add_iplparams(void)
  * numbering used by HDAT to reference chips, which doesn't correspond
  * to the HW IDs. We want to use the HW IDs everywhere in the DT so
  * we convert using this.
- *
- * Note: On P7, the HW ID is the XSCOM "GCID" including the T bit which
- * is *different* from the chip ID portion of the interrupt server#
- * (or PIR). See the explanations in chip.h
  */
 uint32_t pcid_to_chip_id(uint32_t proc_chip_id)
 {
@@ -1734,10 +1730,9 @@ int parse_hdat(bool is_opal)
 	/* Create /ibm,opal/led node */
 	dt_init_led_node();
 
-	/* Parse SPPACA and/or PCIA */
+	/* Parse PCIA */
 	if (!pcia_parse())
-		if (paca_parse() < 0)
-			return -1;
+		return -1;
 
 	/* IPL params */
 	add_iplparams();
diff --git a/hdata/spira.h b/hdata/spira.h
index eb5d1ea..2c944be 100644
--- a/hdata/spira.h
+++ b/hdata/spira.h
@@ -73,7 +73,7 @@ struct spira {
 	struct spira_ntuples	ntuples;
 	/*
 	 * We reserve 0xc0 rather than 0x4c0 so we fit SPIRAH/SPIRAS here
-	 * while preserving compatibility with existing P7/P8 systems.
+	 * while preserving compatibility with existing P8 systems.
 	 *
 	 * According to FSP engineers, this is an okay thing to do.
 	 */
@@ -180,11 +180,8 @@ extern struct HDIF_common_hdr *__get_hdif(struct spira_ntuple *n,
 			be32_to_cpu((_ntuples)->alloc_len));		\
 	     _p = (void *)_p + be32_to_cpu((_ntuples)->alloc_len))
 
-#define for_each_paca(p) for_each_ntuple(&spira.ntuples.paca, p, PACA_HDIF_SIG)
-
 #define for_each_pcia(p) for_each_ntuple(&spira.ntuples.pcia, p, SPPCIA_HDIF_SIG)
 
-
 /* We override these for testing. */
 #ifndef ntuple_addr
 #define ntuple_addr(_ntuples) ((void *)BE64_TO_CPU((_ntuples)->addr))
@@ -930,24 +927,18 @@ struct slca_entry {
 
 
 /*
- * SPPACA structure. The SPIRA contain an array of these, one
- * per processor thread
+ * SPPCIA structure. The SPIRA contain an array of these, one
+ * per processor core
  */
-#define PACA_HDIF_SIG	"SPPACA"
-
-/* Idata index 0 : FRU ID Data */
-#define SPPACA_IDATA_FRU_ID	0
-
-/* Idata index 1 : Keyword VPD */
-#define SPPACA_IDATA_KW_VPD	1
+#define SPPCIA_HDIF_SIG	"SPPCIA"
 
-/* Idata index 2 : CPU ID data area */
-#define SPPACA_IDATA_CPU_ID	2
+/* Idata index 0 : Core unique data */
+#define SPPCIA_IDATA_CORE_UNIQUE	0
 
-struct sppaca_cpu_id {
-	__be32 pir;
-	__be32 fru_id;
-	__be32 hardware_proc_id;
+struct sppcia_core_unique {
+	__be32 reserved;
+	__be32 proc_fru_id;
+	__be32 hw_proc_id;
 #define CPU_ID_VERIFY_MASK			0xC0000000
 #define CPU_ID_VERIFY_SHIFT			30
 #define CPU_ID_VERIFY_USABLE_NO_FAILURES	0
@@ -955,45 +946,43 @@ struct sppaca_cpu_id {
 #define CPU_ID_VERIFY_NOT_INSTALLED		2
 #define CPU_ID_VERIFY_UNUSABLE			3
 #define CPU_ID_SECONDARY_THREAD			0x20000000
-#define CPU_ID_PACA_RESERVED			0x10000000
+#define CPU_ID_PCIA_RESERVED			0x10000000
 #define CPU_ID_NUM_SECONDARY_THREAD_MASK	0x00FF0000
 #define CPU_ID_NUM_SECONDARY_THREAD_SHIFT	16
-	__be32 verify_exists_flags;
+	__be32 verif_exist_flags;
 	__be32 chip_ec_level;
-	__be32 processor_chip_id;
-	__be32 logical_processor_id;
-	/* This is the resource number, too. */
-	__be32 process_interrupt_line;
-	__be32 reserved1;
-	__be32 hardware_module_id;
-	__be64 ibase;
-	__be32 deprecated1;
-	__be32 physical_thread_id;
-	__be32 deprecated2;
+	__be32 proc_chip_id;
+	__be32 reserved2;
+	__be32 reserved3;
+	__be32 reserved4;
+	__be32 hw_module_id;
+	__be64 reserved5;
+	__be32 reserved6;
+	__be32 reserved7;
+	__be32 reserved8;
 	__be32 ccm_node_id;
-	/* This fields are not always present, check struct size */
-#define SPIRA_CPU_ID_MIN_SIZE	0x40
 	__be32 hw_card_id;
 	__be32 internal_drawer_node_id;
 	__be32 drawer_book_octant_blade_id;
 	__be32 memory_interleaving_scope;
 	__be32 lco_target;
+	__be32 reserved9;
 } __packed;
 
-/* Idata index 3 : Timebase data */
-#define SPPACA_IDATA_TIMEBASE	3
+/* Idata index 1 : CPU Time base structure */
+#define SPPCIA_IDATA_TIMEBASE		1
 
-struct sppaca_cpu_timebase {
+struct sppcia_cpu_timebase {
 	__be32 cycle_time;
 	__be32 time_base;
 	__be32 actual_clock_speed;
 	__be32 memory_bus_frequency;
 } __packed;
 
-/* Idata index 4 : Cache size structure */
-#define SPPACA_IDATA_CACHE_SIZE	4
+/* Idata index 2 : CPU Cache Size Structure */
+#define SPPCIA_IDATA_CPU_CACHE		2
 
-struct sppaca_cpu_cache {
+struct sppcia_cpu_cache {
 	__be32 icache_size_kb;
 	__be32 icache_line_size;
 	__be32 l1_dcache_size_kb;
@@ -1016,57 +1005,6 @@ struct sppaca_cpu_cache {
 	__be32 l35_cache_line_size;
 } __packed;
 
-/* Idata index 6 : CPU Attributes */
-#define SPPACA_IDATA_CPU_ATTR	6
-
-#define sppaca_cpu_attr sppcia_cpu_attr
-
-/*
- * SPPCIA structure. The SPIRA contain an array of these, one
- * per processor core
- */
-#define SPPCIA_HDIF_SIG	"SPPCIA"
-
-/* Idata index 0 : Core unique data */
-#define SPPCIA_IDATA_CORE_UNIQUE	0
-
-/* NOTE: This is the same layout as "struct sppaca_cpu_id",
- *       with essentially some fields removed and a reserved
- *       field added
- */
-struct sppcia_core_unique {
-	__be32 reserved;
-	__be32 proc_fru_id;
-	__be32 hw_proc_id;
-	__be32 verif_exist_flags;	/* Same as PACA */
-	__be32 chip_ec_level;
-	__be32 proc_chip_id;
-	__be32 reserved2;
-	__be32 reserved3;
-	__be32 reserved4;
-	__be32 hw_module_id;
-	__be64 reserved5;
-	__be32 reserved6;
-	__be32 reserved7;
-	__be32 reserved8;
-	__be32 ccm_node_id;
-	__be32 hw_card_id;
-	__be32 internal_drawer_node_id;
-	__be32 drawer_book_octant_blade_id;
-	__be32 memory_interleaving_scope;
-	__be32 lco_target;
-	__be32 reserved9;
-} __packed;
-
-/* Idata index 1 : CPU Time base structure */
-#define SPPCIA_IDATA_TIMEBASE		1
-
-#define sppcia_cpu_timebase sppaca_cpu_timebase
-
-/* Idata index 2 : CPU Cache Size Structure */
-#define SPPCIA_IDATA_CPU_CACHE		2
-
-#define sppcia_cpu_cache sppaca_cpu_cache
 
 /* Idata index 3 : Thread Array Data
  *
diff --git a/hdata/test/hdata_to_dt.c b/hdata/test/hdata_to_dt.c
index e1258f1..4605d50 100644
--- a/hdata/test/hdata_to_dt.c
+++ b/hdata/test/hdata_to_dt.c
@@ -136,7 +136,6 @@ static bool spira_check_ptr(const void *ptr, const char *file, unsigned int line
 #include "../hdif.c"
 #include "../iohub.c"
 #include "../memory.c"
-#include "../paca.c"
 #include "../pcia.c"
 #include "../spira.c"
 #include "../vpd.c"
@@ -339,7 +338,7 @@ int main(int argc, char *argv[])
 		     "  -8E Force PVR to POWER8E\n"
 		     "  -9 Force PVR to POWER9 (nimbus)\n"
 		     "\n"
-		     "When no PVR is specified -7 is assumed"
+		     "When no PVR is specified -8 is assumed"
 		     "\n"
 		     "Pipe to 'dtc -I dtb -O dts' for human readable output\n");
 	}
diff --git a/hdata/vpd.c b/hdata/vpd.c
index a29155a..3c480b4 100644
--- a/hdata/vpd.c
+++ b/hdata/vpd.c
@@ -702,7 +702,6 @@ static void iohub_vpd_parse(void)
 			continue;
 		}
 
-		/* On P7, the keyword VPD will not be NULL */
 		if (HDIF_get_idata(iohub_hdr,
 				   CECHUB_ASCII_KEYWORD_VPD, &vpd_sz))
 			dt_add_vpd_node(iohub_hdr, CECHUB_FRU_ID_DATA,