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| author | Christophe Lombard <clombard@linux.vnet.ibm.com> | 2021-10-14 17:56:51 +0200 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-10-19 12:26:01 +0530 |
| commit | 768f67e686e5691a6d6d956f625ce455d3b48fb5 (patch) | |
| tree | 5bd43725c341f3c8014c2e0cf3a88f71f61bfa4b /hdata | |
| parent | b10c12c63a4f58fe2c31dafdc5269c65b3a8a613 (diff) | |
| download | skiboot-768f67e686e5691a6d6d956f625ce455d3b48fb5.zip skiboot-768f67e686e5691a6d6d956f625ce455d3b48fb5.tar.gz skiboot-768f67e686e5691a6d6d956f625ce455d3b48fb5.tar.bz2 | |
pau: introduce support
OpenCapi for P10 is included in the P10 chip. This requires OCAPI capable
PHYs, Datalink Layer Logic and Transaction Layer Logic to be included.
The PHYs are the physical connection to the OCAPI interconnect.
The Datalink Layer provides link training.
The Transaction Layer executes the cache coherent and data movement
commands on the P10 chip.
The PAU provides the Transaction Layer functionality for the OCAPI
link(s) on the P10 chip.
The P10 PAU supports two OCAPI links. Six accelerator units PAUs are
instantiated on the P10 chip for a total of twelve OCAPI links.
This patch adds PAU opencapi structure for supporting OpenCapi5.
hw/pau.c file contains main of PAU management functions.
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'hdata')
| -rw-r--r-- | hdata/spira.c | 31 | ||||
| -rw-r--r-- | hdata/spira.h | 2 |
2 files changed, 25 insertions, 8 deletions
diff --git a/hdata/spira.c b/hdata/spira.c index baa2375..1a35146 100644 --- a/hdata/spira.c +++ b/hdata/spira.c @@ -966,21 +966,38 @@ static void add_nx(void) static void add_nmmu(void) { struct dt_node *xscom, *nmmu; - u32 scom; + u32 scom1, scom2; + u32 chip_id; /* Nest MMU only exists on POWER9 or later */ if (proc_gen < proc_gen_p9) return; - if (proc_gen == proc_gen_p9) - scom = 0x5012c40; - else - scom = 0x2010c40; + if (proc_gen == proc_gen_p10) { + scom1 = 0x2010c40; + scom2 = 0x3010c40; + } else + scom1 = 0x5012c40; dt_for_each_compatible(dt_root, xscom, "ibm,xscom") { - nmmu = dt_new_addr(xscom, "nmmu", scom); + nmmu = dt_new_addr(xscom, "nmmu", scom1); dt_add_property_strings(nmmu, "compatible", "ibm,power9-nest-mmu"); - dt_add_property_cells(nmmu, "reg", scom, 0x20); + dt_add_property_cells(nmmu, "reg", scom1, 0x20); + + /* + * P10 has a second nMMU, a.k.a "south" nMMU. + * It exists only on P1 and P3 + */ + if (proc_gen == proc_gen_p10) { + + chip_id = __dt_get_chip_id(xscom); + if (chip_id != 2 && chip_id != 6) + continue; + + nmmu = dt_new_addr(xscom, "nmmu", scom2); + dt_add_property_strings(nmmu, "compatible", "ibm,power9-nest-mmu"); + dt_add_property_cells(nmmu, "reg", scom2, 0x20); + } } } diff --git a/hdata/spira.h b/hdata/spira.h index afdc922..8def23b 100644 --- a/hdata/spira.h +++ b/hdata/spira.h @@ -1152,7 +1152,7 @@ struct sppcrd_smp_link { __be16 pci_sideband_slot_idx; __be16 slca_idx; /* SLCA index of the *external* port */ - __be16 reserved; + __be16 opt_id; /* nvlink/ocapi detection devices */ __be32 i2c_link_cable; |