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2 daysMdePkg: Remove the old name of LoongArch CSR 0x20Chao Li1-1/+0
Since all places where the old name was used for the LoongArch CSR 0x20 regiser have been changed to the new name, the old name is removed. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn>
2 daysMdePkg: Rename the LoongArch CSR 0x20 registerChao Li1-0/+1
Added a new name for CSR 0x20 because LoongArch SPEC has adjustd the CSR 0x20 register name. Ref: LoongArch Reference Manual Vol 1, Seciton 7.1. https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#control-and-status-registers Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn>
2024-07-15MdePkg/Library: Add RISCV64 support to BaseRngLibDhaval1-0/+10
The ratified RISC-V crypto scalar extensions provide entropy bits via the seed CSR, as exposed by the Zkr extension. The Zkr extension is ratified and provides 16 bits of entropy seed when reading the SEED CSR. Guarded by a RISCV64 Feature PCD, 64-bit random numbers can be accumulated from the `seed` CSR. This driver is based on the driver in the Linux kernel. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Co-authored-by: Tim Wawrzynczak <tim@rivosinc.com>
2024-07-12MdePkg/StmApi.h: Add SMM_REV_ID definition for STM headerMichael Kubacki1-0/+2
The `SMM_REV_ID` is defined in the STM specification: https://www.intel.com/content/www/us/en/content-details/671521/smi-transfer-monitor-stm-developer-or-user-guide.html?wapkw=stm, section 10.1.1. This adds it into the `StmApi.h` for potential STM usage. Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
2024-07-04MdePkg/Register/Amd: Define all bits from MSR_SEV_STATUS_REGISTERAlexey Kardashevskiy1-4/+91
For now we need DebugSwap but others are likely to be needed too. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Alexey Kardashevskiy <aik@amd.com> Changes: v5: * "rb" from Tom v4: * added more from April/2024 APM
2024-06-26MdePkg/ArchitecturalMsr.h: add #defines for MTRR cache typesGerd Hoffmann1-0/+7
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2024-06-18MdePkg/Include: Update AMD specification referencesPaul Grimes2-2/+2
Update AMD sepcification references (code comments) as part of a refactor of MSR definitions and SEV-SNP related defines, which aims to remove family-specific references (filename) as these defines are common to all modern EPYC Processors. Signed-off-by: Paul Grimes <paul.grimes@amd.com>
2024-06-18MdePkg/Include: Update Msr.h header guard definePaul Grimes1-2/+2
Update the Msr.h eader guard to comply with latest edk2 coding guidelines. This change is part of a refactor of MSR definitions and SEV-SNP related defines, which aims to remove family-specific references (filename) as these defines are common to all modern EPYC Processors. Signed-off-by: Paul Grimes <paul.grimes@amd.com>
2024-06-18MdePkg/Include: Remove deprecated AMD SEV-SNP header filePaul Grimes1-153/+0
Delete Fam17Msr.h as part of a refactor of MSR definitions and SEV-SNP related defines, which aims to remove family-specific references (filename) as these defines are common to all modern EPYC Processors. Signed-off-by: Paul Grimes <paul.grimes@amd.com>
2024-06-18MdePkg/Include: Update reference to SEV-SNP header filePaul Grimes1-1/+1
Update reference to SevSnpMsr.h as part of a refactor of MSR definitions and SEV-SNP related defines. Remove family-specific references (filename) as these defines are common to all modern EPYC Processors. Signed-off-by: Paul Grimes <paul.grimes@amd.com>
2024-06-18MdePkg/Include: Add AMD SEV-SNP header filePaul Grimes1-0/+153
Add SevSnpMsr.h as part of a refactor of MSR definitions and SEV-SNP related defines, which aims to remove family-specific references (filename) as these defines are common to all modern EPYC Processors. Signed-off-by: Paul Grimes <paul.grimes@amd.com>
2024-06-05MdePkg: Remove non-ASCII characters from header fileNeo Hsueh2-6/+6
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4775 Signed-off-by: Neo Hsueh <Hong-Chih.Hsueh@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Jiangang He <jiangang.he@amd.com>
2024-04-17MdePkg/Register/Amd: Define the SVSM related informationTom Lendacky4-2/+156
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4654 The Secure VM Service Module specification defines the interfaces needed to allow multi-VMPL level execution of an SEV-SNP guest. Define the SVSM related structures for the SVSM Calling Area as well as the SVSM CAA MSR. The SVSM CAA MSR is an MSR register that is reserved for software use and will not be implemented in hardware. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
2024-04-17MdePkg: Avoid hardcoded value for number of Page State Change entriesTom Lendacky1-3/+4
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4654 The SNP_PAGE_STATE_MAX_ENTRY is based on the number of entries that can fit in the GHCB shared buffer. As a result, the SNP_PAGE_STATE_CHANGE_INFO structure maps the full GHCB shared buffer based on the shared buffer size being 2032 bytes. Instead of using a hardcoded value for SNP_PAGE_STATE_MAX_ENTRY, use a build calculated value. Since the SNP_PAGE_STATE_CHANGE_INFO is used as a mapping, eliminate the hardcoded array size so that the structure can be used based on any size buffer. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2024-04-17MdePkg: GHCB APIC ID retrieval support definitionsTom Lendacky1-1/+11
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4654 When an SVSM is present, starting the APs requires knowledge of the APIC IDs. Create the definitions required to retrieve and hold the APIC ID information of all the vCPUs present in the guest. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
2024-02-06MdePkg: Add LoongArch Cpucfg functionChao Li1-0/+565
Add LoongArch AsmCpucfg function and Cpucfg definitions. Also added Include/Register/LoongArch64/Cpucfg.h to IgnoreFiles of EccCheck. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2024-02-06MdePkg: Add the header file named Csr.h for LoongArch64Chao Li1-0/+263
Adding Csr.h for LoongArch64, it is use for accessing the CSR registers. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2024-01-31MdePkg: Adds AMD Extended CPU topology CPUIDAbdul Lateef Attar1-1/+22
Adds cpuid macro for AMD extended CPU topology. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Message-Id: <15199aaefbc497bb1ea7b20028c13ebedd8c488b.1705549445.git.AbdulLateef.Attar@amd.com> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Acked-by: Ray Ni <ray.ni@intel.com> Acked-by: Tom Lendacky <thomas.lendacky@amd.com>
2024-01-11MdePkg/BaseLib: RISC-V: Add function to update stimecmp registerSunil V L1-0/+3
stimecmp is a CSR supported only when Sstc extension is supported by the platform. This register can be used to set the timer interrupt directly in S-mode instead of going via SBI call. Add a function to update this register. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
2023-07-15MdePkg/Register: RISC-V: Add satp mode bits shift definitionTuan Phan1-3/+4
The satp mode bits shift is used cross modules. It should be defined in one place. Signed-off-by: Tuan Phan <tphan@ventanamicro.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2023-07-03MdePkg: Adds AMD SMRAM save state mapAbdul Lateef Attar1-0/+194
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182 Adds an SMM SMRAM save-state map for AMD processors. SMRAM save state maps for the AMD processor family are now supported. Save state map structure is added based on AMD64 Architecture Programmer's Manual, Volume 2, Section 10.2. The AMD legacy save state map for 32-bit architecture is defined. The AMD64 save state map for 64-bit architecture is defined.  Also added Amd/SmramSaveStateMap.h to IgnoreFiles of EccCheck, because structures defined in this file are derived from Intel/SmramSaveStateMap.h. Cc: Paul Grimes <paul.grimes@amd.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Abdul Lateef Attar <abdattar@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2023-06-15UefiCpuPkg: RISC-V: TimerLib: Fix delay function to use 64-bitTuan Phan1-1/+0
The timer compare register is 64-bit so simplifying the delay function. Cc: Andrei Warkentin <andrei.warkentin@intel.com> Signed-off-by: Tuan Phan <tphan@ventanamicro.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2023-04-01MdePkg: Add TME-MK related CPUID and MSR definitionsRay Ni2-3/+112
TME (Total Memory Encryption) is the capability to encrypt the entirety of physical memory of a system. TME-MK (Total Memory Encryption-Multi-Key) builds on TME and adds support for multiple encryption keys. The patch adds some necessary CPUID/MSR definitions for TME-MK. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2023-02-16MdePkg/Register: Add register definition header files for RISC-VSunil V L2-0/+144
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Add register definitions and access routines for RISC-V. These headers are leveraged from opensbi repo. Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2022-04-02MdePkg: Update Cpuid.h for TdxMin Xu1-2/+33
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429 Guest software can be designed to run either as a TD, as a legacy virtual machine, or directly on the CPU, based on enumeration of its run-time environment. [TDX-Module] Chap 10.2 defines the flow and the new CPUID leaf 0x21. [TDX-Module] Architecture Specification: Intel(R) Trust Domain Extensions Module, Chap 10.2, 344425-003US, August 2021 https://www.intel.com/content/dam/develop/external/us/en/documents/ tdx-module-1.0-public-spec-v0.931.pdf Cc: Ray Ni <ray.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
2021-12-09MdePkg/GHCB: increase the GHCB protocol max versionBrijesh Singh1-1/+1
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 Now that OvmfPkg supports version 2 of the GHCB specification, bump the protocol version. Cc: Michael Roth <michael.roth@amd.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Ray Ni <ray.ni@intel.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
2021-12-07MdePkg: Apply uncrustify changesMichael Kubacki32-8630/+6991
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the MdePkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-10-28MdePkg Cpuid.h: Define CPUID.(EAX=7,ECX=0):EDX[30]Zeng, Star1-2/+2
This patch follows new Intel SDM to define CPUID.(EAX=7,ECX=0):EDX[30]. Signed-off-by: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Ray Ni <ray.ni@intel.com>
2021-05-29MdePkg/Register/Amd: define GHCB macros for SNP AP creationTom Lendacky1-0/+84
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 Version 2 of GHCB introduces NAE for creating AP when SEV-SNP is enabled in the guest VM. See the GHCB specification, Table 5 "List of Supported Non-Automatic Events" and sections 4.1.9 and 4.3.2, for further details. While at it, define the VMSA state save area that is required for creating the AP. The save area format is defined in AMD APM volume 2, Table B-4 (there is a mistake in the table that defines the size of the reserved area at offset 0xc8 as a dword, when it is actually a word). The format of the save area segment registers is further defined in AMD APM volume 2, sections 10 and 15.5. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-7-brijesh.singh@amd.com> [lersek@redhat.com: fix typo in BZ reference]
2021-05-29MdePkg/Register/Amd: define GHCB macro for the Page State ChangeBrijesh Singh2-0/+48
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 The Page State Change NAE exit will be used by the SEV-SNP guest to request a page state change using the GHCB protocol. See the GHCB spec section 4.1.6 and 2.3.1 for more detail on the structure definitions. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Erdem Aktas <erdemaktas@google.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-6-brijesh.singh@amd.com>
2021-05-29MdePkg/Register/Amd: define GHCB macro for Register GPA structureBrijesh Singh1-0/+7
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 An SEV-SNP guest is required to perform the GHCB GPA registration. See the GHCB specification for further details. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Erdem Aktas <erdemaktas@google.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-5-brijesh.singh@amd.com>
2021-05-29MdePkg/Register/Amd: define GHCB macros for hypervisor feature detectionBrijesh Singh2-0/+15
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 Version 2 of GHCB introduces advertisement of features that are supported by the hypervisor. See the GHCB spec section 2.2 for an additional details. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Erdem Aktas <erdemaktas@google.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-4-brijesh.singh@amd.com>
2021-05-29MdePkg/Register/Amd: realign macros with more space for future expansionBrijesh Singh2-11/+11
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 Version 2 of the GHCB spec introduces several new SNP-specific NAEs. Unfortunately, the names for those NAEs break the alignment. Add some white spaces so that the SNP support patches do not break the alignment. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-3-brijesh.singh@amd.com>
2021-05-29MdePkg/Register/Amd: expand the SEV MSR to include the SNP definitionBrijesh Singh1-1/+6
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 Define the SEV-SNP MSR bits. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-2-brijesh.singh@amd.com>
2021-04-20MdePkg/Cpuid.h: Define new element in CPUID Leaf(07h) data structure.Jason1-3/+11
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3309 Define new element(Hybird) in CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (07h) data structure. Signed-off-by: Jason Lou <yun.lou@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed: Ray Ni <ray.ni@intel.com>
2021-01-26MdePkg/Cpuid.h: Change and add some macro definitions.Lou, Yun1-5/+14
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3105 Change and add some macro definitions about CPUID_HYBRID_INFORMATION Leaf(1Ah). Signed-off-by: Jason Lou <yun.lou@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
2021-01-19MdePkg/Cpuid.h: Add CPUID_HYBRID_INFORMATION Leaf(1Ah).Jason Lou1-1/+62
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3105 The UefiCpuPkg/CpuCacheInfoLib will reference new definition about CPUID_HYBRID_INFORMATION Leaf(1Ah). Signed-off-by: Jason Lou <yun.lou@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
2020-11-10MdePkg: Clean up GHCB field offsets and save areaTom Lendacky1-26/+17
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3008 Use OFFSET_OF () and sizeof () to calculate the GHCB register field offsets instead of hardcoding the values in the GHCB_REGISTER enum. Define only fields that are used per the GHCB specification, which will result in removing some fields and adding others. Also, remove the DR7 field from the GHCB_SAVE_AREA structure since it is not used/defined in the GHCB specification and then rename the reserved fields as appropriate. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Message-Id: <5e9245c7600b9b2d55dd7586b8df28b91b75b72b.1604685192.git.thomas.lendacky@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2020-08-16MdePkg: Add a structure definition for the GHCBTom Lendacky1-0/+166
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 The GHCB is used by an SEV-ES guest for communicating between the guest and the hypervisor. Create the GHCB definition as defined by the GHCB protocol definition. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2020-08-16MdePkg: Add the MSR definition for the GHCB registerTom Lendacky1-0/+46
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 For SEV-ES, the GHCB page address is stored in the GHCB MSR register (0xc0010130). Define the register and the format used for register during GHCB protocol negotiation. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2020-02-10MdePkg/Register: Fix various typosAntoine Coeur6-9/+9
Fix various typos in comments and documentation. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Antoine Coeur <coeur@gmx.fr> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Philippe Mathieu-Daude <philmd@redhat.com> Message-Id: <20200207010831.9046-29-philmd@redhat.com>
2019-08-09UefiCpuPkg|MdePkg: Move Register/ folder to MdePkg/Include/Ni, Ray32-0/+53560
The patch moves all files under UefiCpuPkg/Include/Register/ to MdePkg/Include/Register using following detailed approaches: 1. Move UefiCpuPkg/Include/Register/Amd/ to MdePkg/Include/Register/Amd folder. 2. Move remaining in UefiCpuPkg/Include/Register/ to MdePkg/Include/Register/Intel folder. 3. Create wrapper header files under UefiCpuPkg/Include/Register/ to include the accordingly files in MdePkg/Include/Register/Intel. This is to avoid build break because code in other repos like edk2-platform includes the file from UefiCpuPkg. The wrapper header files will be removed after all consumers code is updated. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com>
2019-08-09MdePkg/Cpuid.h: Move Cpuid.h from UefiCpuPkg to MdePkgNi, Ray1-0/+3997
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008 MdeModulePkg/DxeIpl needs to get CPUID output for CPU 5-level paging capability detection. In order to use the macros/structures defined in UefiCpuPkg/Include/Register/Cpuid.h, the patch adds Intel/Cpuid.h to MdePkg/Include/Register/ directory and updates Cpuid.h in UefiCpuPkg to include the new one in MdePkg. Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Eric Dong <eric.dong@intel.com>
generated by cgit v1.1 at 2024-09-01 23:25:18 +0000