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| author | Sunil V L <sunilvl@ventanamicro.com> | 2023-06-24 03:38:10 +0530 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2024-01-11 12:07:42 +0000 |
| commit | 8ae17a71afc31410e50d86d008c2a7b9df1a7d22 (patch) | |
| tree | 328f1ae632ec6bdea475731ab522f0f4bfe215c5 /MdePkg/Include/Register | |
| parent | fd629ef6e3dc894ddcfefe21542190f26c8c5c65 (diff) | |
| download | edk2-8ae17a71afc31410e50d86d008c2a7b9df1a7d22.zip edk2-8ae17a71afc31410e50d86d008c2a7b9df1a7d22.tar.gz edk2-8ae17a71afc31410e50d86d008c2a7b9df1a7d22.tar.bz2 | |
MdePkg/BaseLib: RISC-V: Add function to update stimecmp register
stimecmp is a CSR supported only when Sstc extension is supported by the
platform. This register can be used to set the timer interrupt directly in
S-mode instead of going via SBI call. Add a function to update this
register.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Diffstat (limited to 'MdePkg/Include/Register')
| -rw-r--r-- | MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h index 2bde8db..8ccdea2 100644 --- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h @@ -96,6 +96,9 @@ /* Supervisor Protection and Translation */
#define CSR_SATP 0x180
+/* Sstc extension */
+#define CSR_STIMECMP 0x14D
+
/* Trap/Exception Causes */
#define CAUSE_MISALIGNED_FETCH 0x0
#define CAUSE_FETCH_ACCESS 0x1
|