Age | Commit message (Expand) | Author | Files | Lines |
2024-10-16 | target/loongarch: Avoid bits shift exceeding width of bool type | Bibo Mao | 1 | -5/+1 |
2024-10-13 | target/arm: Fix alignment fault priority in get_phys_addr_lpae | Richard Henderson | 1 | -21/+30 |
2024-10-13 | target/arm: Implement TCGCPUOps.tlb_fill_align | Richard Henderson | 4 | -34/+23 |
2024-10-13 | target/arm: Move device detection earlier in get_phys_addr_lpae | Richard Henderson | 1 | -24/+25 |
2024-10-13 | target/arm: Pass MemOp to get_phys_addr_lpae | Richard Henderson | 1 | -2/+4 |
2024-10-13 | target/arm: Pass MemOp through get_phys_addr_twostage | Richard Henderson | 1 | -4/+6 |
2024-10-13 | target/arm: Pass MemOp to get_phys_addr_nogpc | Richard Henderson | 1 | -6/+8 |
2024-10-13 | target/arm: Pass MemOp to get_phys_addr_gpc | Richard Henderson | 1 | -5/+6 |
2024-10-13 | target/arm: Pass MemOp to get_phys_addr_with_space_nogpc | Richard Henderson | 3 | -6/+8 |
2024-10-13 | target/arm: Pass MemOp to get_phys_addr | Richard Henderson | 4 | -7/+8 |
2024-10-13 | target/hppa: Implement TCGCPUOps.tlb_fill_align | Richard Henderson | 3 | -13/+16 |
2024-10-13 | target/hppa: Handle alignment faults in hppa_get_physical_address | Richard Henderson | 1 | -1/+6 |
2024-10-13 | target/hppa: Fix priority of T, D, and B page faults | Richard Henderson | 1 | -3/+5 |
2024-10-13 | target/hppa: Perform access rights before protection id check | Richard Henderson | 1 | -6/+6 |
2024-10-13 | target/hppa: Add MemOp argument to hppa_get_physical_address | Richard Henderson | 4 | -7/+8 |
2024-10-13 | include/exec/memop: Rename get_alignment_bits | Richard Henderson | 2 | -3/+3 |
2024-10-13 | target/i386/gdbstub: Expose orig_ax | Ilya Leoshkevich | 3 | -0/+53 |
2024-10-13 | target/i386/gdbstub: Factor out gdb_get_reg() and gdb_write_reg() | Ilya Leoshkevich | 1 | -21/+30 |
2024-10-13 | tcg: remove singlestep_enabled from DisasContextBase | Paolo Bonzini | 1 | -2/+3 |
2024-10-08 | target/m68k: Always return a temporary from gen_lea_mode | Richard Henderson | 1 | -4/+9 |
2024-10-07 | target/s390x: Use explicit big-endian LD/ST API | Philippe Mathieu-Daudé | 2 | -18/+18 |
2024-10-07 | target/s390x: Replace ldtul_p() -> ldq_p() | Philippe Mathieu-Daudé | 1 | -15/+15 |
2024-10-07 | target/m68k: Use explicit big-endian LD/ST API | Philippe Mathieu-Daudé | 2 | -6/+6 |
2024-10-04 | Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging | Peter Maydell | 11 | -168/+267 |
2024-10-03 | target/i386/kvm: Report which action failed in kvm_arch_put/get_registers | Julia Suvorova | 1 | -0/+23 |
2024-10-03 | kvm: Allow kvm_arch_get/put_registers to accept Error** | Julia Suvorova | 7 | -14/+14 |
2024-10-03 | target/i386: Expose IBPB-BRTYPE and SBPB CPUID bits to the guest | Fabiano Rosas | 1 | -2/+2 |
2024-10-03 | kvm/i386: replace identity_base variable with a constant | Paolo Bonzini | 1 | -18/+18 |
2024-10-03 | kvm/i386: refactor kvm_arch_init and split it into smaller functions | Ani Sinha | 1 | -126/+201 |
2024-10-03 | Merge tag 'warn-pull-request' of https://gitlab.com/marcandre.lureau/qemu int... | Peter Maydell | 1 | -12/+14 |
2024-10-02 | Merge tag 'pull-riscv-to-apply-20241002' of https://github.com/alistair23/qem... | Peter Maydell | 11 | -17/+160 |
2024-10-02 | target/loongarch: fix -Werror=maybe-uninitialized false-positive | Marc-André Lureau | 1 | -12/+14 |
2024-10-02 | kvm/i386: fix return values of is_host_cpu_intel() | Ani Sinha | 2 | -4/+4 |
2024-10-02 | kvm/i386: make kvm_filter_msr() and related definitions private to kvm module | Ani Sinha | 2 | -12/+11 |
2024-10-02 | target/i386: Raise the highest index value used for any VMCS encoding | Lei Wang | 2 | -1/+9 |
2024-10-02 | target/i386: Add VMX control bits for nested FRED support | Xin Li (Intel) | 1 | -2/+2 |
2024-10-02 | target/i386: Delete duplicated macro definition CR4_FRED_MASK | Xin Li (Intel) | 1 | -6/+0 |
2024-10-02 | target/riscv/cpu_helper: Fix linking problem with semihosting disabled | Thomas Huth | 2 | -2/+4 |
2024-10-02 | target/riscv32: Fix masking of physical address | Andrew Jones | 1 | -3/+3 |
2024-10-02 | target: riscv: Add Svvptc extension support | Alexandre Ghiti | 2 | -0/+3 |
2024-10-02 | target/riscv: Add textra matching condition for the triggers | Alvin Chang | 2 | -1/+47 |
2024-10-02 | target/riscv: Preliminary textra trigger CSR writting support | Alvin Chang | 2 | -6/+73 |
2024-10-02 | target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension | Maria Klauchek | 1 | -0/+6 |
2024-10-02 | target/riscv: Stop timer with infinite timecmp | Andrew Jones | 1 | -0/+1 |
2024-10-02 | target/riscv/kvm: Fix the group bit setting of AIA | Andrew Jones | 1 | -1/+3 |
2024-10-02 | target: riscv: Enable Bit Manip for OpenTitan Ibex CPU | Alistair Francis | 1 | -0/+5 |
2024-10-02 | target/riscv: fix za64rs enabling | Vladimir Isaev | 1 | -1/+1 |
2024-10-02 | target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule | Daniel Henrique Barboza | 1 | -3/+10 |
2024-10-02 | target/riscv: Add a property to set vl to ceil(AVL/2) | Jason Chien | 3 | -0/+4 |
2024-10-01 | target/arm: Avoid target_ulong for physical address lookups | Ard Biesheuvel | 2 | -10/+10 |