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2024-10-16target/loongarch: Avoid bits shift exceeding width of bool typeBibo Mao1-5/+1
2024-10-13target/arm: Fix alignment fault priority in get_phys_addr_lpaeRichard Henderson1-21/+30
2024-10-13target/arm: Implement TCGCPUOps.tlb_fill_alignRichard Henderson4-34/+23
2024-10-13target/arm: Move device detection earlier in get_phys_addr_lpaeRichard Henderson1-24/+25
2024-10-13target/arm: Pass MemOp to get_phys_addr_lpaeRichard Henderson1-2/+4
2024-10-13target/arm: Pass MemOp through get_phys_addr_twostageRichard Henderson1-4/+6
2024-10-13target/arm: Pass MemOp to get_phys_addr_nogpcRichard Henderson1-6/+8
2024-10-13target/arm: Pass MemOp to get_phys_addr_gpcRichard Henderson1-5/+6
2024-10-13target/arm: Pass MemOp to get_phys_addr_with_space_nogpcRichard Henderson3-6/+8
2024-10-13target/arm: Pass MemOp to get_phys_addrRichard Henderson4-7/+8
2024-10-13target/hppa: Implement TCGCPUOps.tlb_fill_alignRichard Henderson3-13/+16
2024-10-13target/hppa: Handle alignment faults in hppa_get_physical_addressRichard Henderson1-1/+6
2024-10-13target/hppa: Fix priority of T, D, and B page faultsRichard Henderson1-3/+5
2024-10-13target/hppa: Perform access rights before protection id checkRichard Henderson1-6/+6
2024-10-13target/hppa: Add MemOp argument to hppa_get_physical_addressRichard Henderson4-7/+8
2024-10-13include/exec/memop: Rename get_alignment_bitsRichard Henderson2-3/+3
2024-10-13target/i386/gdbstub: Expose orig_axIlya Leoshkevich3-0/+53
2024-10-13target/i386/gdbstub: Factor out gdb_get_reg() and gdb_write_reg()Ilya Leoshkevich1-21/+30
2024-10-13tcg: remove singlestep_enabled from DisasContextBasePaolo Bonzini1-2/+3
2024-10-08target/m68k: Always return a temporary from gen_lea_modeRichard Henderson1-4/+9
2024-10-07target/s390x: Use explicit big-endian LD/ST APIPhilippe Mathieu-Daudé2-18/+18
2024-10-07target/s390x: Replace ldtul_p() -> ldq_p()Philippe Mathieu-Daudé1-15/+15
2024-10-07target/m68k: Use explicit big-endian LD/ST APIPhilippe Mathieu-Daudé2-6/+6
2024-10-04Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell11-168/+267
2024-10-03target/i386/kvm: Report which action failed in kvm_arch_put/get_registersJulia Suvorova1-0/+23
2024-10-03kvm: Allow kvm_arch_get/put_registers to accept Error**Julia Suvorova7-14/+14
2024-10-03target/i386: Expose IBPB-BRTYPE and SBPB CPUID bits to the guestFabiano Rosas1-2/+2
2024-10-03kvm/i386: replace identity_base variable with a constantPaolo Bonzini1-18/+18
2024-10-03kvm/i386: refactor kvm_arch_init and split it into smaller functionsAni Sinha1-126/+201
2024-10-03Merge tag 'warn-pull-request' of https://gitlab.com/marcandre.lureau/qemu int...Peter Maydell1-12/+14
2024-10-02Merge tag 'pull-riscv-to-apply-20241002' of https://github.com/alistair23/qem...Peter Maydell11-17/+160
2024-10-02target/loongarch: fix -Werror=maybe-uninitialized false-positiveMarc-André Lureau1-12/+14
2024-10-02kvm/i386: fix return values of is_host_cpu_intel()Ani Sinha2-4/+4
2024-10-02kvm/i386: make kvm_filter_msr() and related definitions private to kvm moduleAni Sinha2-12/+11
2024-10-02target/i386: Raise the highest index value used for any VMCS encodingLei Wang2-1/+9
2024-10-02target/i386: Add VMX control bits for nested FRED supportXin Li (Intel)1-2/+2
2024-10-02target/i386: Delete duplicated macro definition CR4_FRED_MASKXin Li (Intel)1-6/+0
2024-10-02target/riscv/cpu_helper: Fix linking problem with semihosting disabledThomas Huth2-2/+4
2024-10-02target/riscv32: Fix masking of physical addressAndrew Jones1-3/+3
2024-10-02target: riscv: Add Svvptc extension supportAlexandre Ghiti2-0/+3
2024-10-02target/riscv: Add textra matching condition for the triggersAlvin Chang2-1/+47
2024-10-02target/riscv: Preliminary textra trigger CSR writting supportAlvin Chang2-6/+73
2024-10-02target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extensionMaria Klauchek1-0/+6
2024-10-02target/riscv: Stop timer with infinite timecmpAndrew Jones1-0/+1
2024-10-02target/riscv/kvm: Fix the group bit setting of AIAAndrew Jones1-1/+3
2024-10-02target: riscv: Enable Bit Manip for OpenTitan Ibex CPUAlistair Francis1-0/+5
2024-10-02target/riscv: fix za64rs enablingVladimir Isaev1-1/+1
2024-10-02target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied ruleDaniel Henrique Barboza1-3/+10
2024-10-02target/riscv: Add a property to set vl to ceil(AVL/2)Jason Chien3-0/+4
2024-10-01target/arm: Avoid target_ulong for physical address lookupsArd Biesheuvel2-10/+10