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| author | Vladimir Isaev <vladimir.isaev@syntacore.com> | 2024-08-23 09:34:31 +0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-10-02 15:11:51 +1000 |
| commit | d1f872e15f9b489f121ab8570270c771175254ec (patch) | |
| tree | 04a0caad51ce01c87d3cdae4c817ee15aad2ca7a /target | |
| parent | b0d43815a10b884997407e1864ea264144cff265 (diff) | |
| download | qemu-d1f872e15f9b489f121ab8570270c771175254ec.zip qemu-d1f872e15f9b489f121ab8570270c771175254ec.tar.gz qemu-d1f872e15f9b489f121ab8570270c771175254ec.tar.bz2 | |
target/riscv: fix za64rs enabling
za64rs requires priv 1.12 when enabled by priv 1.11.
This fixes annoying warning:
warning: disabling za64rs extension for hart 0x00000000 because privilege spec version does not match
on priv 1.11 CPUs.
Fixes: 68c9e54beae8 ("target/riscv: do not enable all named features by default")
Signed-off-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240823063431.17474-1-vladimir.isaev@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/cpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cc55525..0f8189b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -115,7 +115,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm), ISA_EXT_DATA_ENTRY(zimop, PRIV_VERSION_1_13_0, ext_zimop), ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), - ISA_EXT_DATA_ENTRY(za64rs, PRIV_VERSION_1_12_0, has_priv_1_11), + ISA_EXT_DATA_ENTRY(za64rs, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(zaamo, PRIV_VERSION_1_12_0, ext_zaamo), ISA_EXT_DATA_ENTRY(zabha, PRIV_VERSION_1_13_0, ext_zabha), ISA_EXT_DATA_ENTRY(zacas, PRIV_VERSION_1_12_0, ext_zacas), |