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author | Thomas Huth <thuth@redhat.com> | 2024-09-06 11:48:58 +0200 |
---|---|---|
committer | Alistair Francis <alistair.francis@wdc.com> | 2024-10-02 15:11:51 +1000 |
commit | 177060d860ec94df7110963be289d0596ae6807b (patch) | |
tree | ea807b04b4c94d3014dd31db1f20388e7289aa9f /target | |
parent | b27402813e7007ab82ddd914c092777f11fab6ed (diff) | |
download | qemu-177060d860ec94df7110963be289d0596ae6807b.zip qemu-177060d860ec94df7110963be289d0596ae6807b.tar.gz qemu-177060d860ec94df7110963be289d0596ae6807b.tar.bz2 |
target/riscv/cpu_helper: Fix linking problem with semihosting disabled
If QEMU has been configured with "--without-default-devices", the build
is currently failing with:
/usr/bin/ld: libqemu-riscv32-softmmu.a.p/target_riscv_cpu_helper.c.o:
in function `riscv_cpu_do_interrupt':
.../qemu/target/riscv/cpu_helper.c:1678:(.text+0x2214): undefined
reference to `do_common_semihosting'
We always want semihosting to be enabled if TCG is available, so change
the "imply" statements in the Kconfig file to "select", and make sure to
avoid calling into do_common_semihosting() if TCG is not available.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240906094858.718105-1-thuth@redhat.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
-rw-r--r-- | target/riscv/Kconfig | 4 | ||||
-rw-r--r-- | target/riscv/cpu_helper.c | 2 |
2 files changed, 4 insertions, 2 deletions
diff --git a/target/riscv/Kconfig b/target/riscv/Kconfig index c332616..11bc09b 100644 --- a/target/riscv/Kconfig +++ b/target/riscv/Kconfig @@ -1,9 +1,9 @@ config RISCV32 bool - imply ARM_COMPATIBLE_SEMIHOSTING if TCG + select ARM_COMPATIBLE_SEMIHOSTING if TCG select DEVICE_TREE # needed by boot.c config RISCV64 bool - imply ARM_COMPATIBLE_SEMIHOSTING if TCG + select ARM_COMPATIBLE_SEMIHOSTING if TCG select DEVICE_TREE # needed by boot.c diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 4b2c727..a935377 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1674,10 +1674,12 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (!async) { /* set tval to badaddr for traps with address information */ switch (cause) { +#ifdef CONFIG_TCG case RISCV_EXCP_SEMIHOST: do_common_semihosting(cs); env->pc += 4; return; +#endif case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: case RISCV_EXCP_LOAD_ADDR_MIS: |