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Author
Files
Lines
2022-01-21
target/riscv: Relax UXL field for debugging
LIU Zhiwei
1
-4
/
+4
2022-01-21
target/riscv: Enable uxl field write
LIU Zhiwei
2
-6
/
+25
2022-01-21
target/riscv: Set default XLEN for hypervisor
LIU Zhiwei
1
-0
/
+10
2022-01-21
target/riscv: Adjust scalar reg in vector with XLEN
LIU Zhiwei
1
-1
/
+1
2022-01-21
target/riscv: Adjust vector address with mask
LIU Zhiwei
1
-10
/
+15
2022-01-21
target/riscv: Fix check range for first fault only
LIU Zhiwei
1
-2
/
+2
2022-01-21
target/riscv: Remove VILL field in VTYPE
LIU Zhiwei
1
-1
/
+0
2022-01-21
target/riscv: Adjust vsetvl according to XLEN
LIU Zhiwei
2
-2
/
+10
2022-01-21
target/riscv: Split out the vill from vtype
LIU Zhiwei
5
-6
/
+19
2022-01-21
target/riscv: Split pm_enabled into mask and base
LIU Zhiwei
3
-23
/
+16
2022-01-21
target/riscv: Calculate address according to XLEN
LIU Zhiwei
5
-69
/
+21
2022-01-21
target/riscv: Alloc tcg global for cur_pm[mask|base]
LIU Zhiwei
1
-24
/
+8
2022-01-21
target/riscv: Create current pm fields in env
LIU Zhiwei
5
-0
/
+68
2022-01-21
target/riscv: Adjust csr write mask with XLEN
LIU Zhiwei
2
-5
/
+10
2022-01-21
target/riscv: Relax debug check for pm write
LIU Zhiwei
1
-0
/
+3
2022-01-21
target/riscv: Use gdb xml according to max mxlen
LIU Zhiwei
2
-24
/
+55
2022-01-21
target/riscv: Extend pc for runtime pc write
LIU Zhiwei
1
-3
/
+19
2022-01-21
target/riscv: Ignore the pc bits above XLEN
LIU Zhiwei
1
-1
/
+1
2022-01-21
target/riscv: Create xl field in env
LIU Zhiwei
5
-32
/
+46
2022-01-21
target/riscv: Sign extend pc for different XLEN
LIU Zhiwei
4
-9
/
+27
2022-01-21
target/riscv: Sign extend link reg for jal and jalr
LIU Zhiwei
2
-6
/
+2
2022-01-21
target/riscv: Don't save pc when exception return
LIU Zhiwei
3
-9
/
+6
2022-01-21
target/riscv: Adjust pmpcfg access with mxl
LIU Zhiwei
2
-8
/
+23
2022-01-21
target/riscv: rvv-1.0: Allow Zve32f extension to be turned on
Frank Chang
1
-0
/
+1
2022-01-21
target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns
Frank Chang
1
-0
/
+3
2022-01-21
target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns
Frank Chang
1
-0
/
+18
2022-01-21
target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns
Frank Chang
1
-0
/
+1
2022-01-21
target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns
Frank Chang
1
-0
/
+21
2022-01-21
target/riscv: rvv-1.0: Add Zve32f support for configuration insns
Frank Chang
1
-2
/
+2
2022-01-21
target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
Frank Chang
5
-4
/
+7
2022-01-21
target/riscv: rvv-1.0: Allow Zve64f extension to be turned on
Frank Chang
1
-0
/
+1
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns
Frank Chang
1
-3
/
+6
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns
Frank Chang
1
-7
/
+25
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns
Frank Chang
1
-1
/
+2
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns
Frank Chang
1
-10
/
+31
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns
Frank Chang
1
-2
/
+25
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns
Frank Chang
1
-6
/
+33
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for load and store insns
Frank Chang
1
-4
/
+15
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for configuration insns
Frank Chang
1
-2
/
+4
2022-01-21
target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
Frank Chang
5
-2
/
+16
2022-01-21
target/riscv: Support virtual time context synchronization
Yifei Jiang
1
-0
/
+30
2022-01-21
target/riscv: Implement virtual time adjusting with vm state changing
Yifei Jiang
1
-0
/
+15
2022-01-21
target/riscv: Add kvm_riscv_get/put_regs_timer
Yifei Jiang
2
-0
/
+79
2022-01-21
target/riscv: Add host cpu type
Yifei Jiang
2
-0
/
+16
2022-01-21
target/riscv: Handle KVM_EXIT_RISCV_SBI exit
Yifei Jiang
2
-1
/
+113
2022-01-21
target/riscv: Support setting external interrupt by KVM
Yifei Jiang
4
-1
/
+28
2022-01-21
target/riscv: Support start kernel directly by KVM
Yifei Jiang
6
-1
/
+75
2022-01-21
target/riscv: Implement kvm_arch_put_registers
Yifei Jiang
1
-1
/
+103
2022-01-21
target/riscv: Implement kvm_arch_get_registers
Yifei Jiang
1
-1
/
+111
2022-01-21
target/riscv: Implement function kvm_arch_init_vcpu
Yifei Jiang
1
-1
/
+33
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