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| author | Frank Chang <frank.chang@sifive.com> | 2022-01-18 09:45:10 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-21 15:52:56 +1000 |
| commit | 193fb5c9bd1fbf8a0b78c75f2056b0d7d9fc0ffe (patch) | |
| tree | bac6adb9cb66e10a670e311b386ca9bdb280fd0b /target | |
| parent | 40d78c85f6f321c00588230a400477250a85c2e7 (diff) | |
| download | qemu-193fb5c9bd1fbf8a0b78c75f2056b0d7d9fc0ffe.zip qemu-193fb5c9bd1fbf8a0b78c75f2056b0d7d9fc0ffe.tar.gz qemu-193fb5c9bd1fbf8a0b78c75f2056b0d7d9fc0ffe.tar.bz2 | |
target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns
Vector single-width floating-point reduction operations for EEW=32 are
supported for Zve64f extension.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-8-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/insn_trans/trans_rvv.c.inc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 56246a5..08f25e3 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2937,7 +2937,8 @@ GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_widen_check) static bool freduction_check(DisasContext *s, arg_rmrr *a) { return reduction_check(s, a) && - require_rvf(s); + require_rvf(s) && + require_zve64f(s); } GEN_OPFVV_TRANS(vfredsum_vs, freduction_check) |