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| author | Frank Chang <frank.chang@sifive.com> | 2022-01-18 09:45:05 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-21 15:52:56 +1000 |
| commit | c7a26fb2f6bafd45b983d81d180f624c0e8c4d2b (patch) | |
| tree | 37c67be3240be10137a905a82ae5249044eefac1 /target | |
| parent | b4a99d40276eb5bdfa849cc04344d9a2c4c820ef (diff) | |
| download | qemu-c7a26fb2f6bafd45b983d81d180f624c0e8c4d2b.zip qemu-c7a26fb2f6bafd45b983d81d180f624c0e8c4d2b.tar.gz qemu-c7a26fb2f6bafd45b983d81d180f624c0e8c4d2b.tar.bz2 | |
target/riscv: rvv-1.0: Add Zve64f support for configuration insns
All Zve* extensions support the vector configuration instructions.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-3-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/insn_trans/trans_rvv.c.inc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 6c285c9..5b47729 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -129,7 +129,8 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2) { TCGv s1, dst; - if (!require_rvv(s) || !has_ext(s, RVV)) { + if (!require_rvv(s) || + !(has_ext(s, RVV) || s->ext_zve64f)) { return false; } @@ -164,7 +165,8 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2) { TCGv dst; - if (!require_rvv(s) || !has_ext(s, RVV)) { + if (!require_rvv(s) || + !(has_ext(s, RVV) || s->ext_zve64f)) { return false; } |