index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
stable-9.1
stable-9.2
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
staging-9.1
staging-9.2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target
Age
Commit message (
Expand
)
Author
Files
Lines
2022-01-21
target/riscv: Split pm_enabled into mask and base
LIU Zhiwei
3
-23
/
+16
2022-01-21
target/riscv: Calculate address according to XLEN
LIU Zhiwei
5
-69
/
+21
2022-01-21
target/riscv: Alloc tcg global for cur_pm[mask|base]
LIU Zhiwei
1
-24
/
+8
2022-01-21
target/riscv: Create current pm fields in env
LIU Zhiwei
5
-0
/
+68
2022-01-21
target/riscv: Adjust csr write mask with XLEN
LIU Zhiwei
2
-5
/
+10
2022-01-21
target/riscv: Relax debug check for pm write
LIU Zhiwei
1
-0
/
+3
2022-01-21
target/riscv: Use gdb xml according to max mxlen
LIU Zhiwei
2
-24
/
+55
2022-01-21
target/riscv: Extend pc for runtime pc write
LIU Zhiwei
1
-3
/
+19
2022-01-21
target/riscv: Ignore the pc bits above XLEN
LIU Zhiwei
1
-1
/
+1
2022-01-21
target/riscv: Create xl field in env
LIU Zhiwei
5
-32
/
+46
2022-01-21
target/riscv: Sign extend pc for different XLEN
LIU Zhiwei
4
-9
/
+27
2022-01-21
target/riscv: Sign extend link reg for jal and jalr
LIU Zhiwei
2
-6
/
+2
2022-01-21
target/riscv: Don't save pc when exception return
LIU Zhiwei
3
-9
/
+6
2022-01-21
target/riscv: Adjust pmpcfg access with mxl
LIU Zhiwei
2
-8
/
+23
2022-01-21
target/riscv: rvv-1.0: Allow Zve32f extension to be turned on
Frank Chang
1
-0
/
+1
2022-01-21
target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns
Frank Chang
1
-0
/
+3
2022-01-21
target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns
Frank Chang
1
-0
/
+18
2022-01-21
target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns
Frank Chang
1
-0
/
+1
2022-01-21
target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns
Frank Chang
1
-0
/
+21
2022-01-21
target/riscv: rvv-1.0: Add Zve32f support for configuration insns
Frank Chang
1
-2
/
+2
2022-01-21
target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
Frank Chang
5
-4
/
+7
2022-01-21
target/riscv: rvv-1.0: Allow Zve64f extension to be turned on
Frank Chang
1
-0
/
+1
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns
Frank Chang
1
-3
/
+6
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns
Frank Chang
1
-7
/
+25
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns
Frank Chang
1
-1
/
+2
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns
Frank Chang
1
-10
/
+31
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns
Frank Chang
1
-2
/
+25
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns
Frank Chang
1
-6
/
+33
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for load and store insns
Frank Chang
1
-4
/
+15
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for configuration insns
Frank Chang
1
-2
/
+4
2022-01-21
target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
Frank Chang
5
-2
/
+16
2022-01-21
target/riscv: Support virtual time context synchronization
Yifei Jiang
1
-0
/
+30
2022-01-21
target/riscv: Implement virtual time adjusting with vm state changing
Yifei Jiang
1
-0
/
+15
2022-01-21
target/riscv: Add kvm_riscv_get/put_regs_timer
Yifei Jiang
2
-0
/
+79
2022-01-21
target/riscv: Add host cpu type
Yifei Jiang
2
-0
/
+16
2022-01-21
target/riscv: Handle KVM_EXIT_RISCV_SBI exit
Yifei Jiang
2
-1
/
+113
2022-01-21
target/riscv: Support setting external interrupt by KVM
Yifei Jiang
4
-1
/
+28
2022-01-21
target/riscv: Support start kernel directly by KVM
Yifei Jiang
6
-1
/
+75
2022-01-21
target/riscv: Implement kvm_arch_put_registers
Yifei Jiang
1
-1
/
+103
2022-01-21
target/riscv: Implement kvm_arch_get_registers
Yifei Jiang
1
-1
/
+111
2022-01-21
target/riscv: Implement function kvm_arch_init_vcpu
Yifei Jiang
1
-1
/
+33
2022-01-21
target/riscv: Add target/riscv/kvm.c to place the public kvm interface
Yifei Jiang
2
-0
/
+134
2022-01-20
hw/arm/virt: KVM: Enable PAuth when supported by the host
Marc Zyngier
4
-15
/
+54
2022-01-19
Merge remote-tracking branch 'remotes/thuth-gitlab/tags/pull-request-2022-01-...
Peter Maydell
6
-87
/
+58
2022-01-18
s390x: sigp: Reorder the SIGP STOP code
Eric Farman
1
-4
/
+8
2022-01-18
target/ppc: Fix 7448 support
Cédric Le Goater
1
-4
/
+4
2022-01-18
target/ppc: Finish removal of 401/403 CPUs
Cédric Le Goater
6
-51
/
+1
2022-01-18
target/ppc: Remove last user of .load_state_old
Cédric Le Goater
1
-112
/
+0
2022-01-17
target/s390x: Fix shifting 32-bit values for more than 31 bits
Ilya Leoshkevich
5
-80
/
+45
2022-01-17
target/s390x: Fix cc_calc_sla_64() missing overflows
Ilya Leoshkevich
1
-1
/
+1
[prev]
[next]