diff options
author | Cédric Le Goater <clg@kaod.org> | 2022-01-18 12:56:30 +0100 |
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committer | Cédric Le Goater <clg@kaod.org> | 2022-01-18 12:56:30 +0100 |
commit | 328c95fc7d005380e970383a79e30bb4d4acddd2 (patch) | |
tree | 6919cc1e3dea032499ee76824640cf07f6c24583 /target | |
parent | 8f91aca7ff0044b77f04c745ab1572f1e40e2b2f (diff) | |
download | qemu-328c95fc7d005380e970383a79e30bb4d4acddd2.zip qemu-328c95fc7d005380e970383a79e30bb4d4acddd2.tar.gz qemu-328c95fc7d005380e970383a79e30bb4d4acddd2.tar.bz2 |
target/ppc: Finish removal of 401/403 CPUs
Commit c8f49e6b938e ("target/ppc: remove 401/403 CPUs") left a few
things behind.
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220117091541.1615807-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220118104150.1899661-3-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'target')
-rw-r--r-- | target/ppc/cpu-models.c | 1 | ||||
-rw-r--r-- | target/ppc/cpu.h | 1 | ||||
-rw-r--r-- | target/ppc/helper.h | 1 | ||||
-rw-r--r-- | target/ppc/machine.c | 24 | ||||
-rw-r--r-- | target/ppc/misc_helper.c | 9 | ||||
-rw-r--r-- | target/ppc/translate.c | 16 |
6 files changed, 1 insertions, 51 deletions
diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c index c9fcb61..96fec9c 100644 --- a/target/ppc/cpu-models.c +++ b/target/ppc/cpu-models.c @@ -750,7 +750,6 @@ /* PowerPC CPU aliases */ PowerPCCPUAlias ppc_cpu_aliases[] = { - { "403", "403gc" }, { "405", "405d4" }, { "405cr", "405crc" }, { "405gp", "405gpd" }, diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f99cd0e..2560b70 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1133,7 +1133,6 @@ struct CPUPPCState { int nb_pids; /* Number of available PID registers */ int tlb_type; /* Type of TLB we're dealing with */ ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */ - target_ulong pb[4]; /* 403 dedicated access protection registers */ bool tlb_dirty; /* Set to non-zero when modifying TLB */ bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */ uint32_t tlb_need_flush; /* Delayed flush needed */ diff --git a/target/ppc/helper.h b/target/ppc/helper.h index f9c72dc..d318837 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -703,7 +703,6 @@ DEF_HELPER_FLAGS_2(store_hdecr, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(store_vtb, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(store_tbu40, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_2(store_hid0_601, void, env, tl) -DEF_HELPER_3(store_403_pbr, void, env, i32, tl) DEF_HELPER_FLAGS_1(load_40x_pit, TCG_CALL_NO_RWG, tl, env) DEF_HELPER_FLAGS_2(store_40x_pit, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(store_40x_tcr, TCG_CALL_NO_RWG, void, env, tl) diff --git a/target/ppc/machine.c b/target/ppc/machine.c index df54738..733a22d 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -598,25 +598,6 @@ static bool tlbemb_needed(void *opaque) return env->nb_tlb && (env->tlb_type == TLB_EMB); } -static bool pbr403_needed(void *opaque) -{ - PowerPCCPU *cpu = opaque; - uint32_t pvr = cpu->env.spr[SPR_PVR]; - - return (pvr & 0xffff0000) == 0x00200000; -} - -static const VMStateDescription vmstate_pbr403 = { - .name = "cpu/pbr403", - .version_id = 1, - .minimum_version_id = 1, - .needed = pbr403_needed, - .fields = (VMStateField[]) { - VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4), - VMSTATE_END_OF_LIST() - }, -}; - static const VMStateDescription vmstate_tlbemb = { .name = "cpu/tlb6xx", .version_id = 1, @@ -628,13 +609,8 @@ static const VMStateDescription vmstate_tlbemb = { env.nb_tlb, vmstate_tlbemb_entry, ppcemb_tlb_t), - /* 403 protection registers */ VMSTATE_END_OF_LIST() }, - .subsections = (const VMStateDescription*[]) { - &vmstate_pbr403, - NULL - } }; static const VMStateDescription vmstate_tlbmas_entry = { diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index c33f5f3..1bcefa7 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -226,15 +226,6 @@ void helper_store_hid0_601(CPUPPCState *env, target_ulong val) } } -void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value) -{ - if (likely(env->pb[num] != value)) { - env->pb[num] = value; - /* Should be optimized */ - tlb_flush(env_cpu(env)); - } -} - void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val) { /* Bits 26 & 27 affect single-stepping. */ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 4023220..9d2adc0 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -911,22 +911,8 @@ void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) } #endif -/* PowerPC 403 specific registers */ -/* PBL1 / PBU1 / PBL2 / PBU2 */ +/* PIR */ #if !defined(CONFIG_USER_ONLY) -void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn) -{ - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, - offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1])); -} - -void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn) -{ - TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); - gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); - tcg_temp_free_i32(t0); -} - void spr_write_pir(DisasContext *ctx, int sprn, int gprn) { TCGv t0 = tcg_temp_new(); |