riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-10-23	Merge remote-tracking branch 'remotes/vivier/tags/trivial-branch-for-6.2-pull...	Richard Henderson	1	-5/+1
2021-10-22	disas/nios2: Simplify endianess conversion	Philippe Mathieu-Daudé	1	-5/+1
2021-10-22	target/riscv: Compute mstatus.sd on demand	Richard Henderson	3	-20/+25
2021-10-22	target/riscv: Use riscv_csrrw_debug for cpu_dump	Richard Henderson	1	-44/+45
2021-10-22	target/riscv: Use gen_shift*_per_ol for RVB, RVI	Richard Henderson	3	-52/+97
2021-10-22	target/riscv: Use gen_unary_per_ol for RVB	Richard Henderson	2	-17/+32
2021-10-22	target/riscv: Adjust trans_rev8_32 for riscv64	Richard Henderson	1	-1/+6
2021-10-22	target/riscv: Use gen_arith_per_ol for RVM	Richard Henderson	2	-3/+39
2021-10-22	target/riscv: Replace DisasContext.w with DisasContext.ol	Richard Henderson	4	-43/+62
2021-10-22	target/riscv: Replace is_32bit with get_xl/get_xlen	Richard Henderson	1	-14/+17
2021-10-22	target/riscv: Properly check SEW in amo_op	Richard Henderson	1	-12/+14
2021-10-22	target/riscv: Use REQUIRE_64BIT in amo_check64	Richard Henderson	1	-1/+2
2021-10-22	target/riscv: Add MXL/SXL/UXL to TB_FLAGS	Richard Henderson	5	-1/+47
2021-10-22	target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl	Richard Henderson	6	-32/+43
2021-10-22	target/riscv: Split misa.mxl and misa.ext	Richard Henderson	6	-67/+98
2021-10-22	target/riscv: Create RISCVMXL enumeration	Richard Henderson	1	-3/+5
2021-10-22	target/riscv: Move cpu_get_tb_cpu_state out of line	Richard Henderson	2	-45/+48
2021-10-22	target/riscv: Organise the CPU properties	Alistair Francis	1	-7/+10
2021-10-22	target/riscv: Remove some unused macros	Alistair Francis	1	-8/+0
2021-10-22	target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh	Frank Chang	2	-8/+8
2021-10-22	target/riscv: Fix orc.b implementation	Philipp Tomsich	1	-5/+8
2021-10-22	target/riscv: line up all of the registers in the info register dump	Travis Geiselbrecht	1	-5/+5
2021-10-22	target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v	Frank Chang	1	-1/+2
2021-10-21	target/ppc: adding user read/write functions for PMCs	Daniel Henrique Barboza	3	-6/+80
2021-10-21	target/ppc: add user read/write functions for MMCR2	Daniel Henrique Barboza	4	-12/+99
2021-10-21	target/ppc: add user read/write functions for MMCR0	Gustavo Romero	5	-1/+128
2021-10-21	target/ppc: add MMCR0 PMCC bits to hflags	Daniel Henrique Barboza	3	-0/+16
2021-10-21	target/ppc: Filter mtmsr[d] input before setting MSR	Matheus Ferst	2	-33/+41
2021-10-21	target/ppc: Fix XER access in monitor	Matheus Ferst	1	-1/+8
2021-10-21	linux-user: Fix XER access in ppc version of elf_core_copy_regs	Matheus Ferst	2	-2/+2
2021-10-21	target/ppc: Fix XER access in gdbstub	Matheus Ferst	1	-4/+4
2021-10-21	target/ppc: Use tcg_constant_i64() in gen_brh()	Philippe Mathieu-Daudé	1	-5/+3
2021-10-21	target/ppc: Use tcg_constant_i32() in gen_setb()	Philippe Mathieu-Daudé	1	-6/+2
2021-10-18	target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn()	Philippe Mathieu-Daudé	1	-4/+0
2021-10-18	target/mips: Fix DEXTRV_S.H DSP opcode	Philippe Mathieu-Daudé	1	-2/+1
2021-10-18	target/mips: Use tcg_constant_tl() in gen_compute_compact_branch()	Philippe Mathieu-Daudé	1	-3/+1
2021-10-18	target/mips: Use explicit extract32() calls in gen_msa_i5()	Philippe Mathieu-Daudé	1	-7/+4
2021-10-18	target/mips: Use tcg_constant_i32() in gen_msa_3rf()	Philippe Mathieu-Daudé	1	-9/+14
2021-10-18	target/mips: Use tcg_constant_i32() in gen_msa_2r()	Philippe Mathieu-Daudé	1	-3/+2
2021-10-18	target/mips: Use tcg_constant_i32() in gen_msa_2rf()	Philippe Mathieu-Daudé	1	-2/+1
2021-10-18	target/mips: Use tcg_constant_i32() in gen_msa_elm_df()	Philippe Mathieu-Daudé	1	-2/+1
2021-10-18	target/mips: Remove unused register from MSA 2R/2RF instruction format	Philippe Mathieu-Daudé	1	-6/+0
2021-10-17	target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6	Philippe Mathieu-Daudé	1	-0/+6
2021-10-15	target/xtensa: Drop check for singlestep_enabled	Richard Henderson	1	-17/+8
2021-10-15	target/tricore: Drop check for singlestep_enabled	Richard Henderson	3	-21/+1
2021-10-15	target/sh4: Drop check for singlestep_enabled	Richard Henderson	3	-17/+3
2021-10-15	target/s390x: Drop check for singlestep_enabled	Richard Henderson	1	-6/+2
2021-10-15	target/rx: Drop checks for singlestep_enabled	Richard Henderson	3	-19/+2
2021-10-15	target/riscv: Remove exit_tb and lookup_and_goto_ptr	Richard Henderson	4	-34/+7
2021-10-15	target/riscv: Remove dead code after exception	Richard Henderson	1	-5/+1