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| author | Richard Henderson <richard.henderson@linaro.org> | 2021-10-19 20:16:56 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair@alistair23.me> | 2021-10-22 07:47:51 +1000 |
| commit | 99bc874fb3a0709c36ae4e594a1262ce1660e698 (patch) | |
| tree | c1f5ff95c30c2f77366d73413d4e5836fecd4e1d /target | |
| parent | 53677acf25afa8e529d7f81a6ae9a03d15c72713 (diff) | |
| download | qemu-99bc874fb3a0709c36ae4e594a1262ce1660e698.zip qemu-99bc874fb3a0709c36ae4e594a1262ce1660e698.tar.gz qemu-99bc874fb3a0709c36ae4e594a1262ce1660e698.tar.bz2 | |
target/riscv: Create RISCVMXL enumeration
Move the MXL_RV* defines to enumerators.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-3-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/cpu_bits.h | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 3aa2512..cffcd3a 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -364,9 +364,11 @@ #define MISA32_MXL 0xC0000000 #define MISA64_MXL 0xC000000000000000ULL -#define MXL_RV32 1 -#define MXL_RV64 2 -#define MXL_RV128 3 +typedef enum { + MXL_RV32 = 1, + MXL_RV64 = 2, + MXL_RV128 = 3, +} RISCVMXL; /* sstatus CSR bits */ #define SSTATUS_UIE 0x00000001 |